From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA6EFC4332F for ; Tue, 13 Dec 2022 17:58:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235629AbiLMR6H (ORCPT ); Tue, 13 Dec 2022 12:58:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236335AbiLMR6B (ORCPT ); Tue, 13 Dec 2022 12:58:01 -0500 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78FC41F62F; Tue, 13 Dec 2022 09:57:58 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id c66so18873583edf.5; Tue, 13 Dec 2022 09:57:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=f74flBhltkIF6Kyzm1psBFvXaiR1ZpsFYBiux/pnBP0=; b=h5saAjMhrH0HxaWeXItI+PASmkeSYJ2PQdO9BLbEOFZMfii8fwzQnWRsbK/4SKxc7s rD4KG/Q1ZPION2xh25FfyL8e0ZB2Qd2fzVMGloq3ccKc3fh7BhotnxOssEIU6NXTOmPw Ed0iTBqXWx2VVGJY2IcdbQFnpw0qfxiYeO5x4JEkEvIV37SnFXK3JBVkwiC/r04njS8y DeZAUot9otBwpYzTq8BRqdksVkGzl71NkXIVhCIZ99z1EG+3khhsYIauwGuirflTgh0V TCYybUkkwvY/s4CVK+hSzWpo0fEViGSEK8W+W0wklZBuO2soqu75jQ+l5cX7FKRhBJgT 3ohw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=f74flBhltkIF6Kyzm1psBFvXaiR1ZpsFYBiux/pnBP0=; b=i2BDavDhjQNQdURhqVmzR6+aovWcnNeWUaclauTtIYXpwnB535isAA4CYxs48KQBVF QFW1Gp8FXbxWxY5yxkKLMpoWvr/B0xP1CDNcz9oadwjHCfFeSKe73c7pAdTPx70w4lp6 zlQpC8/EmuJ16/Ey3BSNSkQfoYO0Eo9DUW3nAK9KIfBUePmEP2sWT3pY0sFsBWydVvUs MBEbNmRkPE99SI2t4I6X5xcROs4TN55EkVaFLObkygGOurJ3xpj1ZSDTY7inkhHvwMz8 TMEtO8nzlah2ziFfXqMnGCC6Ce+SdK6Th2MshOOoMKoHa1XgBix9MEHIbIhn7oxX4upl 6qog== X-Gm-Message-State: ANoB5plTu5Umg5e+l22/EDfEliMkZng608xJ+8WGgbBTQzmWTnjtZ+YG 0mWMLmoHwBGcsOoR8qsd11c71bub01ii/zukuLc= X-Google-Smtp-Source: AA0mqf5BkB6tOs9ZGs9+GqphqnUcCfvk0twwLhRnghScakJzu5AIhu6mkb8wvOOc7fcyfPZ5034mmUZ5ehkKT3Pvgc4= X-Received: by 2002:a05:6402:1f87:b0:468:7df:c38c with SMTP id c7-20020a0564021f8700b0046807dfc38cmr20457565edc.150.1670954276964; Tue, 13 Dec 2022 09:57:56 -0800 (PST) MIME-Version: 1.0 References: <20221212115505.36770-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221212115505.36770-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Tue, 13 Dec 2022 17:57:30 +0000 Message-ID: Subject: Re: [PATCH v5 4/6] riscv: mm: dma-noncoherent: Pass direction and operation to ALT_CMO_OP() To: Geert Uytterhoeven Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Magnus Damm , Heiko Stuebner , Conor Dooley , Samuel Holland , Guo Ren , Rob Herring , Krzysztof Kozlowski , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Tue, Dec 13, 2022 at 5:15 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Mon, Dec 12, 2022 at 12:55 PM Prabhakar wrote: > > From: Lad Prabhakar > > > > Pass direction and operation to ALT_CMO_OP() macro. > > > > Vendors might want to perform different operations based on the direction > > and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/ > > arch_dma_prep_coherent) so to handle such cases pass the direction and > > operation to ALT_CMO_OP() macro. This is in preparation for adding errata > > for the Andes CPU core. > > > > Signed-off-by: Lad Prabhakar > > Thanks for your patch! > > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" > > > > -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > > +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > > Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM > APIs") in riscv/for-next, there are two new users of this macro, > which need to be updated to (add two zeroes?). > Thanks for pointing that out, I'll rebase on for-next. I think -1 would be a better option than zeros. Cheers, Prabhakar From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25FC8C4332F for ; Tue, 13 Dec 2022 17:58:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ib9INYpIsORkmWkcNk1omL5VEtNAieg2mgL7aTj0mkA=; b=T1Ypze0uKFtxYj JKZt1ILq4IqlN2ydYRiHllvfktshRQK+JWZ8IivE8kjdDUJwHnyAtZGfWWYTw23kVuQe4wBTswFf2 VjENRK7iYx8bMouK3yYu8DtPWEgekcmT3FK1At4uwtJ7wx/ELFT4eXQ5KGRwPNmeVXcU1iY9eLFRe XNCga/pVcn8MBJpW6W6/hDY4khv9wUAEmT6plaTBQrLFXheaTIuqEy0Sn5KIb4IZUYdMQ/Po8puPD CshqOMtyaG/vbfsgqSag31iBqin5ZzjKqpV+PsR/e3oPigxyRqZp0A+QLmBwVSoJ3hMoeAOcc37Ik 8ZdVmJt1+El/RNOfoS4A==; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Geert, On Tue, Dec 13, 2022 at 5:15 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Mon, Dec 12, 2022 at 12:55 PM Prabhakar wrote: > > From: Lad Prabhakar > > > > Pass direction and operation to ALT_CMO_OP() macro. > > > > Vendors might want to perform different operations based on the direction > > and callbacks (arch_sync_dma_for_device/arch_sync_dma_for_cpu/ > > arch_dma_prep_coherent) so to handle such cases pass the direction and > > operation to ALT_CMO_OP() macro. This is in preparation for adding errata > > for the Andes CPU core. > > > > Signed-off-by: Lad Prabhakar > > Thanks for your patch! > > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -124,7 +124,7 @@ asm volatile(ALTERNATIVE( \ > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" > > > > -#define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > > +#define ALT_CMO_OP(_op, _start, _size, _cachesize, _dir, _ops) \ > > Since commit a49ab905a1fc8630 ("RISC-V: Implement arch specific PMEM > APIs") in riscv/for-next, there are two new users of this macro, > which need to be updated to (add two zeroes?). > Thanks for pointing that out, I'll rebase on for-next. I think -1 would be a better option than zeros. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv