* [PATCH 0/6] Add support for Renesas RZ/Five SoC
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/
riscv-ax45mp/
Patch series depends on:
-----------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/
cover/20220630100241.35233-1-samuel@sholland.org/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Below are the logs from Renesas RZ/Five SMARC EVK:
-------------------------------------------------
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # cat /proc/meminfo
MemTotal: 884132 kB
MemFree: 863292 kB
MemAvailable: 860880 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 1412 kB
Inactive: 456 kB
Active(anon): 1412 kB
Inactive(anon): 456 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 0 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 108 kB
Mapped: 1136 kB
Shmem: 1796 kB
KReclaimable: 6424 kB
Slab: 12548 kB
SReclaimable: 6424 kB
SUnreclaim: 6124 kB
KernelStack: 844 kB
PageTables: 32 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 442064 kB
Committed_AS: 2388 kB
VmallocTotal: 67108864 kB
VmallocUsed: 860 kB
VmallocChunk: 0 kB
Percpu: 84 kB
CmaTotal: 0 kB
CmaFree: 0 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 1 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 72 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 10193 RISC-V INTC 5 Edge riscv-timer
6: 14 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ #
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g043
family: RZ/Five
soc_id: r9a07g043
revision: 0
/ #
Cheers,
Prabhakar
Lad Prabhakar (6):
dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five
SoC and SMARC EVK
RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
.../devicetree/bindings/arm/renesas.yaml | 9 ++
.../devicetree/bindings/riscv/cpus.yaml | 11 +-
.../devicetree/bindings/riscv/renesas.yaml | 49 +++++++
arch/riscv/Kconfig.socs | 14 ++
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 ++++++++++++++++++
6 files changed, 200 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
--
2.17.1
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH 0/6] Add support for Renesas RZ/Five SoC
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/
riscv-ax45mp/
Patch series depends on:
-----------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/
cover/20220630100241.35233-1-samuel@sholland.org/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Below are the logs from Renesas RZ/Five SMARC EVK:
-------------------------------------------------
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # cat /proc/meminfo
MemTotal: 884132 kB
MemFree: 863292 kB
MemAvailable: 860880 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 1412 kB
Inactive: 456 kB
Active(anon): 1412 kB
Inactive(anon): 456 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 0 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 108 kB
Mapped: 1136 kB
Shmem: 1796 kB
KReclaimable: 6424 kB
Slab: 12548 kB
SReclaimable: 6424 kB
SUnreclaim: 6124 kB
KernelStack: 844 kB
PageTables: 32 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 442064 kB
Committed_AS: 2388 kB
VmallocTotal: 67108864 kB
VmallocUsed: 860 kB
VmallocChunk: 0 kB
Percpu: 84 kB
CmaTotal: 0 kB
CmaFree: 0 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 1 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 72 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 10193 RISC-V INTC 5 Edge riscv-timer
6: 14 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ #
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g043
family: RZ/Five
soc_id: r9a07g043
revision: 0
/ #
Cheers,
Prabhakar
Lad Prabhakar (6):
dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five
SoC and SMARC EVK
RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
.../devicetree/bindings/arm/renesas.yaml | 9 ++
.../devicetree/bindings/riscv/cpus.yaml | 11 +-
.../devicetree/bindings/riscv/renesas.yaml | 49 +++++++
arch/riscv/Kconfig.socs | 14 ++
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 ++++++++++++++++++
6 files changed, 200 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
(RISC-V arch).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index ff80152f092f..f646df1a23af 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
+# We want to ignore this schema if the board is of RISC-V arch
+select:
+ not:
+ properties:
+ compatible:
+ contains:
+ items:
+ - const: renesas,r9a07g043f01
+
properties:
$nodename:
const: '/'
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
(RISC-V arch).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index ff80152f092f..f646df1a23af 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
+# We want to ignore this schema if the board is of RISC-V arch
+select:
+ not:
+ properties:
+ compatible:
+ contains:
+ items:
+ - const: renesas,r9a07g043f01
+
properties:
$nodename:
const: '/'
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..ffa8f12c29af 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..ffa8f12c29af 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index ffa8f12c29af..e941b2821d23 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index ffa8f12c29af..e941b2821d23 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
new file mode 100644
index 000000000000..f72f8aea6a82
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/renesas.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/Five Platform Device Tree Bindings
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
+select:
+ not:
+ properties:
+ compatible:
+ contains:
+ items:
+ - const: renesas,smarc-evk
+ - enum:
+ - renesas,r9a07g043u11
+ - renesas,r9a07g043u12
+ - renesas,r9a07g044c1
+ - renesas,r9a07g044c2
+ - renesas,r9a07g044l1
+ - renesas,r9a07g044l2
+ - renesas,r9a07g054l1
+ - renesas,r9a07g054l2
+ - enum:
+ - renesas,r9a07g043
+ - renesas,r9a07g044
+ - renesas,r9a07g054
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: RZ/Five (R9A07G043)
+ items:
+ - enum:
+ - renesas,smarc-evk # SMARC EVK
+ - const: renesas,r9a07g043f01
+ - const: renesas,r9a07g043
+
+additionalProperties: true
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
new file mode 100644
index 000000000000..f72f8aea6a82
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/renesas.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/Five Platform Device Tree Bindings
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
+select:
+ not:
+ properties:
+ compatible:
+ contains:
+ items:
+ - const: renesas,smarc-evk
+ - enum:
+ - renesas,r9a07g043u11
+ - renesas,r9a07g043u12
+ - renesas,r9a07g044c1
+ - renesas,r9a07g044c2
+ - renesas,r9a07g044l1
+ - renesas,r9a07g044l2
+ - renesas,r9a07g054l1
+ - renesas,r9a07g054l2
+ - enum:
+ - renesas,r9a07g043
+ - renesas,r9a07g044
+ - renesas,r9a07g054
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: RZ/Five (R9A07G043)
+ items:
+ - enum:
+ - renesas,smarc-evk # SMARC EVK
+ - const: renesas,r9a07g043f01
+ - const: renesas,r9a07g043
+
+additionalProperties: true
+
+...
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
(R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
of the Renesas drivers depend on this config option.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig.socs | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..91b7f38b77a8 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
endif # SOC_CANAAN
+config ARCH_RENESAS
+ bool
+ select GPIOLIB
+ select PINCTRL
+ select SOC_BUS
+
+config SOC_RENESAS_RZFIVE
+ bool "Renesas RZ/Five SoC"
+ select ARCH_R9A07G043
+ select ARCH_RENESAS
+ select RESET_CONTROLLER
+ help
+ This enables support for Renesas RZ/Five SoC.
+
endmenu # "SoC selection"
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
(R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
of the Renesas drivers depend on this config option.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/Kconfig.socs | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..91b7f38b77a8 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
endif # SOC_CANAAN
+config ARCH_RENESAS
+ bool
+ select GPIOLIB
+ select PINCTRL
+ select SOC_BUS
+
+config SOC_RENESAS_RZFIVE
+ bool "Renesas RZ/Five SoC"
+ select ARCH_R9A07G043
+ select ARCH_RENESAS
+ select RESET_CONTROLLER
+ help
+ This enables support for Renesas RZ/Five SoC.
+
endmenu # "SoC selection"
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:06 ` Lad Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..6e0b640c6c7f
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ ax45mp: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+ <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+ <414 IRQ_TYPE_LEVEL_HIGH>,
+ <415 IRQ_TYPE_LEVEL_HIGH>,
+ <413 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g043-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 152>;
+ clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_GPIO_RSTN>,
+ <&cpg R9A07G043_GPIO_PORT_RESETN>,
+ <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+ };
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <543>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-26 18:06 ` Lad Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad Prabhakar @ 2022-07-26 18:06 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).
Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..6e0b640c6c7f
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ ax45mp: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+ <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+ <414 IRQ_TYPE_LEVEL_HIGH>,
+ <415 IRQ_TYPE_LEVEL_HIGH>,
+ <413 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g043-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 152>;
+ clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_GPIO_RSTN>,
+ <&cpg R9A07G043_GPIO_PORT_RESETN>,
+ <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+ };
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <543>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+ };
+};
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:25 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:25 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
Hey,
Saw your other binding patches coming in earlier & wondered if
this would show up today ;)
On 26/07/2022 19:06, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
Missing files? Where is your Makefile for this directory?
Or the board dts?
Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> new file mode 100644
> index 000000000000..6e0b640c6c7f
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
Including arm gic stuff on riscv? That seems a bit odd to me.
> +#include <dt-bindings/clock/r9a07g043-cpg.h>
> +
> +/ {
> + compatible = "renesas,r9a07g043";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
Why add the empty value in that case?
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + ax45mp: cpu@0 {
> + compatible = "andestech,ax45mp", "riscv";
> + device_type = "cpu";
> + reg = <0x0>;
> + status = "okay";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <0x40>;
> + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + scif0: serial@1004b800 {
> + compatible = "renesas,scif-r9a07g043",
> + "renesas,scif-r9a07g044";
> + reg = <0 0x1004b800 0 0x400>;
> + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> + <414 IRQ_TYPE_LEVEL_HIGH>,
> + <415 IRQ_TYPE_LEVEL_HIGH>,
> + <413 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi",
> + "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> + status = "disabled";
> + };
> +
> + cpg: clock-controller@11010000 {
> + compatible = "renesas,r9a07g043-cpg";
> + reg = <0 0x11010000 0 0x10000>;
> + clocks = <&extal_clk>;
> + clock-names = "extal";
> + #clock-cells = <2>;
> + #reset-cells = <1>;
> + #power-domain-cells = <0>;
> + };
> +
> + sysc: system-controller@11020000 {
> + compatible = "renesas,r9a07g043-sysc";
> + reg = <0 0x11020000 0 0x10000>;
> + status = "disabled";
> + };
> +
> + pinctrl: pinctrl@11030000 {
> + compatible = "renesas,r9a07g043-pinctrl";
> + reg = <0 0x11030000 0 0x10000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + gpio-ranges = <&pinctrl 0 0 152>;
> + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_GPIO_RSTN>,
> + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> + };
> +
> + plic: interrupt-controller@12c00000 {
> + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + riscv,ndev = <543>;
> + interrupt-controller;
> + reg = <0x0 0x12c00000 0 0x400000>;
Does reg not usually get sorted after compatible?
For consistency in this file it should at least.
Thanks,
Conor.
> + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> + };
> + };
> +};
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-26 18:25 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:25 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
Hey,
Saw your other binding patches coming in earlier & wondered if
this would show up today ;)
On 26/07/2022 19:06, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
Missing files? Where is your Makefile for this directory?
Or the board dts?
Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> new file mode 100644
> index 000000000000..6e0b640c6c7f
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
Including arm gic stuff on riscv? That seems a bit odd to me.
> +#include <dt-bindings/clock/r9a07g043-cpg.h>
> +
> +/ {
> + compatible = "renesas,r9a07g043";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
Why add the empty value in that case?
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + ax45mp: cpu@0 {
> + compatible = "andestech,ax45mp", "riscv";
> + device_type = "cpu";
> + reg = <0x0>;
> + status = "okay";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <0x40>;
> + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + scif0: serial@1004b800 {
> + compatible = "renesas,scif-r9a07g043",
> + "renesas,scif-r9a07g044";
> + reg = <0 0x1004b800 0 0x400>;
> + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> + <414 IRQ_TYPE_LEVEL_HIGH>,
> + <415 IRQ_TYPE_LEVEL_HIGH>,
> + <413 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi",
> + "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> + status = "disabled";
> + };
> +
> + cpg: clock-controller@11010000 {
> + compatible = "renesas,r9a07g043-cpg";
> + reg = <0 0x11010000 0 0x10000>;
> + clocks = <&extal_clk>;
> + clock-names = "extal";
> + #clock-cells = <2>;
> + #reset-cells = <1>;
> + #power-domain-cells = <0>;
> + };
> +
> + sysc: system-controller@11020000 {
> + compatible = "renesas,r9a07g043-sysc";
> + reg = <0 0x11020000 0 0x10000>;
> + status = "disabled";
> + };
> +
> + pinctrl: pinctrl@11030000 {
> + compatible = "renesas,r9a07g043-pinctrl";
> + reg = <0 0x11030000 0 0x10000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + gpio-ranges = <&pinctrl 0 0 152>;
> + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_GPIO_RSTN>,
> + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> + };
> +
> + plic: interrupt-controller@12c00000 {
> + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + riscv,ndev = <543>;
> + interrupt-controller;
> + reg = <0x0 0x12c00000 0 0x400000>;
Does reg not usually get sorted after compatible?
For consistency in this file it should at least.
Thanks,
Conor.
> + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> + };
> + };
> +};
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:49 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:49 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:06, Lad Prabhakar wrote:
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/Kconfig.socs | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
> endif # SOC_CANAAN
>
> +config ARCH_RENESAS
Hmm, I guess since it is very late in the day for v5.20 and there
appear to be some issues with the SOC_ symbol breaking the dts build
anyway, this is likely to be v5.21 content anyway...
...but I would be wary of adding ARCH_ symbols from ARM archs prior
to figuring out what we actually want symbols in Kconfig.socs to
actually at LPC or w/e. Palmer?
> + bool
> + select GPIOLIB
> + select PINCTRL
> + select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE
I would like to see this added to the default defconfig so that
it has dtbs_check coverage by default.
Thanks,
Conor.
> + bool "Renesas RZ/Five SoC"
> + select ARCH_R9A07G043
> + select ARCH_RENESAS
> + select RESET_CONTROLLER
> + help
> + This enables support for Renesas RZ/Five SoC.
> +
> endmenu # "SoC selection"
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
@ 2022-07-26 18:49 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:49 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:06, Lad Prabhakar wrote:
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/Kconfig.socs | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
> endif # SOC_CANAAN
>
> +config ARCH_RENESAS
Hmm, I guess since it is very late in the day for v5.20 and there
appear to be some issues with the SOC_ symbol breaking the dts build
anyway, this is likely to be v5.21 content anyway...
...but I would be wary of adding ARCH_ symbols from ARM archs prior
to figuring out what we actually want symbols in Kconfig.socs to
actually at LPC or w/e. Palmer?
> + bool
> + select GPIOLIB
> + select PINCTRL
> + select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE
I would like to see this added to the default defconfig so that
it has dtbs_check coverage by default.
Thanks,
Conor.
> + bool "Renesas RZ/Five SoC"
> + select ARCH_R9A07G043
> + select ARCH_RENESAS
> + select RESET_CONTROLLER
> + help
> + This enables support for Renesas RZ/Five SoC.
> +
> endmenu # "SoC selection"
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-26 18:51 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:51 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:06, Lad Prabhakar wrote:
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> riscv-ax45mp/
>
> Patch series depends on:
> -----------------------
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> 20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> cover/20220630100241.35233-1-samuel@sholland.org/
>
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
FYI, your mail client or w/e wrapped these links and none of
them work properly :(
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC
@ 2022-07-26 18:51 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:51 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:06, Lad Prabhakar wrote:
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> riscv-ax45mp/
>
> Patch series depends on:
> -----------------------
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> 20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> cover/20220630100241.35233-1-samuel@sholland.org/
>
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> 20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
FYI, your mail client or w/e wrapped these links and none of
them work properly :(
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-26 18:25 ` Conor.Dooley
@ 2022-07-26 18:53 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:53 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:25, Conor.Dooley@microchip.com wrote:
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>> Single).
>>
>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>> used to boot via initramfs on RZ/Five SMARC EVK:
>> - AX45MP CPU
>> - CPG
>> - PINCTRL
>> - PLIC
>> - SCIF0
>> - SYSC
>>
>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> ---
>> arch/riscv/boot/dts/Makefile | 1 +
>> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
FWIW, it breaks the dts build too even disabled b/c of the missing
Makefile.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-26 18:53 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-26 18:53 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou
Cc: anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
prabhakar.csengg, biju.das.jz
On 26/07/2022 19:25, Conor.Dooley@microchip.com wrote:
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>> Single).
>>
>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>> used to boot via initramfs on RZ/Five SMARC EVK:
>> - AX45MP CPU
>> - CPG
>> - PINCTRL
>> - PLIC
>> - SCIF0
>> - SYSC
>>
>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> ---
>> arch/riscv/boot/dts/Makefile | 1 +
>> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
FWIW, it breaks the dts build too even disabled b/c of the missing
Makefile.
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC
2022-07-26 18:51 ` Conor.Dooley
@ 2022-07-27 8:00 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:00 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Tue, Jul 26, 2022 at 7:51 PM <Conor.Dooley@microchip.com> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Useful links:
> > -------------
> > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> > rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> > andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> >
> > [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> > riscv-ax45mp/
> >
> > Patch series depends on:
> > -----------------------
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> > 20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> > cover/20220630100241.35233-1-samuel@sholland.org/
> >
> > [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> FYI, your mail client or w/e wrapped these links and none of
> them work properly :(
>
Sorry I had wrapped them around.
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220630100241.35233-1-samuel@sholland.org/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC
@ 2022-07-27 8:00 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:00 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Tue, Jul 26, 2022 at 7:51 PM <Conor.Dooley@microchip.com> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Useful links:
> > -------------
> > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> > rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> > andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> >
> > [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> > riscv-ax45mp/
> >
> > Patch series depends on:
> > -----------------------
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> > 20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> > cover/20220630100241.35233-1-samuel@sholland.org/
> >
> > [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >
> > [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > 20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> FYI, your mail client or w/e wrapped these links and none of
> them work properly :(
>
Sorry I had wrapped them around.
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220722141506.20171-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220630100241.35233-1-samuel@sholland.org/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726174929.950-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220726175315.1147-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-26 18:25 ` Conor.Dooley
@ 2022-07-27 8:09 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:09 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Tue, Jul 26, 2022 at 7:25 PM <Conor.Dooley@microchip.com> wrote:
>
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
:)
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
My plan was to get the initial minimal SoC DTSi and then later
gradually add the board DTS, but it looks like I'll have to include it
along with this series.
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
I shall include the Makefile and boards dts in v2
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..6e0b640c6c7f
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
>
> Including arm gic stuff on riscv? That seems a bit odd to me.
>
Ouch this needs to be replaced with irq.h (required for IRQ_TYPE_LEVEL_* flags)
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a07g043";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
>
> Why add the empty value in that case?
>
For ARM64 SoC DTSI we use the above approach so f Iollowed the same,
but you are right this can be dropped.
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + ax45mp: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc: soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scif0: serial@1004b800 {
> > + compatible = "renesas,scif-r9a07g043",
> > + "renesas,scif-r9a07g044";
> > + reg = <0 0x1004b800 0 0x400>;
> > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > + <414 IRQ_TYPE_LEVEL_HIGH>,
> > + <415 IRQ_TYPE_LEVEL_HIGH>,
> > + <413 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eri", "rxi", "txi",
> > + "bri", "dri", "tei";
> > + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > + clock-names = "fck";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > + status = "disabled";
> > + };
> > +
> > + cpg: clock-controller@11010000 {
> > + compatible = "renesas,r9a07g043-cpg";
> > + reg = <0 0x11010000 0 0x10000>;
> > + clocks = <&extal_clk>;
> > + clock-names = "extal";
> > + #clock-cells = <2>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + sysc: system-controller@11020000 {
> > + compatible = "renesas,r9a07g043-sysc";
> > + reg = <0 0x11020000 0 0x10000>;
> > + status = "disabled";
> > + };
> > +
> > + pinctrl: pinctrl@11030000 {
> > + compatible = "renesas,r9a07g043-pinctrl";
> > + reg = <0 0x11030000 0 0x10000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + gpio-ranges = <&pinctrl 0 0 152>;
> > + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_GPIO_RSTN>,
> > + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > + };
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <543>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
>
> Does reg not usually get sorted after compatible?
> For consistency in this file it should at least.
>
Agreed will fix that.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-27 8:09 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:09 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Tue, Jul 26, 2022 at 7:25 PM <Conor.Dooley@microchip.com> wrote:
>
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
:)
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
My plan was to get the initial minimal SoC DTSi and then later
gradually add the board DTS, but it looks like I'll have to include it
along with this series.
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
I shall include the Makefile and boards dts in v2
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..6e0b640c6c7f
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
>
> Including arm gic stuff on riscv? That seems a bit odd to me.
>
Ouch this needs to be replaced with irq.h (required for IRQ_TYPE_LEVEL_* flags)
> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a07g043";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
>
> Why add the empty value in that case?
>
For ARM64 SoC DTSI we use the above approach so f Iollowed the same,
but you are right this can be dropped.
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + ax45mp: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc: soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scif0: serial@1004b800 {
> > + compatible = "renesas,scif-r9a07g043",
> > + "renesas,scif-r9a07g044";
> > + reg = <0 0x1004b800 0 0x400>;
> > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > + <414 IRQ_TYPE_LEVEL_HIGH>,
> > + <415 IRQ_TYPE_LEVEL_HIGH>,
> > + <413 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eri", "rxi", "txi",
> > + "bri", "dri", "tei";
> > + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > + clock-names = "fck";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > + status = "disabled";
> > + };
> > +
> > + cpg: clock-controller@11010000 {
> > + compatible = "renesas,r9a07g043-cpg";
> > + reg = <0 0x11010000 0 0x10000>;
> > + clocks = <&extal_clk>;
> > + clock-names = "extal";
> > + #clock-cells = <2>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + sysc: system-controller@11020000 {
> > + compatible = "renesas,r9a07g043-sysc";
> > + reg = <0 0x11020000 0 0x10000>;
> > + status = "disabled";
> > + };
> > +
> > + pinctrl: pinctrl@11030000 {
> > + compatible = "renesas,r9a07g043-pinctrl";
> > + reg = <0 0x11030000 0 0x10000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + gpio-ranges = <&pinctrl 0 0 152>;
> > + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_GPIO_RSTN>,
> > + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > + };
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <543>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
>
> Does reg not usually get sorted after compatible?
> For consistency in this file it should at least.
>
Agreed will fix that.
Cheers,
Prabhakar
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
2022-07-26 18:49 ` Conor.Dooley
@ 2022-07-27 8:19 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:19 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
Thank you for the review.
On Tue, Jul 26, 2022 at 7:49 PM <Conor.Dooley@microchip.com> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> > (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> > of the Renesas drivers depend on this config option.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/Kconfig.socs | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..91b7f38b77a8 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> > endif # SOC_CANAAN
> >
> > +config ARCH_RENESAS
>
> Hmm, I guess since it is very late in the day for v5.20 and there
> appear to be some issues with the SOC_ symbol breaking the dts build
> anyway, this is likely to be v5.21 content anyway...
>
I was targeting this for v5.21 ;)
> ...but I would be wary of adding ARCH_ symbols from ARM archs prior
> to figuring out what we actually want symbols in Kconfig.socs to
> actually at LPC or w/e. Palmer?
>
> > + bool
> > + select GPIOLIB
> > + select PINCTRL
> > + select SOC_BUS
> > +
> > +config SOC_RENESAS_RZFIVE
>
> I would like to see this added to the default defconfig so that
> it has dtbs_check coverage by default.
>
Agreed, I will include it in the next version.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
@ 2022-07-27 8:19 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:19 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
Thank you for the review.
On Tue, Jul 26, 2022 at 7:49 PM <Conor.Dooley@microchip.com> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> > (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> > of the Renesas drivers depend on this config option.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/Kconfig.socs | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..91b7f38b77a8 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> > endif # SOC_CANAAN
> >
> > +config ARCH_RENESAS
>
> Hmm, I guess since it is very late in the day for v5.20 and there
> appear to be some issues with the SOC_ symbol breaking the dts build
> anyway, this is likely to be v5.21 content anyway...
>
I was targeting this for v5.21 ;)
> ...but I would be wary of adding ARCH_ symbols from ARM archs prior
> to figuring out what we actually want symbols in Kconfig.socs to
> actually at LPC or w/e. Palmer?
>
> > + bool
> > + select GPIOLIB
> > + select PINCTRL
> > + select SOC_BUS
> > +
> > +config SOC_RENESAS_RZFIVE
>
> I would like to see this added to the default defconfig so that
> it has dtbs_check coverage by default.
>
Agreed, I will include it in the next version.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-27 8:09 ` Lad, Prabhakar
@ 2022-07-27 8:21 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-27 8:21 UTC (permalink / raw)
To: prabhakar.csengg, Conor.Dooley
Cc: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, anup,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
biju.das.jz
On 27/07/2022 09:09, Lad, Prabhakar wrote:
> Hi Conor,
>
>>
>> Missing files? Where is your Makefile for this directory?
>> Or the board dts?
>>
> My plan was to get the initial minimal SoC DTSi and then later
> gradually add the board DTS, but it looks like I'll have to include it
> along with this series.
>
You could still add a minimal dts & add more things to it over time I
guess?
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-27 8:21 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-27 8:21 UTC (permalink / raw)
To: prabhakar.csengg, Conor.Dooley
Cc: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, anup,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
biju.das.jz
On 27/07/2022 09:09, Lad, Prabhakar wrote:
> Hi Conor,
>
>>
>> Missing files? Where is your Makefile for this directory?
>> Or the board dts?
>>
> My plan was to get the initial minimal SoC DTSi and then later
> gradually add the board DTS, but it looks like I'll have to include it
> along with this series.
>
You could still add a minimal dts & add more things to it over time I
guess?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-27 8:21 ` Conor.Dooley
@ 2022-07-27 8:30 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:30 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Wed, Jul 27, 2022 at 9:21 AM <Conor.Dooley@microchip.com> wrote:
>
>
> On 27/07/2022 09:09, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> >>
> >> Missing files? Where is your Makefile for this directory?
> >> Or the board dts?
> >>
> > My plan was to get the initial minimal SoC DTSi and then later
> > gradually add the board DTS, but it looks like I'll have to include it
> > along with this series.
> >
>
> You could still add a minimal dts & add more things to it over time I
> guess?
>
Agreed.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-27 8:30 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:30 UTC (permalink / raw)
To: Conor.Dooley
Cc: Lad, Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, aou, anup,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Conor,
On Wed, Jul 27, 2022 at 9:21 AM <Conor.Dooley@microchip.com> wrote:
>
>
> On 27/07/2022 09:09, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> >>
> >> Missing files? Where is your Makefile for this directory?
> >> Or the board dts?
> >>
> > My plan was to get the initial minimal SoC DTSi and then later
> > gradually add the board DTS, but it looks like I'll have to include it
> > along with this series.
> >
>
> You could still add a minimal dts & add more things to it over time I
> guess?
>
Agreed.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:50 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:50 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
Your commit msg says one, but patch ignores r9a07g043f01 which sounds
entirely different for non-Renesas people. Be a bit more clear.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
It is only one item, so I guess you wanted here enum.
Just like syscon is doing...
> + - const: renesas,r9a07g043f01
> +
> properties:
> $nodename:
> const: '/'
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 8:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:50 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
Your commit msg says one, but patch ignores r9a07g043f01 which sounds
entirely different for non-Renesas people. Be a bit more clear.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
It is only one item, so I guess you wanted here enum.
Just like syscon is doing...
> + - const: renesas,r9a07g043f01
> +
> properties:
> $nodename:
> const: '/'
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:51 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:51 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically
@ 2022-07-27 8:51 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:51 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:51 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:51 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
@ 2022-07-27 8:51 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:51 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:53 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01
Second issue - why not renesas,r9a07g043?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 8:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:53 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01
Second issue - why not renesas,r9a07g043?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:54 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:54 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> new file mode 100644
> index 000000000000..f72f8aea6a82
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/Five Platform Device Tree Bindings
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
I think you should rather ignore the RiscV SoCs, not specific board.
> + - const: renesas,smarc-evk
> + - enum:
> + - renesas,r9a07g043u11
> + - renesas,r9a07g043u12
> + - renesas,r9a07g044c1
> + - renesas,r9a07g044c2
> + - renesas,r9a07g044l1
> + - renesas,r9a07g044l2
> + - renesas,r9a07g054l1
> + - renesas,r9a07g054l2
> + - enum:
> + - renesas,r9a07g043
> + - renesas,r9a07g044
> + - renesas,r9a07g054
Did you actually test that it works and properly matches?
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: RZ/Five (R9A07G043)
> + items:
> + - enum:
> + - renesas,smarc-evk # SMARC EVK
> + - const: renesas,r9a07g043f01
> + - const: renesas,r9a07g043
> +
> +additionalProperties: true
> +
> +...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 8:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:54 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> new file mode 100644
> index 000000000000..f72f8aea6a82
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/Five Platform Device Tree Bindings
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
I think you should rather ignore the RiscV SoCs, not specific board.
> + - const: renesas,smarc-evk
> + - enum:
> + - renesas,r9a07g043u11
> + - renesas,r9a07g043u12
> + - renesas,r9a07g044c1
> + - renesas,r9a07g044c2
> + - renesas,r9a07g044l1
> + - renesas,r9a07g044l2
> + - renesas,r9a07g054l1
> + - renesas,r9a07g054l2
> + - enum:
> + - renesas,r9a07g043
> + - renesas,r9a07g044
> + - renesas,r9a07g054
Did you actually test that it works and properly matches?
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: RZ/Five (R9A07G043)
> + items:
> + - enum:
> + - renesas,smarc-evk # SMARC EVK
> + - const: renesas,r9a07g043f01
> + - const: renesas,r9a07g043
> +
> +additionalProperties: true
> +
> +...
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-27 8:50 ` Krzysztof Kozlowski
@ 2022-07-27 8:55 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
Thank you for the review.
On Wed, Jul 27, 2022 at 9:51 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
>
> Your commit msg says one, but patch ignores r9a07g043f01 which sounds
> entirely different for non-Renesas people. Be a bit more clear.
>
Sure will update the commit message.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
>
> It is only one item, so I guess you wanted here enum.
>
> Just like syscon is doing...
>
Ok I will switch to enum.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 8:55 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 8:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
Thank you for the review.
On Wed, Jul 27, 2022 at 9:51 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
>
> Your commit msg says one, but patch ignores r9a07g043f01 which sounds
> entirely different for non-Renesas people. Be a bit more clear.
>
Sure will update the commit message.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
>
> It is only one item, so I guess you wanted here enum.
>
> Just like syscon is doing...
>
Ok I will switch to enum.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 8:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:55 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
What are you building there? There is no DTS.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-27 8:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 8:55 UTC (permalink / raw)
To: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: Anup Patel, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, Prabhakar, Biju Das
On 26/07/2022 20:06, Lad Prabhakar wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
What are you building there? There is no DTS.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-27 8:53 ` Krzysztof Kozlowski
@ 2022-07-27 9:00 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:00 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
> > + - const: renesas,r9a07g043f01
>
> Second issue - why not renesas,r9a07g043?
>
We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
RZ/G2UL ARM64:
Type-1 Part Number: R9A07G043U11GBG#BC0
Type-2 Part Number: R9A07G043U12GBG#BC0
RZ/Five RISCV:
13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
So to differentiate in ARM schema I am using renesas,r9a07g043f01.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 9:00 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:00 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
> > + - const: renesas,r9a07g043f01
>
> Second issue - why not renesas,r9a07g043?
>
We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
RZ/G2UL ARM64:
Type-1 Part Number: R9A07G043U11GBG#BC0
Type-2 Part Number: R9A07G043U12GBG#BC0
RZ/Five RISCV:
13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
So to differentiate in ARM schema I am using renesas,r9a07g043f01.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 8:54 ` Krzysztof Kozlowski
@ 2022-07-27 9:05 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
Thank you for the review.
On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > new file mode 100644
> > index 000000000000..f72f8aea6a82
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > @@ -0,0 +1,49 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/Five Platform Device Tree Bindings
> > +
> > +maintainers:
> > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > +
> > +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
>
> I think you should rather ignore the RiscV SoCs, not specific board.
>
You mean to ignore ARM/64 SoCs?
Agreed just the below enum, should do the trick.
- enum:
- renesas,r9a07g043u11
- renesas,r9a07g043u12
- renesas,r9a07g044c1
- renesas,r9a07g044c2
- renesas,r9a07g044l1
- renesas,r9a07g044l2
- renesas,r9a07g054l1
- renesas,r9a07g054l2
> > + - const: renesas,smarc-evk
> > + - enum:
> > + - renesas,r9a07g043u11
> > + - renesas,r9a07g043u12
> > + - renesas,r9a07g044c1
> > + - renesas,r9a07g044c2
> > + - renesas,r9a07g044l1
> > + - renesas,r9a07g044l2
> > + - renesas,r9a07g054l1
> > + - renesas,r9a07g054l2
> > + - enum:
> > + - renesas,r9a07g043
> > + - renesas,r9a07g044
> > + - renesas,r9a07g054
>
> Did you actually test that it works and properly matches?
>
Yes I have run the dtbs_check and dt_binding _check for ARM64 and
RISC-V. Do you see any cases where it can fail?
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 9:05 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
Thank you for the review.
On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > new file mode 100644
> > index 000000000000..f72f8aea6a82
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > @@ -0,0 +1,49 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/Five Platform Device Tree Bindings
> > +
> > +maintainers:
> > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > +
> > +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
>
> I think you should rather ignore the RiscV SoCs, not specific board.
>
You mean to ignore ARM/64 SoCs?
Agreed just the below enum, should do the trick.
- enum:
- renesas,r9a07g043u11
- renesas,r9a07g043u12
- renesas,r9a07g044c1
- renesas,r9a07g044c2
- renesas,r9a07g044l1
- renesas,r9a07g044l2
- renesas,r9a07g054l1
- renesas,r9a07g054l2
> > + - const: renesas,smarc-evk
> > + - enum:
> > + - renesas,r9a07g043u11
> > + - renesas,r9a07g043u12
> > + - renesas,r9a07g044c1
> > + - renesas,r9a07g044c2
> > + - renesas,r9a07g044l1
> > + - renesas,r9a07g044l2
> > + - renesas,r9a07g054l1
> > + - renesas,r9a07g054l2
> > + - enum:
> > + - renesas,r9a07g043
> > + - renesas,r9a07g044
> > + - renesas,r9a07g054
>
> Did you actually test that it works and properly matches?
>
Yes I have run the dtbs_check and dt_binding _check for ARM64 and
RISC-V. Do you see any cases where it can fail?
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
2022-07-27 8:55 ` Krzysztof Kozlowski
@ 2022-07-27 9:08 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 9:55 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
>
> What are you building there? There is no DTS.
>
My plan was to get the initial minimal SoC DTSi and then gradually add
the board DTS, but it looks like I'll have to include it along with
this series.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
@ 2022-07-27 9:08 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 9:55 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
>
> What are you building there? There is no DTS.
>
My plan was to get the initial minimal SoC DTSi and then gradually add
the board DTS, but it looks like I'll have to include it along with
this series.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 9:05 ` Lad, Prabhakar
@ 2022-07-27 9:27 ` Biju Das
-1 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 9:27 UTC (permalink / raw)
To: Lad, Prabhakar, Krzysztof Kozlowski
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Lad, Prabhakar,
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> Hi Krzysztof,
>
> Thank you for the review.
>
> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this
> SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > .../devicetree/bindings/riscv/renesas.yaml | 49
> +++++++++++++++++++
> > > 1 file changed, 49 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/riscv/renesas.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > new file mode 100644
> > > index 000000000000..f72f8aea6a82
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > @@ -0,0 +1,49 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +
> > > +title: Renesas RZ/Five Platform Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > +
> > > +# We want to ignore this schema if the board is SMARC EVK based on
> > > +ARM64 arch
> > > +select:
> > > + not:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + items:
> >
> > I think you should rather ignore the RiscV SoCs, not specific board.
> >
> You mean to ignore ARM/64 SoCs?
>
> Agreed just the below enum, should do the trick.
>
> - enum:
> - renesas,r9a07g043u11
> - renesas,r9a07g043u12
> - renesas,r9a07g044c1
> - renesas,r9a07g044c2
> - renesas,r9a07g044l1
> - renesas,r9a07g044l2
> - renesas,r9a07g054l1
> - renesas,r9a07g054l2
Why do we need to add renesas,r9a07g044 and renesas,r9a07g054
in riscv file? These are arm64 only SoC's.
Cheers,
Biju
>
> > > + - const: renesas,smarc-evk
> > > + - enum:
> > > + - renesas,r9a07g043u11
> > > + - renesas,r9a07g043u12
> > > + - renesas,r9a07g044c1
> > > + - renesas,r9a07g044c2
> > > + - renesas,r9a07g044l1
> > > + - renesas,r9a07g044l2
> > > + - renesas,r9a07g054l1
> > > + - renesas,r9a07g054l2
> > > + - enum:
> > > + - renesas,r9a07g043
> > > + - renesas,r9a07g044
> > > + - renesas,r9a07g054
> >
> > Did you actually test that it works and properly matches?
> >
> Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC-
> V. Do you see any cases where it can fail?
>
> Cheers,
> Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 9:27 ` Biju Das
0 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 9:27 UTC (permalink / raw)
To: Lad, Prabhakar, Krzysztof Kozlowski
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Lad, Prabhakar,
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> Hi Krzysztof,
>
> Thank you for the review.
>
> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this
> SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > .../devicetree/bindings/riscv/renesas.yaml | 49
> +++++++++++++++++++
> > > 1 file changed, 49 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/riscv/renesas.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > new file mode 100644
> > > index 000000000000..f72f8aea6a82
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > @@ -0,0 +1,49 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +
> > > +title: Renesas RZ/Five Platform Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > +
> > > +# We want to ignore this schema if the board is SMARC EVK based on
> > > +ARM64 arch
> > > +select:
> > > + not:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + items:
> >
> > I think you should rather ignore the RiscV SoCs, not specific board.
> >
> You mean to ignore ARM/64 SoCs?
>
> Agreed just the below enum, should do the trick.
>
> - enum:
> - renesas,r9a07g043u11
> - renesas,r9a07g043u12
> - renesas,r9a07g044c1
> - renesas,r9a07g044c2
> - renesas,r9a07g044l1
> - renesas,r9a07g044l2
> - renesas,r9a07g054l1
> - renesas,r9a07g054l2
Why do we need to add renesas,r9a07g044 and renesas,r9a07g054
in riscv file? These are arm64 only SoC's.
Cheers,
Biju
>
> > > + - const: renesas,smarc-evk
> > > + - enum:
> > > + - renesas,r9a07g043u11
> > > + - renesas,r9a07g043u12
> > > + - renesas,r9a07g044c1
> > > + - renesas,r9a07g044c2
> > > + - renesas,r9a07g044l1
> > > + - renesas,r9a07g044l2
> > > + - renesas,r9a07g054l1
> > > + - renesas,r9a07g054l2
> > > + - enum:
> > > + - renesas,r9a07g043
> > > + - renesas,r9a07g044
> > > + - renesas,r9a07g054
> >
> > Did you actually test that it works and properly matches?
> >
> Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC-
> V. Do you see any cases where it can fail?
>
> Cheers,
> Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-27 9:00 ` Lad, Prabhakar
@ 2022-07-27 9:31 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 9:31 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 11:00, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
>>> (RISC-V arch).
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> index ff80152f092f..f646df1a23af 100644
>>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
>>> maintainers:
>>> - Geert Uytterhoeven <geert+renesas@glider.be>
>>>
>>> +# We want to ignore this schema if the board is of RISC-V arch
>>> +select:
>>> + not:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + items:
>>> + - const: renesas,r9a07g043f01
>>
>> Second issue - why not renesas,r9a07g043?
>>
> We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
>
> RZ/G2UL ARM64:
> Type-1 Part Number: R9A07G043U11GBG#BC0
> Type-2 Part Number: R9A07G043U12GBG#BC0
>
> RZ/Five RISCV:
> 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
>
> So to differentiate in ARM schema I am using renesas,r9a07g043f01.
What is the point to keep then r9a07g043 fallback? The two SoCs are not
compatible at all, so they must not use the same fallback.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 9:31 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 9:31 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 11:00, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
>>> (RISC-V arch).
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> index ff80152f092f..f646df1a23af 100644
>>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
>>> maintainers:
>>> - Geert Uytterhoeven <geert+renesas@glider.be>
>>>
>>> +# We want to ignore this schema if the board is of RISC-V arch
>>> +select:
>>> + not:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + items:
>>> + - const: renesas,r9a07g043f01
>>
>> Second issue - why not renesas,r9a07g043?
>>
> We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
>
> RZ/G2UL ARM64:
> Type-1 Part Number: R9A07G043U11GBG#BC0
> Type-2 Part Number: R9A07G043U12GBG#BC0
>
> RZ/Five RISCV:
> 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
>
> So to differentiate in ARM schema I am using renesas,r9a07g043f01.
What is the point to keep then r9a07g043 fallback? The two SoCs are not
compatible at all, so they must not use the same fallback.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 9:27 ` Biju Das
@ 2022-07-27 9:35 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:35 UTC (permalink / raw)
To: Biju Das
Cc: Krzysztof Kozlowski, Prabhakar Mahadev Lad, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Biju,
On Wed, Jul 27, 2022 at 10:27 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Lad, Prabhakar,
>
> > Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> > documentation for Renesas RZ/Five SoC and SMARC EVK
> >
> > Hi Krzysztof,
> >
> > Thank you for the review.
> >
> > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > >
> > > On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this
> > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > .../devicetree/bindings/riscv/renesas.yaml | 49
> > +++++++++++++++++++
> > > > 1 file changed, 49 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/riscv/renesas.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > new file mode 100644
> > > > index 000000000000..f72f8aea6a82
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > @@ -0,0 +1,49 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > > +---
> > > > +$id:
>
> > > > +
> > > > +title: Renesas RZ/Five Platform Device Tree Bindings
> > > > +
> > > > +maintainers:
> > > > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > +
> > > > +# We want to ignore this schema if the board is SMARC EVK based on
> > > > +ARM64 arch
> > > > +select:
> > > > + not:
> > > > + properties:
> > > > + compatible:
> > > > + contains:
> > > > + items:
> > >
> > > I think you should rather ignore the RiscV SoCs, not specific board.
> > >
> > You mean to ignore ARM/64 SoCs?
> >
> > Agreed just the below enum, should do the trick.
> >
> > - enum:
> > - renesas,r9a07g043u11
> > - renesas,r9a07g043u12
> > - renesas,r9a07g044c1
> > - renesas,r9a07g044c2
> > - renesas,r9a07g044l1
> > - renesas,r9a07g044l2
> > - renesas,r9a07g054l1
> > - renesas,r9a07g054l2
>
> Why do we need to add renesas,r9a07g044 and renesas,r9a07g054
> in riscv file? These are arm64 only SoC's.
>
The above needs to be added to avoid dtbs_check/dt_binding_check
errors. The above hunk ignores the RISC-V schema if it's an ARM64 SoC.
Cheers,
Prabhakar
> Cheers,
> Biju
>
>
>
> >
> > > > + - const: renesas,smarc-evk
> > > > + - enum:
> > > > + - renesas,r9a07g043u11
> > > > + - renesas,r9a07g043u12
> > > > + - renesas,r9a07g044c1
> > > > + - renesas,r9a07g044c2
> > > > + - renesas,r9a07g044l1
> > > > + - renesas,r9a07g044l2
> > > > + - renesas,r9a07g054l1
> > > > + - renesas,r9a07g054l2
> > > > + - enum:
> > > > + - renesas,r9a07g043
> > > > + - renesas,r9a07g044
> > > > + - renesas,r9a07g054
> > >
> > > Did you actually test that it works and properly matches?
> > >
> > Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC-
> > V. Do you see any cases where it can fail?
> >
> > Cheers,
> > Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 9:35 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:35 UTC (permalink / raw)
To: Biju Das
Cc: Krzysztof Kozlowski, Prabhakar Mahadev Lad, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Biju,
On Wed, Jul 27, 2022 at 10:27 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Lad, Prabhakar,
>
> > Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> > documentation for Renesas RZ/Five SoC and SMARC EVK
> >
> > Hi Krzysztof,
> >
> > Thank you for the review.
> >
> > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > >
> > > On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this
> > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > .../devicetree/bindings/riscv/renesas.yaml | 49
> > +++++++++++++++++++
> > > > 1 file changed, 49 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/riscv/renesas.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > new file mode 100644
> > > > index 000000000000..f72f8aea6a82
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > > @@ -0,0 +1,49 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > > +---
> > > > +$id:
>
> > > > +
> > > > +title: Renesas RZ/Five Platform Device Tree Bindings
> > > > +
> > > > +maintainers:
> > > > + - Geert Uytterhoeven <geert+renesas@glider.be>
> > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > +
> > > > +# We want to ignore this schema if the board is SMARC EVK based on
> > > > +ARM64 arch
> > > > +select:
> > > > + not:
> > > > + properties:
> > > > + compatible:
> > > > + contains:
> > > > + items:
> > >
> > > I think you should rather ignore the RiscV SoCs, not specific board.
> > >
> > You mean to ignore ARM/64 SoCs?
> >
> > Agreed just the below enum, should do the trick.
> >
> > - enum:
> > - renesas,r9a07g043u11
> > - renesas,r9a07g043u12
> > - renesas,r9a07g044c1
> > - renesas,r9a07g044c2
> > - renesas,r9a07g044l1
> > - renesas,r9a07g044l2
> > - renesas,r9a07g054l1
> > - renesas,r9a07g054l2
>
> Why do we need to add renesas,r9a07g044 and renesas,r9a07g054
> in riscv file? These are arm64 only SoC's.
>
The above needs to be added to avoid dtbs_check/dt_binding_check
errors. The above hunk ignores the RISC-V schema if it's an ARM64 SoC.
Cheers,
Prabhakar
> Cheers,
> Biju
>
>
>
> >
> > > > + - const: renesas,smarc-evk
> > > > + - enum:
> > > > + - renesas,r9a07g043u11
> > > > + - renesas,r9a07g043u12
> > > > + - renesas,r9a07g044c1
> > > > + - renesas,r9a07g044c2
> > > > + - renesas,r9a07g044l1
> > > > + - renesas,r9a07g044l2
> > > > + - renesas,r9a07g054l1
> > > > + - renesas,r9a07g054l2
> > > > + - enum:
> > > > + - renesas,r9a07g043
> > > > + - renesas,r9a07g044
> > > > + - renesas,r9a07g054
> > >
> > > Did you actually test that it works and properly matches?
> > >
> > Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC-
> > V. Do you see any cases where it can fail?
> >
> > Cheers,
> > Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-27 9:31 ` Krzysztof Kozlowski
@ 2022-07-27 9:48 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> >>> (RISC-V arch).
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> >>> 1 file changed, 9 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> index ff80152f092f..f646df1a23af 100644
> >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> >>> maintainers:
> >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> >>>
> >>> +# We want to ignore this schema if the board is of RISC-V arch
> >>> +select:
> >>> + not:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + items:
> >>> + - const: renesas,r9a07g043f01
> >>
> >> Second issue - why not renesas,r9a07g043?
> >>
> > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> >
> > RZ/G2UL ARM64:
> > Type-1 Part Number: R9A07G043U11GBG#BC0
> > Type-2 Part Number: R9A07G043U12GBG#BC0
> >
> > RZ/Five RISCV:
> > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> >
> > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
>
> What is the point to keep then r9a07g043 fallback? The two SoCs are not
> compatible at all, so they must not use the same fallback.
>
Agreed, I wanted to keep it consistent with what was done with ARM64
(since both the SoCs shared R9A07G043 part number).
Geert - What are your thoughts on the above?
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 9:48 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 9:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: Lad Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> >>> (RISC-V arch).
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> >>> 1 file changed, 9 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> index ff80152f092f..f646df1a23af 100644
> >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> >>> maintainers:
> >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> >>>
> >>> +# We want to ignore this schema if the board is of RISC-V arch
> >>> +select:
> >>> + not:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + items:
> >>> + - const: renesas,r9a07g043f01
> >>
> >> Second issue - why not renesas,r9a07g043?
> >>
> > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> >
> > RZ/G2UL ARM64:
> > Type-1 Part Number: R9A07G043U11GBG#BC0
> > Type-2 Part Number: R9A07G043U12GBG#BC0
> >
> > RZ/Five RISCV:
> > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> >
> > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
>
> What is the point to keep then r9a07g043 fallback? The two SoCs are not
> compatible at all, so they must not use the same fallback.
>
Agreed, I wanted to keep it consistent with what was done with ARM64
(since both the SoCs shared R9A07G043 part number).
Geert - What are your thoughts on the above?
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 9:05 ` Lad, Prabhakar
@ 2022-07-27 9:54 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 9:54 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 11:05, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> Thank you for the review.
>
> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
>>> 1 file changed, 49 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>> new file mode 100644
>>> index 000000000000..f72f8aea6a82
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>> @@ -0,0 +1,49 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas RZ/Five Platform Device Tree Bindings
>>> +
>>> +maintainers:
>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> +
>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
>>> +select:
>>> + not:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + items:
>>
>> I think you should rather ignore the RiscV SoCs, not specific board.
>>
> You mean to ignore ARM/64 SoCs?
>
> Agreed just the below enum, should do the trick.
>
> - enum:
> - renesas,r9a07g043u11
> - renesas,r9a07g043u12
> - renesas,r9a07g044c1
> - renesas,r9a07g044c2
> - renesas,r9a07g044l1
> - renesas,r9a07g044l2
> - renesas,r9a07g054l1
> - renesas,r9a07g054l2
>
>
>>> + - const: renesas,smarc-evk
>>> + - enum:
>>> + - renesas,r9a07g043u11
>>> + - renesas,r9a07g043u12
>>> + - renesas,r9a07g044c1
>>> + - renesas,r9a07g044c2
>>> + - renesas,r9a07g044l1
>>> + - renesas,r9a07g044l2
>>> + - renesas,r9a07g054l1
>>> + - renesas,r9a07g054l2
>>> + - enum:
>>> + - renesas,r9a07g043
>>> + - renesas,r9a07g044
>>> + - renesas,r9a07g054
>>
>> Did you actually test that it works and properly matches?
>>
> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> RISC-V. Do you see any cases where it can fail?
Just remove the renesas,smarc-evk2 from
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
error? Not from this schema. The only error you will see is that no
matching schema was found.
I don't think you can use such selects...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 9:54 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 9:54 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 11:05, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> Thank you for the review.
>
> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
>>> 1 file changed, 49 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>> new file mode 100644
>>> index 000000000000..f72f8aea6a82
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>> @@ -0,0 +1,49 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas RZ/Five Platform Device Tree Bindings
>>> +
>>> +maintainers:
>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> +
>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
>>> +select:
>>> + not:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + items:
>>
>> I think you should rather ignore the RiscV SoCs, not specific board.
>>
> You mean to ignore ARM/64 SoCs?
>
> Agreed just the below enum, should do the trick.
>
> - enum:
> - renesas,r9a07g043u11
> - renesas,r9a07g043u12
> - renesas,r9a07g044c1
> - renesas,r9a07g044c2
> - renesas,r9a07g044l1
> - renesas,r9a07g044l2
> - renesas,r9a07g054l1
> - renesas,r9a07g054l2
>
>
>>> + - const: renesas,smarc-evk
>>> + - enum:
>>> + - renesas,r9a07g043u11
>>> + - renesas,r9a07g043u12
>>> + - renesas,r9a07g044c1
>>> + - renesas,r9a07g044c2
>>> + - renesas,r9a07g044l1
>>> + - renesas,r9a07g044l2
>>> + - renesas,r9a07g054l1
>>> + - renesas,r9a07g054l2
>>> + - enum:
>>> + - renesas,r9a07g043
>>> + - renesas,r9a07g044
>>> + - renesas,r9a07g054
>>
>> Did you actually test that it works and properly matches?
>>
> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> RISC-V. Do you see any cases where it can fail?
Just remove the renesas,smarc-evk2 from
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
error? Not from this schema. The only error you will see is that no
matching schema was found.
I don't think you can use such selects...
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 9:54 ` Krzysztof Kozlowski
@ 2022-07-27 10:06 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 10:06 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 11:05, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > Thank you for the review.
> >
> > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> ---
> >>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> >>> 1 file changed, 49 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>> new file mode 100644
> >>> index 000000000000..f72f8aea6a82
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>> @@ -0,0 +1,49 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas RZ/Five Platform Device Tree Bindings
> >>> +
> >>> +maintainers:
> >>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> >>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> +
> >>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> >>> +select:
> >>> + not:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + items:
> >>
> >> I think you should rather ignore the RiscV SoCs, not specific board.
> >>
> > You mean to ignore ARM/64 SoCs?
> >
> > Agreed just the below enum, should do the trick.
> >
> > - enum:
> > - renesas,r9a07g043u11
> > - renesas,r9a07g043u12
> > - renesas,r9a07g044c1
> > - renesas,r9a07g044c2
> > - renesas,r9a07g044l1
> > - renesas,r9a07g044l2
> > - renesas,r9a07g054l1
> > - renesas,r9a07g054l2
> >
> >
> >>> + - const: renesas,smarc-evk
> >>> + - enum:
> >>> + - renesas,r9a07g043u11
> >>> + - renesas,r9a07g043u12
> >>> + - renesas,r9a07g044c1
> >>> + - renesas,r9a07g044c2
> >>> + - renesas,r9a07g044l1
> >>> + - renesas,r9a07g044l2
> >>> + - renesas,r9a07g054l1
> >>> + - renesas,r9a07g054l2
> >>> + - enum:
> >>> + - renesas,r9a07g043
> >>> + - renesas,r9a07g044
> >>> + - renesas,r9a07g054
> >>
> >> Did you actually test that it works and properly matches?
> >>
> > Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> > RISC-V. Do you see any cases where it can fail?
>
>
> Just remove the renesas,smarc-evk2 from
> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
> error? Not from this schema. The only error you will see is that no
> matching schema was found.
>
I did run the dtbs_check test as per your suggestion (below is the
log) and didn't see "no matching schema error"
prasmi@prasmi:~/work/linux$ git diff
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 121e55282d18..b8129d85515f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -11,5 +11,5 @@
/ {
model = "Renesas SMARC EVK based on r9a07g043u11";
- compatible = "renesas,smarc-evk", "renesas,r9a07g043u11",
"renesas,r9a07g043";
+ compatible = "renesas,r9a07g043u11", "renesas,r9a07g043";
};
prasmi@prasmi:~/work/linux$ rm
Documentation/devicetree/bindings/processed-schema.json
arch/arm64/boot/dts/renesas/*.dtb
prasmi@prasmi:~/work/linux$ make ARCH=arm64
CROSS_COMPILE=aarch64-linux-gnu- dtbs_check -j6
LINT Documentation/devicetree/bindings
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
pinctrl@11030000: 'interrupt-controller' is a required property
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
pinctrl@11030000: '#interrupt-cells' is a required property
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
usbphy-ctrl@11c40000: compatible:0: 'renesas,r9a07g043-usbphy-ctrl' is
not one of ['renesas,r9a07g044-usbphy-ctrl',
'renesas,r9a07g054-usbphy-ctrl']
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:0:0:
/soc/usbphy-ctrl@11c40000: failed to match any schema with compatible:
['renesas,r9a07g043-usbphy-ctrl', 'renesas,rzg2l-usbphy-ctrl']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
prasmi@prasmi:~/work/linux$
prasmi@prasmi:~/work/linux$
Note: I am using dtschema version 2022.7.
> I don't think you can use such selects...
>
> Best regards,
> Krzysztof
Cheers,
Prabhakar
^ permalink raw reply related [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 10:06 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 10:06 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 11:05, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > Thank you for the review.
> >
> > On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >>>
> >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> ---
> >>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> >>> 1 file changed, 49 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>> new file mode 100644
> >>> index 000000000000..f72f8aea6a82
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>> @@ -0,0 +1,49 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas RZ/Five Platform Device Tree Bindings
> >>> +
> >>> +maintainers:
> >>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> >>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>> +
> >>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> >>> +select:
> >>> + not:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + items:
> >>
> >> I think you should rather ignore the RiscV SoCs, not specific board.
> >>
> > You mean to ignore ARM/64 SoCs?
> >
> > Agreed just the below enum, should do the trick.
> >
> > - enum:
> > - renesas,r9a07g043u11
> > - renesas,r9a07g043u12
> > - renesas,r9a07g044c1
> > - renesas,r9a07g044c2
> > - renesas,r9a07g044l1
> > - renesas,r9a07g044l2
> > - renesas,r9a07g054l1
> > - renesas,r9a07g054l2
> >
> >
> >>> + - const: renesas,smarc-evk
> >>> + - enum:
> >>> + - renesas,r9a07g043u11
> >>> + - renesas,r9a07g043u12
> >>> + - renesas,r9a07g044c1
> >>> + - renesas,r9a07g044c2
> >>> + - renesas,r9a07g044l1
> >>> + - renesas,r9a07g044l2
> >>> + - renesas,r9a07g054l1
> >>> + - renesas,r9a07g054l2
> >>> + - enum:
> >>> + - renesas,r9a07g043
> >>> + - renesas,r9a07g044
> >>> + - renesas,r9a07g054
> >>
> >> Did you actually test that it works and properly matches?
> >>
> > Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> > RISC-V. Do you see any cases where it can fail?
>
>
> Just remove the renesas,smarc-evk2 from
> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
> error? Not from this schema. The only error you will see is that no
> matching schema was found.
>
I did run the dtbs_check test as per your suggestion (below is the
log) and didn't see "no matching schema error"
prasmi@prasmi:~/work/linux$ git diff
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 121e55282d18..b8129d85515f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -11,5 +11,5 @@
/ {
model = "Renesas SMARC EVK based on r9a07g043u11";
- compatible = "renesas,smarc-evk", "renesas,r9a07g043u11",
"renesas,r9a07g043";
+ compatible = "renesas,r9a07g043u11", "renesas,r9a07g043";
};
prasmi@prasmi:~/work/linux$ rm
Documentation/devicetree/bindings/processed-schema.json
arch/arm64/boot/dts/renesas/*.dtb
prasmi@prasmi:~/work/linux$ make ARCH=arm64
CROSS_COMPILE=aarch64-linux-gnu- dtbs_check -j6
LINT Documentation/devicetree/bindings
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb
DTC arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb
CHECK arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
pinctrl@11030000: 'interrupt-controller' is a required property
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
pinctrl@11030000: '#interrupt-cells' is a required property
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:
flash@0: compatible: 'oneOf' conditional failed, one must be fixed:
['micron,mt25qu512a', 'jedec,spi-nor'] is too long
'micron,mt25qu512a' does not match
'^((((micron|spansion|st),)?(m25p(40|80|16|32|64|128)|n25q(32b|064|128a11|128a13|256a|512a|164k)))|atmel,at25df(321a|641|081a)|everspin,mr25h(10|40|128|256)|(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|(mxicy|macronix),mx25u(4033|4035)|(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|(sst|microchip),sst25vf(016b|032b|040b)|(sst,)?sst26wf016b|(sst,)?sst25wf(040b|080)|winbond,w25x(80|32)|(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$'
'micron,mt25qu512a' is not one of ['issi,is25lp016d',
'micron,mt25qu02g', 'mxicy,mx25r1635f', 'mxicy,mx25u6435f',
'mxicy,mx25v8035f', 'spansion,s25sl12801', 'spansion,s25fs512s']
'jedec,spi-nor' was expected
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:0:0:
/soc/spi@10060000/flash@0: failed to match any schema with compatible:
['micron,mt25qu512a', 'jedec,spi-nor']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:
usbphy-ctrl@11c40000: compatible:0: 'renesas,r9a07g043-usbphy-ctrl' is
not one of ['renesas,r9a07g044-usbphy-ctrl',
'renesas,r9a07g054-usbphy-ctrl']
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dtb:0:0:
/soc/usbphy-ctrl@11c40000: failed to match any schema with compatible:
['renesas,r9a07g043-usbphy-ctrl', 'renesas,rzg2l-usbphy-ctrl']
/home/prasmi/work/linux/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb:
pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must
be fixed:
[[2]] is not of type 'object'
From schema:
/home/prasmi/work/linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
prasmi@prasmi:~/work/linux$
prasmi@prasmi:~/work/linux$
Note: I am using dtschema version 2022.7.
> I don't think you can use such selects...
>
> Best regards,
> Krzysztof
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 10:06 ` Lad, Prabhakar
@ 2022-07-27 10:09 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 10:09 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 12:06, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 11:05, Lad, Prabhakar wrote:
>>> Hi Krzysztof,
>>>
>>> Thank you for the review.
>>>
>>> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> ---
>>>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
>>>>> 1 file changed, 49 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..f72f8aea6a82
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> @@ -0,0 +1,49 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas RZ/Five Platform Device Tree Bindings
>>>>> +
>>>>> +maintainers:
>>>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> +
>>>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
>>>>> +select:
>>>>> + not:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + items:
>>>>
>>>> I think you should rather ignore the RiscV SoCs, not specific board.
>>>>
>>> You mean to ignore ARM/64 SoCs?
>>>
>>> Agreed just the below enum, should do the trick.
>>>
>>> - enum:
>>> - renesas,r9a07g043u11
>>> - renesas,r9a07g043u12
>>> - renesas,r9a07g044c1
>>> - renesas,r9a07g044c2
>>> - renesas,r9a07g044l1
>>> - renesas,r9a07g044l2
>>> - renesas,r9a07g054l1
>>> - renesas,r9a07g054l2
>>>
>>>
>>>>> + - const: renesas,smarc-evk
>>>>> + - enum:
>>>>> + - renesas,r9a07g043u11
>>>>> + - renesas,r9a07g043u12
>>>>> + - renesas,r9a07g044c1
>>>>> + - renesas,r9a07g044c2
>>>>> + - renesas,r9a07g044l1
>>>>> + - renesas,r9a07g044l2
>>>>> + - renesas,r9a07g054l1
>>>>> + - renesas,r9a07g054l2
>>>>> + - enum:
>>>>> + - renesas,r9a07g043
>>>>> + - renesas,r9a07g044
>>>>> + - renesas,r9a07g054
>>>>
>>>> Did you actually test that it works and properly matches?
>>>>
>>> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
>>> RISC-V. Do you see any cases where it can fail?
>>
>>
>> Just remove the renesas,smarc-evk2 from
>> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
>> error? Not from this schema. The only error you will see is that no
>> matching schema was found.
>>
> I did run the dtbs_check test as per your suggestion (below is the
> log) and didn't see "no matching schema error"
>
So you do not see any errors at all. Then it does not work, does it?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 10:09 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 10:09 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 12:06, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 11:05, Lad, Prabhakar wrote:
>>> Hi Krzysztof,
>>>
>>> Thank you for the review.
>>>
>>> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> ---
>>>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
>>>>> 1 file changed, 49 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..f72f8aea6a82
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> @@ -0,0 +1,49 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas RZ/Five Platform Device Tree Bindings
>>>>> +
>>>>> +maintainers:
>>>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> +
>>>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
>>>>> +select:
>>>>> + not:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + items:
>>>>
>>>> I think you should rather ignore the RiscV SoCs, not specific board.
>>>>
>>> You mean to ignore ARM/64 SoCs?
>>>
>>> Agreed just the below enum, should do the trick.
>>>
>>> - enum:
>>> - renesas,r9a07g043u11
>>> - renesas,r9a07g043u12
>>> - renesas,r9a07g044c1
>>> - renesas,r9a07g044c2
>>> - renesas,r9a07g044l1
>>> - renesas,r9a07g044l2
>>> - renesas,r9a07g054l1
>>> - renesas,r9a07g054l2
>>>
>>>
>>>>> + - const: renesas,smarc-evk
>>>>> + - enum:
>>>>> + - renesas,r9a07g043u11
>>>>> + - renesas,r9a07g043u12
>>>>> + - renesas,r9a07g044c1
>>>>> + - renesas,r9a07g044c2
>>>>> + - renesas,r9a07g044l1
>>>>> + - renesas,r9a07g044l2
>>>>> + - renesas,r9a07g054l1
>>>>> + - renesas,r9a07g054l2
>>>>> + - enum:
>>>>> + - renesas,r9a07g043
>>>>> + - renesas,r9a07g044
>>>>> + - renesas,r9a07g054
>>>>
>>>> Did you actually test that it works and properly matches?
>>>>
>>> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
>>> RISC-V. Do you see any cases where it can fail?
>>
>>
>> Just remove the renesas,smarc-evk2 from
>> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
>> error? Not from this schema. The only error you will see is that no
>> matching schema was found.
>>
> I did run the dtbs_check test as per your suggestion (below is the
> log) and didn't see "no matching schema error"
>
So you do not see any errors at all. Then it does not work, does it?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 10:09 ` Krzysztof Kozlowski
@ 2022-07-27 11:37 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 11:09 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 12:06, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 27/07/2022 11:05, Lad, Prabhakar wrote:
> >>> Hi Krzysztof,
> >>>
> >>> Thank you for the review.
> >>>
> >>> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >>>>>
> >>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>>> ---
> >>>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> >>>>> 1 file changed, 49 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..f72f8aea6a82
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>> @@ -0,0 +1,49 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: Renesas RZ/Five Platform Device Tree Bindings
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> >>>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>>> +
> >>>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> >>>>> +select:
> >>>>> + not:
> >>>>> + properties:
> >>>>> + compatible:
> >>>>> + contains:
> >>>>> + items:
> >>>>
> >>>> I think you should rather ignore the RiscV SoCs, not specific board.
> >>>>
> >>> You mean to ignore ARM/64 SoCs?
> >>>
> >>> Agreed just the below enum, should do the trick.
> >>>
> >>> - enum:
> >>> - renesas,r9a07g043u11
> >>> - renesas,r9a07g043u12
> >>> - renesas,r9a07g044c1
> >>> - renesas,r9a07g044c2
> >>> - renesas,r9a07g044l1
> >>> - renesas,r9a07g044l2
> >>> - renesas,r9a07g054l1
> >>> - renesas,r9a07g054l2
> >>>
> >>>
> >>>>> + - const: renesas,smarc-evk
> >>>>> + - enum:
> >>>>> + - renesas,r9a07g043u11
> >>>>> + - renesas,r9a07g043u12
> >>>>> + - renesas,r9a07g044c1
> >>>>> + - renesas,r9a07g044c2
> >>>>> + - renesas,r9a07g044l1
> >>>>> + - renesas,r9a07g044l2
> >>>>> + - renesas,r9a07g054l1
> >>>>> + - renesas,r9a07g054l2
> >>>>> + - enum:
> >>>>> + - renesas,r9a07g043
> >>>>> + - renesas,r9a07g044
> >>>>> + - renesas,r9a07g054
> >>>>
> >>>> Did you actually test that it works and properly matches?
> >>>>
> >>> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> >>> RISC-V. Do you see any cases where it can fail?
> >>
> >>
> >> Just remove the renesas,smarc-evk2 from
> >> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
> >> error? Not from this schema. The only error you will see is that no
> >> matching schema was found.
> >>
> > I did run the dtbs_check test as per your suggestion (below is the
> > log) and didn't see "no matching schema error"
> >
>
> So you do not see any errors at all. Then it does not work, does it?
>
Right I reverted my changes I can see it complaining, dtb_check seems
to have returned false positive in my case.
What approach would you suggest to ignore the schema here?
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 11:37 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Krzysztof,
On Wed, Jul 27, 2022 at 11:09 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 12:06, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 27/07/2022 11:05, Lad, Prabhakar wrote:
> >>> Hi Krzysztof,
> >>>
> >>> Thank you for the review.
> >>>
> >>> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
> >>>>>
> >>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>>> ---
> >>>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
> >>>>> 1 file changed, 49 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>> new file mode 100644
> >>>>> index 000000000000..f72f8aea6a82
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> >>>>> @@ -0,0 +1,49 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>>> +%YAML 1.2
> >>>>> +---
> >>>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
> >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>>>> +
> >>>>> +title: Renesas RZ/Five Platform Device Tree Bindings
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
> >>>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>>> +
> >>>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
> >>>>> +select:
> >>>>> + not:
> >>>>> + properties:
> >>>>> + compatible:
> >>>>> + contains:
> >>>>> + items:
> >>>>
> >>>> I think you should rather ignore the RiscV SoCs, not specific board.
> >>>>
> >>> You mean to ignore ARM/64 SoCs?
> >>>
> >>> Agreed just the below enum, should do the trick.
> >>>
> >>> - enum:
> >>> - renesas,r9a07g043u11
> >>> - renesas,r9a07g043u12
> >>> - renesas,r9a07g044c1
> >>> - renesas,r9a07g044c2
> >>> - renesas,r9a07g044l1
> >>> - renesas,r9a07g044l2
> >>> - renesas,r9a07g054l1
> >>> - renesas,r9a07g054l2
> >>>
> >>>
> >>>>> + - const: renesas,smarc-evk
> >>>>> + - enum:
> >>>>> + - renesas,r9a07g043u11
> >>>>> + - renesas,r9a07g043u12
> >>>>> + - renesas,r9a07g044c1
> >>>>> + - renesas,r9a07g044c2
> >>>>> + - renesas,r9a07g044l1
> >>>>> + - renesas,r9a07g044l2
> >>>>> + - renesas,r9a07g054l1
> >>>>> + - renesas,r9a07g054l2
> >>>>> + - enum:
> >>>>> + - renesas,r9a07g043
> >>>>> + - renesas,r9a07g044
> >>>>> + - renesas,r9a07g054
> >>>>
> >>>> Did you actually test that it works and properly matches?
> >>>>
> >>> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
> >>> RISC-V. Do you see any cases where it can fail?
> >>
> >>
> >> Just remove the renesas,smarc-evk2 from
> >> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
> >> error? Not from this schema. The only error you will see is that no
> >> matching schema was found.
> >>
> > I did run the dtbs_check test as per your suggestion (below is the
> > log) and didn't see "no matching schema error"
> >
>
> So you do not see any errors at all. Then it does not work, does it?
>
Right I reverted my changes I can see it complaining, dtb_check seems
to have returned false positive in my case.
What approach would you suggest to ignore the schema here?
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 11:37 ` Lad, Prabhakar
@ 2022-07-27 11:44 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 11:44 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 13:37, Lad, Prabhakar wrote:
>>>>
>>> I did run the dtbs_check test as per your suggestion (below is the
>>> log) and didn't see "no matching schema error"
>>>
>>
>> So you do not see any errors at all. Then it does not work, does it?
>>
> Right I reverted my changes I can see it complaining, dtb_check seems
> to have returned false positive in my case.
>
> What approach would you suggest to ignore the schema here?
I don't think currently it would work with your approach. Instead, you
should select here all SoCs which the schema should match.
This leads to my previous concern - you use the same SoC compatible for
two different architectures and different SoCs: ARMv8 and RISC-V.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 11:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 11:44 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
On 27/07/2022 13:37, Lad, Prabhakar wrote:
>>>>
>>> I did run the dtbs_check test as per your suggestion (below is the
>>> log) and didn't see "no matching schema error"
>>>
>>
>> So you do not see any errors at all. Then it does not work, does it?
>>
> Right I reverted my changes I can see it complaining, dtb_check seems
> to have returned false positive in my case.
>
> What approach would you suggest to ignore the schema here?
I don't think currently it would work with your approach. Instead, you
should select here all SoCs which the schema should match.
This leads to my previous concern - you use the same SoC compatible for
two different architectures and different SoCs: ARMv8 and RISC-V.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 11:44 ` Krzysztof Kozlowski
@ 2022-07-27 12:21 ` Biju Das
-1 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 12:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi,
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>
> >>> I did run the dtbs_check test as per your suggestion (below is the
> >>> log) and didn't see "no matching schema error"
> >>>
> >>
> >> So you do not see any errors at all. Then it does not work, does it?
> >>
> > Right I reverted my changes I can see it complaining, dtb_check seems
> > to have returned false positive in my case.
> >
> > What approach would you suggest to ignore the schema here?
>
> I don't think currently it would work with your approach. Instead, you
> should select here all SoCs which the schema should match.
>
> This leads to my previous concern - you use the same SoC compatible for
> two different architectures and different SoCs: ARMv8 and RISC-V.
Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
Using same SoM and Carrier board?
Cheers,
Biju
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 12:21 ` Biju Das
0 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 12:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi,
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>
> >>> I did run the dtbs_check test as per your suggestion (below is the
> >>> log) and didn't see "no matching schema error"
> >>>
> >>
> >> So you do not see any errors at all. Then it does not work, does it?
> >>
> > Right I reverted my changes I can see it complaining, dtb_check seems
> > to have returned false positive in my case.
> >
> > What approach would you suggest to ignore the schema here?
>
> I don't think currently it would work with your approach. Instead, you
> should select here all SoCs which the schema should match.
>
> This leads to my previous concern - you use the same SoC compatible for
> two different architectures and different SoCs: ARMv8 and RISC-V.
Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
Using same SoM and Carrier board?
Cheers,
Biju
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 12:21 ` Biju Das
@ 2022-07-27 12:36 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 12:36 UTC (permalink / raw)
To: Biju Das, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 27/07/2022 14:21, Biju Das wrote:
> Hi,
>
>> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
>> documentation for Renesas RZ/Five SoC and SMARC EVK
>>
>> On 27/07/2022 13:37, Lad, Prabhakar wrote:
>>>>>>
>>>>> I did run the dtbs_check test as per your suggestion (below is the
>>>>> log) and didn't see "no matching schema error"
>>>>>
>>>>
>>>> So you do not see any errors at all. Then it does not work, does it?
>>>>
>>> Right I reverted my changes I can see it complaining, dtb_check seems
>>> to have returned false positive in my case.
>>>
>>> What approach would you suggest to ignore the schema here?
>>
>> I don't think currently it would work with your approach. Instead, you
>> should select here all SoCs which the schema should match.
>>
>> This leads to my previous concern - you use the same SoC compatible for
>> two different architectures and different SoCs: ARMv8 and RISC-V.
>
> Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
Then it is not the same SoC! Same means same, identical. CPU
architecture is one of the major differences, which means it is not the
same.
> Using same SoM and Carrier board?
It's like saying PC with x86 and ARMv8 board are the same because they
both use same "PC chassis".
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 12:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 12:36 UTC (permalink / raw)
To: Biju Das, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 27/07/2022 14:21, Biju Das wrote:
> Hi,
>
>> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
>> documentation for Renesas RZ/Five SoC and SMARC EVK
>>
>> On 27/07/2022 13:37, Lad, Prabhakar wrote:
>>>>>>
>>>>> I did run the dtbs_check test as per your suggestion (below is the
>>>>> log) and didn't see "no matching schema error"
>>>>>
>>>>
>>>> So you do not see any errors at all. Then it does not work, does it?
>>>>
>>> Right I reverted my changes I can see it complaining, dtb_check seems
>>> to have returned false positive in my case.
>>>
>>> What approach would you suggest to ignore the schema here?
>>
>> I don't think currently it would work with your approach. Instead, you
>> should select here all SoCs which the schema should match.
>>
>> This leads to my previous concern - you use the same SoC compatible for
>> two different architectures and different SoCs: ARMv8 and RISC-V.
>
> Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
Then it is not the same SoC! Same means same, identical. CPU
architecture is one of the major differences, which means it is not the
same.
> Using same SoM and Carrier board?
It's like saying PC with x86 and ARMv8 board are the same because they
both use same "PC chassis".
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 12:36 ` Krzysztof Kozlowski
@ 2022-07-27 12:56 ` Biju Das
-1 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 27 July 2022 13:37
> To: Biju Das <biju.das.jz@bp.renesas.com>; Lad, Prabhakar
> <prabhakar.csengg@gmail.com>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Albert
> Ou <aou@eecs.berkeley.edu>; Anup Patel <anup@brainfault.org>; Linux-
> Renesas <linux-renesas-soc@vger.kernel.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-riscv
> <linux-riscv@lists.infradead.org>; LKML <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> On 27/07/2022 14:21, Biju Das wrote:
> > Hi,
> >
> >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> >> documentation for Renesas RZ/Five SoC and SMARC EVK
> >>
> >> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>>>
> >>>>> I did run the dtbs_check test as per your suggestion (below is the
> >>>>> log) and didn't see "no matching schema error"
> >>>>>
> >>>>
> >>>> So you do not see any errors at all. Then it does not work, does
> it?
> >>>>
> >>> Right I reverted my changes I can see it complaining, dtb_check
> >>> seems to have returned false positive in my case.
> >>>
> >>> What approach would you suggest to ignore the schema here?
> >>
> >> I don't think currently it would work with your approach. Instead,
> >> you should select here all SoCs which the schema should match.
> >>
> >> This leads to my previous concern - you use the same SoC compatible
> >> for two different architectures and different SoCs: ARMv8 and RISC-V.
> >
> > Or is it same SoC(R9A07G043) based on two different CPU architectures
> > (ARMv8 and RISC-V)
>
> Then it is not the same SoC! Same means same, identical. CPU
> architecture is one of the major differences, which means it is not the
> same.
Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
differences for SoC based on ARMV8 and RISC-V which has separate compatible like
r9a07g043u11 and r9a07g043f01?
>
> > Using same SoM and Carrier board?
>
> It's like saying PC with x86 and ARMv8 board are the same because they
> both use same "PC chassis".
What I meant is board based on Family SoC(R9A07G043) that is either based on ARMv8 or
RISC-V cpu architecture.
Cheers,
Biju
^ permalink raw reply [flat|nested] 96+ messages in thread
* RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 12:56 ` Biju Das
0 siblings, 0 replies; 96+ messages in thread
From: Biju Das @ 2022-07-27 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 27 July 2022 13:37
> To: Biju Das <biju.das.jz@bp.renesas.com>; Lad, Prabhakar
> <prabhakar.csengg@gmail.com>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Albert
> Ou <aou@eecs.berkeley.edu>; Anup Patel <anup@brainfault.org>; Linux-
> Renesas <linux-renesas-soc@vger.kernel.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-riscv
> <linux-riscv@lists.infradead.org>; LKML <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> On 27/07/2022 14:21, Biju Das wrote:
> > Hi,
> >
> >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> >> documentation for Renesas RZ/Five SoC and SMARC EVK
> >>
> >> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>>>
> >>>>> I did run the dtbs_check test as per your suggestion (below is the
> >>>>> log) and didn't see "no matching schema error"
> >>>>>
> >>>>
> >>>> So you do not see any errors at all. Then it does not work, does
> it?
> >>>>
> >>> Right I reverted my changes I can see it complaining, dtb_check
> >>> seems to have returned false positive in my case.
> >>>
> >>> What approach would you suggest to ignore the schema here?
> >>
> >> I don't think currently it would work with your approach. Instead,
> >> you should select here all SoCs which the schema should match.
> >>
> >> This leads to my previous concern - you use the same SoC compatible
> >> for two different architectures and different SoCs: ARMv8 and RISC-V.
> >
> > Or is it same SoC(R9A07G043) based on two different CPU architectures
> > (ARMv8 and RISC-V)
>
> Then it is not the same SoC! Same means same, identical. CPU
> architecture is one of the major differences, which means it is not the
> same.
Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
differences for SoC based on ARMV8 and RISC-V which has separate compatible like
r9a07g043u11 and r9a07g043f01?
>
> > Using same SoM and Carrier board?
>
> It's like saying PC with x86 and ARMv8 board are the same because they
> both use same "PC chassis".
What I meant is board based on Family SoC(R9A07G043) that is either based on ARMv8 or
RISC-V cpu architecture.
Cheers,
Biju
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 12:56 ` Biju Das
@ 2022-07-27 13:00 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 13:00 UTC (permalink / raw)
To: Biju Das, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 27/07/2022 14:56, Biju Das wrote:
>>
>> Then it is not the same SoC! Same means same, identical. CPU
>> architecture is one of the major differences, which means it is not the
>> same.
>
> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> r9a07g043u11 and r9a07g043f01?
This does not answer the concern - it's not the same SoC. The most
generic compatible denotes the most common part. I would argue that
instruction set and architecture are the most important differences.
None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
you went even more - you combined two architectures in the most generic
compatibles.
>
>>
>>> Using same SoM and Carrier board?
>>
>> It's like saying PC with x86 and ARMv8 board are the same because they
>> both use same "PC chassis".
>
> What I meant is board based on Family SoC(R9A07G043) that is either based on ARMv8 or
> RISC-V cpu architecture.
I don't see this related to the topic at all. What board do you use,
does not matter. The board does not change the fact these SoCs have
entirely different architecture - ARMv8 and RISC-V.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 13:00 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 13:00 UTC (permalink / raw)
To: Biju Das, Lad, Prabhakar
Cc: Prabhakar Mahadev Lad, Geert Uytterhoeven, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 27/07/2022 14:56, Biju Das wrote:
>>
>> Then it is not the same SoC! Same means same, identical. CPU
>> architecture is one of the major differences, which means it is not the
>> same.
>
> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> r9a07g043u11 and r9a07g043f01?
This does not answer the concern - it's not the same SoC. The most
generic compatible denotes the most common part. I would argue that
instruction set and architecture are the most important differences.
None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
you went even more - you combined two architectures in the most generic
compatibles.
>
>>
>>> Using same SoM and Carrier board?
>>
>> It's like saying PC with x86 and ARMv8 board are the same because they
>> both use same "PC chassis".
>
> What I meant is board based on Family SoC(R9A07G043) that is either based on ARMv8 or
> RISC-V cpu architecture.
I don't see this related to the topic at all. What board do you use,
does not matter. The board does not change the fact these SoCs have
entirely different architecture - ARMv8 and RISC-V.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 13:00 ` Krzysztof Kozlowski
@ 2022-07-27 13:29 ` Conor.Dooley
-1 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-27 13:29 UTC (permalink / raw)
To: krzysztof.kozlowski, biju.das.jz, prabhakar.csengg
Cc: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, anup,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel
On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 27/07/2022 14:56, Biju Das wrote:
>>>
>>> Then it is not the same SoC! Same means same, identical. CPU
>>> architecture is one of the major differences, which means it is not the
>>> same.
>>
>> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
>> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
>> r9a07g043u11 and r9a07g043f01?
>
> This does not answer the concern - it's not the same SoC. The most
> generic compatible denotes the most common part. I would argue that
> instruction set and architecture are the most important differences.
> None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> you went even more - you combined two architectures in the most generic
> compatibles.
I would have to agree with this. The most "core" part of the SoC is
its architecture and while the peripheral IPs might be the same etc
& the Renesas marketing team might have put them in the same "family",
for the purposes of a device tree I don't see how having a common
fallback makes sense.
Conor.
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 13:29 ` Conor.Dooley
0 siblings, 0 replies; 96+ messages in thread
From: Conor.Dooley @ 2022-07-27 13:29 UTC (permalink / raw)
To: krzysztof.kozlowski, biju.das.jz, prabhakar.csengg
Cc: prabhakar.mahadev-lad.rj, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, anup,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel
On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 27/07/2022 14:56, Biju Das wrote:
>>>
>>> Then it is not the same SoC! Same means same, identical. CPU
>>> architecture is one of the major differences, which means it is not the
>>> same.
>>
>> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
>> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
>> r9a07g043u11 and r9a07g043f01?
>
> This does not answer the concern - it's not the same SoC. The most
> generic compatible denotes the most common part. I would argue that
> instruction set and architecture are the most important differences.
> None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> you went even more - you combined two architectures in the most generic
> compatibles.
I would have to agree with this. The most "core" part of the SoC is
its architecture and while the peripheral IPs might be the same etc
& the Renesas marketing team might have put them in the same "family",
for the purposes of a device tree I don't see how having a common
fallback makes sense.
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 13:29 ` Conor.Dooley
@ 2022-07-27 15:32 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 15:32 UTC (permalink / raw)
To: Conor.Dooley
Cc: Krzysztof Kozlowski, Biju Das, Lad, Prabhakar,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On Wed, Jul 27, 2022 at 2:29 PM <Conor.Dooley@microchip.com> wrote:
>
> On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 27/07/2022 14:56, Biju Das wrote:
> >>>
> >>> Then it is not the same SoC! Same means same, identical. CPU
> >>> architecture is one of the major differences, which means it is not the
> >>> same.
> >>
> >> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> >> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> >> r9a07g043u11 and r9a07g043f01?
> >
> > This does not answer the concern - it's not the same SoC. The most
> > generic compatible denotes the most common part. I would argue that
> > instruction set and architecture are the most important differences.
> > None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> > you went even more - you combined two architectures in the most generic
> > compatibles.
>
> I would have to agree with this. The most "core" part of the SoC is
> its architecture and while the peripheral IPs might be the same etc
> & the Renesas marketing team might have put them in the same "family",
> for the purposes of a device tree I don't see how having a common
> fallback makes sense.
>
Agreed, I was following the same which we have done on the ARM64 schema.
I am waiting on Geert's feedback on whether we should follow as
Krzysztof suggested ie to have
renesas,smarc-evk-r9a07g043f01 - for the board
renesas,9a07g043f01 - for the SoC
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-07-27 15:32 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-07-27 15:32 UTC (permalink / raw)
To: Conor.Dooley
Cc: Krzysztof Kozlowski, Biju Das, Lad, Prabhakar,
Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On Wed, Jul 27, 2022 at 2:29 PM <Conor.Dooley@microchip.com> wrote:
>
> On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 27/07/2022 14:56, Biju Das wrote:
> >>>
> >>> Then it is not the same SoC! Same means same, identical. CPU
> >>> architecture is one of the major differences, which means it is not the
> >>> same.
> >>
> >> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> >> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> >> r9a07g043u11 and r9a07g043f01?
> >
> > This does not answer the concern - it's not the same SoC. The most
> > generic compatible denotes the most common part. I would argue that
> > instruction set and architecture are the most important differences.
> > None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> > you went even more - you combined two architectures in the most generic
> > compatibles.
>
> I would have to agree with this. The most "core" part of the SoC is
> its architecture and while the peripheral IPs might be the same etc
> & the Renesas marketing team might have put them in the same "family",
> for the purposes of a device tree I don't see how having a common
> fallback makes sense.
>
Agreed, I was following the same which we have done on the ARM64 schema.
I am waiting on Geert's feedback on whether we should follow as
Krzysztof suggested ie to have
renesas,smarc-evk-r9a07g043f01 - for the board
renesas,9a07g043f01 - for the SoC
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-26 18:06 ` Lad Prabhakar
@ 2022-07-27 15:43 ` Rob Herring
-1 siblings, 0 replies; 96+ messages in thread
From: Rob Herring @ 2022-07-27 15:43 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Geert Uytterhoeven, Magnus Damm, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
Prabhakar, Biju Das
On Tue, Jul 26, 2022 at 07:06:18PM +0100, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01
As I've said, this doesn't work without tool changes I proposed.
Rob
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-07-27 15:43 ` Rob Herring
0 siblings, 0 replies; 96+ messages in thread
From: Rob Herring @ 2022-07-27 15:43 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Geert Uytterhoeven, Magnus Damm, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
Prabhakar, Biju Das
On Tue, Jul 26, 2022 at 07:06:18PM +0100, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01
As I've said, this doesn't work without tool changes I proposed.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-07-27 9:48 ` Lad, Prabhakar
@ 2022-08-11 15:26 ` Geert Uytterhoeven
-1 siblings, 0 replies; 96+ messages in thread
From: Geert Uytterhoeven @ 2022-08-11 15:26 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Krzysztof Kozlowski, Lad Prabhakar, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Prabhakar,
On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > <krzysztof.kozlowski@linaro.org> wrote:
> > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > >>> (RISC-V arch).
> > >>>
> > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >>> ---
> > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > >>> 1 file changed, 9 insertions(+)
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> index ff80152f092f..f646df1a23af 100644
> > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > >>> maintainers:
> > >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> > >>>
> > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > >>> +select:
> > >>> + not:
> > >>> + properties:
> > >>> + compatible:
> > >>> + contains:
> > >>> + items:
> > >>> + - const: renesas,r9a07g043f01
> > >>
> > >> Second issue - why not renesas,r9a07g043?
> > >>
> > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > >
> > > RZ/G2UL ARM64:
> > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > >
> > > RZ/Five RISCV:
> > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > >
> > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> >
> > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > compatible at all, so they must not use the same fallback.
> >
> Agreed, I wanted to keep it consistent with what was done with ARM64
> (since both the SoCs shared R9A07G043 part number).
>
> Geert - What are your thoughts on the above?
"renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
"renesas,r9a07g043f01", "renesas,r9a07g043u11", and
"renesas,r9a07g043u12" are SoCs built by integrating one or more
RV64 or ARM64 CPU cores and the related interrupt controllers with
the CPU-less SoC base.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-08-11 15:26 ` Geert Uytterhoeven
0 siblings, 0 replies; 96+ messages in thread
From: Geert Uytterhoeven @ 2022-08-11 15:26 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Krzysztof Kozlowski, Lad Prabhakar, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Prabhakar,
On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > <krzysztof.kozlowski@linaro.org> wrote:
> > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > >>> (RISC-V arch).
> > >>>
> > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >>> ---
> > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > >>> 1 file changed, 9 insertions(+)
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> index ff80152f092f..f646df1a23af 100644
> > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > >>> maintainers:
> > >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> > >>>
> > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > >>> +select:
> > >>> + not:
> > >>> + properties:
> > >>> + compatible:
> > >>> + contains:
> > >>> + items:
> > >>> + - const: renesas,r9a07g043f01
> > >>
> > >> Second issue - why not renesas,r9a07g043?
> > >>
> > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > >
> > > RZ/G2UL ARM64:
> > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > >
> > > RZ/Five RISCV:
> > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > >
> > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> >
> > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > compatible at all, so they must not use the same fallback.
> >
> Agreed, I wanted to keep it consistent with what was done with ARM64
> (since both the SoCs shared R9A07G043 part number).
>
> Geert - What are your thoughts on the above?
"renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
"renesas,r9a07g043f01", "renesas,r9a07g043u11", and
"renesas,r9a07g043u12" are SoCs built by integrating one or more
RV64 or ARM64 CPU cores and the related interrupt controllers with
the CPU-less SoC base.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-07-27 12:36 ` Krzysztof Kozlowski
@ 2022-08-11 15:42 ` Geert Uytterhoeven
-1 siblings, 0 replies; 96+ messages in thread
From: Geert Uytterhoeven @ 2022-08-11 15:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Biju Das, Lad, Prabhakar, Prabhakar Mahadev Lad, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Krzysztof,
On Wed, Jul 27, 2022 at 2:37 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 27/07/2022 14:21, Biju Das wrote:
> >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> >> documentation for Renesas RZ/Five SoC and SMARC EVK
> >> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>> I did run the dtbs_check test as per your suggestion (below is the
> >>>>> log) and didn't see "no matching schema error"
> >>>>>
> >>>>
> >>>> So you do not see any errors at all. Then it does not work, does it?
> >>>>
> >>> Right I reverted my changes I can see it complaining, dtb_check seems
> >>> to have returned false positive in my case.
> >>>
> >>> What approach would you suggest to ignore the schema here?
> >>
> >> I don't think currently it would work with your approach. Instead, you
> >> should select here all SoCs which the schema should match.
> >>
> >> This leads to my previous concern - you use the same SoC compatible for
> >> two different architectures and different SoCs: ARMv8 and RISC-V.
> >
> > Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
>
> Then it is not the same SoC! Same means same, identical. CPU
> architecture is one of the major differences, which means it is not the
> same.
>
> > Using same SoM and Carrier board?
>
> It's like saying PC with x86 and ARMv8 board are the same because they
> both use same "PC chassis".
That's not a fair comparison: the "PC chassis" is passive, while the
carrier board is an active PCB. So it is more akin to plugging
any Intel LGA 1151 processor into any motherboard with an LGA
1151 socket. Do we have compatible values for all such possible
combinations? ;-)
The classic compatible scheme of an ordered list from most-specific
to least-specific is not well-suited for this case of mere
aggregation. That's why we have been decoupling board and SoC
compatible values for a while, and identifying specific boards by a
combination of a board-specific and an SoC-specific compatible value.
New SoCs that are available with different core CPU families (and
that are pin-compatible) are just the next step in the evolution....
At the DT validation level, I think the proper solution is to
merge Documentation/devicetree/bindings/arm/renesas.yaml and
Documentation/devicetree/bindings/riscv/renesas.yaml into a single
file under Documentation/devicetree/bindings/soc/renesas/.
What do other people think?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-08-11 15:42 ` Geert Uytterhoeven
0 siblings, 0 replies; 96+ messages in thread
From: Geert Uytterhoeven @ 2022-08-11 15:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Biju Das, Lad, Prabhakar, Prabhakar Mahadev Lad, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Krzysztof,
On Wed, Jul 27, 2022 at 2:37 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 27/07/2022 14:21, Biju Das wrote:
> >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> >> documentation for Renesas RZ/Five SoC and SMARC EVK
> >> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>> I did run the dtbs_check test as per your suggestion (below is the
> >>>>> log) and didn't see "no matching schema error"
> >>>>>
> >>>>
> >>>> So you do not see any errors at all. Then it does not work, does it?
> >>>>
> >>> Right I reverted my changes I can see it complaining, dtb_check seems
> >>> to have returned false positive in my case.
> >>>
> >>> What approach would you suggest to ignore the schema here?
> >>
> >> I don't think currently it would work with your approach. Instead, you
> >> should select here all SoCs which the schema should match.
> >>
> >> This leads to my previous concern - you use the same SoC compatible for
> >> two different architectures and different SoCs: ARMv8 and RISC-V.
> >
> > Or is it same SoC(R9A07G043) based on two different CPU architectures (ARMv8 and RISC-V)
>
> Then it is not the same SoC! Same means same, identical. CPU
> architecture is one of the major differences, which means it is not the
> same.
>
> > Using same SoM and Carrier board?
>
> It's like saying PC with x86 and ARMv8 board are the same because they
> both use same "PC chassis".
That's not a fair comparison: the "PC chassis" is passive, while the
carrier board is an active PCB. So it is more akin to plugging
any Intel LGA 1151 processor into any motherboard with an LGA
1151 socket. Do we have compatible values for all such possible
combinations? ;-)
The classic compatible scheme of an ordered list from most-specific
to least-specific is not well-suited for this case of mere
aggregation. That's why we have been decoupling board and SoC
compatible values for a while, and identifying specific boards by a
combination of a board-specific and an SoC-specific compatible value.
New SoCs that are available with different core CPU families (and
that are pin-compatible) are just the next step in the evolution....
At the DT validation level, I think the proper solution is to
merge Documentation/devicetree/bindings/arm/renesas.yaml and
Documentation/devicetree/bindings/riscv/renesas.yaml into a single
file under Documentation/devicetree/bindings/soc/renesas/.
What do other people think?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
2022-08-11 15:26 ` Geert Uytterhoeven
@ 2022-08-11 23:37 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-08-11 23:37 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Krzysztof Kozlowski, Lad Prabhakar, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Geert,
On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > > <krzysztof.kozlowski@linaro.org> wrote:
> > > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > > >>> (RISC-V arch).
> > > >>>
> > > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >>> ---
> > > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > > >>> 1 file changed, 9 insertions(+)
> > > >>>
> > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> index ff80152f092f..f646df1a23af 100644
> > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > > >>> maintainers:
> > > >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> > > >>>
> > > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > > >>> +select:
> > > >>> + not:
> > > >>> + properties:
> > > >>> + compatible:
> > > >>> + contains:
> > > >>> + items:
> > > >>> + - const: renesas,r9a07g043f01
> > > >>
> > > >> Second issue - why not renesas,r9a07g043?
> > > >>
> > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > > >
> > > > RZ/G2UL ARM64:
> > > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > > >
> > > > RZ/Five RISCV:
> > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > > >
> > > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> > >
> > > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > > compatible at all, so they must not use the same fallback.
> > >
> > Agreed, I wanted to keep it consistent with what was done with ARM64
> > (since both the SoCs shared R9A07G043 part number).
> >
> > Geert - What are your thoughts on the above?
>
> "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
> "renesas,r9a07g043f01", "renesas,r9a07g043u11", and
> "renesas,r9a07g043u12" are SoCs built by integrating one or more
> RV64 or ARM64 CPU cores and the related interrupt controllers with
> the CPU-less SoC base.
>
That's bang on! which I missed to convenience the DT maintainers.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch
@ 2022-08-11 23:37 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-08-11 23:37 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Krzysztof Kozlowski, Lad Prabhakar, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML, Biju Das
Hi Geert,
On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > > <krzysztof.kozlowski@linaro.org> wrote:
> > > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > > >>> (RISC-V arch).
> > > >>>
> > > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >>> ---
> > > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > > >>> 1 file changed, 9 insertions(+)
> > > >>>
> > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> index ff80152f092f..f646df1a23af 100644
> > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > > >>> maintainers:
> > > >>> - Geert Uytterhoeven <geert+renesas@glider.be>
> > > >>>
> > > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > > >>> +select:
> > > >>> + not:
> > > >>> + properties:
> > > >>> + compatible:
> > > >>> + contains:
> > > >>> + items:
> > > >>> + - const: renesas,r9a07g043f01
> > > >>
> > > >> Second issue - why not renesas,r9a07g043?
> > > >>
> > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > > >
> > > > RZ/G2UL ARM64:
> > > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > > >
> > > > RZ/Five RISCV:
> > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > > >
> > > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> > >
> > > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > > compatible at all, so they must not use the same fallback.
> > >
> > Agreed, I wanted to keep it consistent with what was done with ARM64
> > (since both the SoCs shared R9A07G043 part number).
> >
> > Geert - What are your thoughts on the above?
>
> "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
> "renesas,r9a07g043f01", "renesas,r9a07g043u11", and
> "renesas,r9a07g043u12" are SoCs built by integrating one or more
> RV64 or ARM64 CPU cores and the related interrupt controllers with
> the CPU-less SoC base.
>
That's bang on! which I missed to convenience the DT maintainers.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-08-11 15:42 ` Geert Uytterhoeven
@ 2022-08-12 6:23 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-08-12 6:23 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Lad, Prabhakar, Prabhakar Mahadev Lad, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 11/08/2022 18:42, Geert Uytterhoeven wrote:
> At the DT validation level, I think the proper solution is to
> merge Documentation/devicetree/bindings/arm/renesas.yaml and
> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
> file under Documentation/devicetree/bindings/soc/renesas/.
>
> What do other people think?
I am ok with it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-08-12 6:23 ` Krzysztof Kozlowski
0 siblings, 0 replies; 96+ messages in thread
From: Krzysztof Kozlowski @ 2022-08-12 6:23 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Lad, Prabhakar, Prabhakar Mahadev Lad, Magnus Damm,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
On 11/08/2022 18:42, Geert Uytterhoeven wrote:
> At the DT validation level, I think the proper solution is to
> merge Documentation/devicetree/bindings/arm/renesas.yaml and
> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
> file under Documentation/devicetree/bindings/soc/renesas/.
>
> What do other people think?
I am ok with it.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-08-12 6:23 ` Krzysztof Kozlowski
@ 2022-08-12 9:49 ` Lad, Prabhakar
-1 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-08-12 9:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: Biju Das, Prabhakar Mahadev Lad, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Krzysztof and Geert,
On Fri, Aug 12, 2022 at 7:23 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
> > At the DT validation level, I think the proper solution is to
> > merge Documentation/devicetree/bindings/arm/renesas.yaml and
> > Documentation/devicetree/bindings/riscv/renesas.yaml into a single
> > file under Documentation/devicetree/bindings/soc/renesas/.
> >
> > What do other people think?
>
> I am ok with it.
>
Thanks, I'll move this to the soc folder in v2.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-08-12 9:49 ` Lad, Prabhakar
0 siblings, 0 replies; 96+ messages in thread
From: Lad, Prabhakar @ 2022-08-12 9:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Geert Uytterhoeven
Cc: Biju Das, Prabhakar Mahadev Lad, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Anup Patel, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv, LKML
Hi Krzysztof and Geert,
On Fri, Aug 12, 2022 at 7:23 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
> > At the DT validation level, I think the proper solution is to
> > merge Documentation/devicetree/bindings/arm/renesas.yaml and
> > Documentation/devicetree/bindings/riscv/renesas.yaml into a single
> > file under Documentation/devicetree/bindings/soc/renesas/.
> >
> > What do other people think?
>
> I am ok with it.
>
Thanks, I'll move this to the soc folder in v2.
Cheers,
Prabhakar
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
2022-08-12 6:23 ` Krzysztof Kozlowski
@ 2022-08-12 15:10 ` Palmer Dabbelt
-1 siblings, 0 replies; 96+ messages in thread
From: Palmer Dabbelt @ 2022-08-12 15:10 UTC (permalink / raw)
To: krzysztof.kozlowski
Cc: geert, biju.das.jz, prabhakar.csengg, prabhakar.mahadev-lad.rj,
magnus.damm, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley, aou,
anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel
On Thu, 11 Aug 2022 23:23:10 PDT (-0700), krzysztof.kozlowski@linaro.org wrote:
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
>> At the DT validation level, I think the proper solution is to
>> merge Documentation/devicetree/bindings/arm/renesas.yaml and
>> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
>> file under Documentation/devicetree/bindings/soc/renesas/.
>>
>> What do other people think?
>
> I am ok with it.
Seems reasonable to me too, but I pretty much always err on the side of
keeping SOC stuff split out from the RISC-V stuff. Just looking at
Documentation/devicetree/bindings/riscv/, it's pretty much all SOC stuff
-- should we just move everything but cpus.yaml over?
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
@ 2022-08-12 15:10 ` Palmer Dabbelt
0 siblings, 0 replies; 96+ messages in thread
From: Palmer Dabbelt @ 2022-08-12 15:10 UTC (permalink / raw)
To: krzysztof.kozlowski
Cc: geert, biju.das.jz, prabhakar.csengg, prabhakar.mahadev-lad.rj,
magnus.damm, robh+dt, krzysztof.kozlowski+dt, Paul Walmsley, aou,
anup, linux-renesas-soc, devicetree, linux-riscv, linux-kernel
On Thu, 11 Aug 2022 23:23:10 PDT (-0700), krzysztof.kozlowski@linaro.org wrote:
> On 11/08/2022 18:42, Geert Uytterhoeven wrote:
>> At the DT validation level, I think the proper solution is to
>> merge Documentation/devicetree/bindings/arm/renesas.yaml and
>> Documentation/devicetree/bindings/riscv/renesas.yaml into a single
>> file under Documentation/devicetree/bindings/soc/renesas/.
>>
>> What do other people think?
>
> I am ok with it.
Seems reasonable to me too, but I pretty much always err on the side of
keeping SOC stuff split out from the RISC-V stuff. Just looking at
Documentation/devicetree/bindings/riscv/, it's pretty much all SOC stuff
-- should we just move everything but cpus.yaml over?
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 96+ messages in thread
end of thread, other threads:[~2022-08-12 15:11 UTC | newest]
Thread overview: 96+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:48 ` Lad, Prabhakar
2022-07-27 9:48 ` Lad, Prabhakar
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 23:37 ` Lad, Prabhakar
2022-08-11 23:37 ` Lad, Prabhakar
2022-07-27 15:43 ` Rob Herring
2022-07-27 15:43 ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:27 ` Biju Das
2022-07-27 9:27 ` Biju Das
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:09 ` Krzysztof Kozlowski
2022-07-27 10:09 ` Krzysztof Kozlowski
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Biju Das
2022-07-27 12:21 ` Biju Das
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:56 ` Biju Das
2022-07-27 12:56 ` Biju Das
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 15:32 ` Lad, Prabhakar
2022-07-27 15:32 ` Lad, Prabhakar
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 15:10 ` Palmer Dabbelt
2022-08-12 15:10 ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-26 18:49 ` Conor.Dooley
2022-07-26 18:49 ` Conor.Dooley
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` Lad Prabhakar
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-26 18:51 ` Conor.Dooley
2022-07-27 8:00 ` Lad, Prabhakar
2022-07-27 8:00 ` Lad, Prabhakar
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