U-Boot mtest Failure (read/write)

From: Embedded Engineer <embed786@gmail.com>
To: u-boot@lists.denx.de
Subject: U-Boot mtest Failure (read/write)
Date: Tue, 20 Oct 2020 10:32:22 +0500	[thread overview]
Message-ID: <CA+_ZnZSXQeP1Y+eREHZFfTDGN=tgPd8UaJnQVa5A5ZRY741b2w@mail.gmail.com> (raw)

I am trying to run mtest in U-Boot to verify if my RAM (on-board DDR3
on PowerPC based boards) is working fine. However, mtest is giving
following errors when I run the test:

Hit any key to stop autoboot:  0
=> mtest 0x4 0x40000000 0xaabbccdd 0x1
Testing 00000004 ... 40000000:
Iteration:      1
FAILURE (read/write) @ 0x08d174f4: expected 0x02345d3d, actual 0x02365d3d)

FAILURE (read/write) @ 0x08d1f4ec: expected 0x02347d3b, actual 0x02357d3b)

FAILURE (read/write) @ 0x08d1f4f4: expected 0x02347d3d, actual 0x02367d3d)

FAILURE (read/write) @ 0x08d1f4fc: expected 0x02347d3f, actual 0x02367d3f)

FAILURE (read/write) @ 0x08d274ec: expected 0x02349d3b, actual 0x02359d3b)

FAILURE (read/write) @ 0x08d274fc: expected 0x02349d3f, actual 0x02369d3f)

FAILURE (read/write) @ 0x2ccb62d4: expected 0x0b32d8b5, actual 0x0bb2d8b5)

FAILURE (read/write): @ 0x0822d77c: expected 0xfdf74a20, actual 0xfdf74a60)

FAILURE (read/write): @ 0x08d0f4c4: expected 0xfdcbc2ce, actual 0xfdcac2ce)

FAILURE (read/write): @ 0x08d0f4e4: expected 0xfdcbc2c6, actual 0xfdcac2c6)

FAILURE (read/write): @ 0x08d174c4: expected 0xfdcba2ce, actual 0xfdcaa2ce)

FAILURE (read/write): @ 0x08d1f4cc: expected 0xfdcb82cc, actual 0xfdca82cc)

FAILURE (read/write): @ 0x08d1f4e4: expected 0xfdcb82c6, actual 0xfdca82c6)

FAILURE (read/write): @ 0x08d274e0: expected 0xfdcb62c7, actual 0xfdca62c7)

I have run this test multiple times but the addresses on which errors
occur remains almost the same ( +/- few different addresses). At
first, I thought that reason of such failures can be wrong DDR timing
parameters used for initializing memory controller but what made me
confuse was that the errors occur on same addresses on same board on
multiple retries and reboots.

I have also noticed that the difference between actual and expected
data is always 1-bit e.g. expected 0xfdcba2ce, actual 0xfdcaa2ce.

Can anyone provide some hint what might be the reason or source of error?

P.S: Running mtest on different boards results in same read/write
errors but the failure addresses are different on different boards.