From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 15/16] drm/i915: Rename ilk_wm_max to ilk_compute_wm_maximums Date: Fri, 11 Oct 2013 14:07:03 -0300 Message-ID: References: <1381335490-4906-1-git-send-email-ville.syrjala@linux.intel.com> <1381335490-4906-16-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ob0-f182.google.com (mail-ob0-f182.google.com [209.85.214.182]) by gabe.freedesktop.org (Postfix) with ESMTP id 8828DE8177 for ; Fri, 11 Oct 2013 10:07:04 -0700 (PDT) Received: by mail-ob0-f182.google.com with SMTP id wn1so2963386obc.41 for ; Fri, 11 Oct 2013 10:07:03 -0700 (PDT) In-Reply-To: <1381335490-4906-16-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org 2013/10/9 : > From: Ville Syrj=E4l=E4 > > Makes the intention more clear. > > Signed-off-by: Ville Syrj=E4l=E4 Thanks! Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 022cd5b..7b52e39 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2371,11 +2371,11 @@ static unsigned int ilk_fbc_wm_max(void) > return 15; > } > > -static void ilk_wm_max(struct drm_device *dev, > - int level, > - const struct intel_wm_config *config, > - enum intel_ddb_partitioning ddb_partitioning, > - struct hsw_wm_maximums *max) > +static void ilk_compute_wm_maximums(struct drm_device *dev, > + int level, > + const struct intel_wm_config *config, > + enum intel_ddb_partitioning ddb_parti= tioning, > + struct hsw_wm_maximums *max) > { > max->pri =3D ilk_plane_wm_max(dev, level, config, ddb_partitionin= g, false); > max->spr =3D ilk_plane_wm_max(dev, level, config, ddb_partitionin= g, true); > @@ -2626,7 +2626,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *= crtc, > struct hsw_wm_maximums max; > > /* LP0 watermarks always use 1/2 DDB partitioning */ > - ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max); > + ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max= ); > > for (level =3D 0; level <=3D max_level; level++) > ilk_compute_wm_level(dev_priv, level, params, > @@ -2954,12 +2954,12 @@ static void haswell_update_wm(struct drm_crtc *cr= tc) > > intel_crtc->wm.active =3D pipe_wm; > > - ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, &max); > + ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max= ); > ilk_wm_merge(dev, &max, &lp_wm_1_2); > > /* 5/6 split only in single pipe config on IVB+ */ > if (INTEL_INFO(dev)->gen >=3D 7 && config.num_pipes_active =3D=3D= 1) { > - ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, &max); > + ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5= _6, &max); > ilk_wm_merge(dev, &max, &lp_wm_5_6); > > best_lp_wm =3D hsw_find_best_result(dev, &lp_wm_1_2, &lp_= wm_5_6); > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Paulo Zanoni