From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 17/16] drm/i915: Check 5/6 DDB split only when sprites are enabled Date: Fri, 11 Oct 2013 14:21:58 -0300 Message-ID: References: <20131011082629.GR13047@intel.com> <1381494386-13380-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-oa0-f50.google.com (mail-oa0-f50.google.com [209.85.219.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 78BC5E6C40 for ; Fri, 11 Oct 2013 10:21:58 -0700 (PDT) Received: by mail-oa0-f50.google.com with SMTP id j1so2634971oag.37 for ; Fri, 11 Oct 2013 10:21:58 -0700 (PDT) In-Reply-To: <1381494386-13380-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: =?ISO-8859-1?Q?Ville_Syrj=E4l=E4?= Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org 2013/10/11 : > From: Ville Syrj=E4l=E4 > > Using the 5/6 DDB split make sense only when sprites are enabled. > So check that before we waste any cycles computing the merged > watermarks with the 5/6 DDB split. > > Signed-off-by: Ville Syrj=E4l=E4 Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 211a946..214a8de 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2958,7 +2958,8 @@ static void haswell_update_wm(struct drm_crtc *crtc) > ilk_wm_merge(dev, &max, &lp_wm_1_2); > > /* 5/6 split only in single pipe config on IVB+ */ > - if (INTEL_INFO(dev)->gen >=3D 7 && config.num_pipes_active =3D=3D= 1) { > + if (INTEL_INFO(dev)->gen >=3D 7 && > + config.num_pipes_active =3D=3D 1 && config.sprites_enabled) { > ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5= _6, &max); > ilk_wm_merge(dev, &max, &lp_wm_5_6); > > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Paulo Zanoni