From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 08/35] drm/i915: Change the watermark latency type to uint16_t Date: Tue, 30 Jul 2013 17:01:17 -0300 Message-ID: References: <1373014667-19484-1-git-send-email-ville.syrjala@linux.intel.com> <1373014667-19484-9-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-oa0-f41.google.com (mail-oa0-f41.google.com [209.85.219.41]) by gabe.freedesktop.org (Postfix) with ESMTP id AD8F0E5D1F for ; Tue, 30 Jul 2013 13:01:18 -0700 (PDT) Received: by mail-oa0-f41.google.com with SMTP id j6so7796911oag.0 for ; Tue, 30 Jul 2013 13:01:18 -0700 (PDT) In-Reply-To: <1373014667-19484-9-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org 2013/7/5 : > From: Ville Syrj=E4l=E4 > > The latency values fit in uint16_t, so let's save a few bytes. > > Signed-off-by: Ville Syrj=E4l=E4 Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 981416c..2239cdb 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2338,7 +2338,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, str= uct drm_crtc *crtc) > > static void hsw_compute_wm_parameters(struct drm_device *dev, > struct hsw_pipe_wm_parameters *para= ms, > - uint32_t *wm, > + uint16_t *wm, > struct hsw_wm_maximums *lp_max_1_2, > struct hsw_wm_maximums *lp_max_5_6) > { > @@ -2411,7 +2411,7 @@ static void hsw_compute_wm_parameters(struct drm_de= vice *dev, > > static void hsw_compute_wm_results(struct drm_device *dev, > struct hsw_pipe_wm_parameters *params, > - uint32_t *wm, > + uint16_t *wm, > struct hsw_wm_maximums *lp_maximums, > struct hsw_wm_values *results) > { > @@ -2593,7 +2593,7 @@ static void haswell_update_wm(struct drm_device *de= v) > struct hsw_wm_maximums lp_max_1_2, lp_max_5_6; > struct hsw_pipe_wm_parameters params[3]; > struct hsw_wm_values results_1_2, results_5_6, *best_results; > - uint32_t wm[5]; > + uint16_t wm[5]; > enum hsw_data_buf_partitioning partitioning; > > hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5= _6); > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Paulo Zanoni