From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WudTq-0005IL-6E for qemu-devel@nongnu.org; Wed, 11 Jun 2014 04:02:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WudTj-0000yE-UE for qemu-devel@nongnu.org; Wed, 11 Jun 2014 04:01:58 -0400 Received: from smtp1.iitd.ernet.in ([103.27.9.45]:58496) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WudTj-0000xi-76 for qemu-devel@nongnu.org; Wed, 11 Jun 2014 04:01:51 -0400 Received: from localhost (localhost [127.0.0.1]) by smtp1.iitd.ernet.in (Postfix) with ESMTP id 70B744177D for ; Wed, 11 Jun 2014 13:31:46 +0530 (IST) Received: from smtp1.iitd.ernet.in ([127.0.0.1]) by localhost (smtp1.iitd.ernet.in [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id axnb0p-Ub8bl for ; Wed, 11 Jun 2014 13:31:41 +0530 (IST) Received: from mail-ig0-f172.google.com (mail-ig0-f172.google.com [209.85.213.172]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sbansal) by smtp1.iitd.ernet.in (Postfix) with ESMTPSA id 4134D41770 for ; Wed, 11 Jun 2014 13:31:40 +0530 (IST) Received: by mail-ig0-f172.google.com with SMTP id l13so6114038iga.11 for ; Wed, 11 Jun 2014 01:01:38 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: Date: Wed, 11 Jun 2014 13:31:38 +0530 Message-ID: From: Sorav Bansal Content-Type: text/plain; charset=UTF-8 Subject: [Qemu-devel] Fwd: Patch: fix to gen_mcrxr() in target-ppc/translate.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf [I had posted to qemu-ppc list earlier, reposting to qemu-devel also on being suggested to do so. Also adding some description about the patch] Hi, I saw a minor bug in the gen_mcrxr() function in target-ppc/translate.c. Here is the patch for your consideration. I have verified the patch by checking the generated code using a SAT-solver based verification tool. thanks, Sorav Patch Description: As I see it, the XER[SO], XER[OV], and XER[CA] flags are stored in the least significant bit (bit 0) of their respective registers. They need to be shifted left (by their respective offsets) to generate the final XER value. The old code seemed to be assuming that the flags are stored in bit 2, and was shifting them right (by their respective offsets), which seems incorrect. >>From 31f39e258cbb289c2e0a3c3adde87cde7ae02a15 Mon Sep 17 00:00:00 2001 From: Sorav Bansal Date: Tue, 10 Jun 2014 19:01:12 +0530 Subject: [PATCH] Fix to the translation of mcrxr instruction --- target-ppc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f089014..b513998 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4147,8 +4147,8 @@ static void gen_mcrxr(DisasContext *ctx) tcg_gen_trunc_tl_i32(t0, cpu_so); tcg_gen_trunc_tl_i32(t1, cpu_ov); tcg_gen_trunc_tl_i32(dst, cpu_ca); - tcg_gen_shri_i32(t0, t0, 2); - tcg_gen_shri_i32(t1, t1, 1); + tcg_gen_shli_i32(dst, dst, 2); + tcg_gen_shli_i32(t1, t1, 1); tcg_gen_or_i32(dst, dst, t0); tcg_gen_or_i32(dst, dst, t1); tcg_temp_free_i32(t0); -- 1.7.9.5