From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C882BC433F5 for ; Mon, 4 Oct 2021 07:31:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B708261090 for ; Mon, 4 Oct 2021 07:31:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230145AbhJDHdc (ORCPT ); Mon, 4 Oct 2021 03:33:32 -0400 Received: from smtp-relay-internal-1.canonical.com ([185.125.188.123]:40410 "EHLO smtp-relay-internal-1.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230004AbhJDHda (ORCPT ); Mon, 4 Oct 2021 03:33:30 -0400 Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id C7335402C9 for ; Mon, 4 Oct 2021 07:31:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1633332700; bh=yMz7a2U4h7tYNWu8HY/sX3yR4RwoKAQESOaigGzONNc=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=GRDTCJT1m4fZbKTsLeOHaP3WHDe4BrsXV8VT2ghTEEuQ3WjywQEPILgdrohlzDQs/ SSQdJJYJkKZ2oMbn+Fbfhwp5WEibcZCo1yezaMbjO/Qsr9DoxfDI5LtqOEimDrpDKD YR0ScX2/13n3BaYooN5Z2OfKIYJkUTw2oJV+tQpHlJHtSV3j0/Z9sSxeTtkIaLHgPp L0F7EdFlunLfXAP3qHe44UCor6vFM5j5qLASEPjXmTrPttLyvpTfu25b/zWB4lyYpZ 8w5an+sRnuDlAPjsoYuP1KGV7AT2sGJ6a/inKCRug8Es5xKRKU4jPNf/TkAz9jEE9S AjLic5mn+jLKA== Received: by mail-ed1-f70.google.com with SMTP id w8-20020a50c448000000b003dae8d38037so3196642edf.8 for ; Mon, 04 Oct 2021 00:31:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yMz7a2U4h7tYNWu8HY/sX3yR4RwoKAQESOaigGzONNc=; b=KDl0wlepc5NooAHyH6mqcD/OJsJw7d3GbuWVBEIzkVbGvFMmrWHmjzQZfGx7KrWpRE QPE/RgSLLLeOGGFDlsbBtTYDqxOHcR0C8nQPScOfnYHaUz16ONzwnRksRj7bYB38PeWM Y2NVk63guV6b0buxJA5LOjnGODCcM885IERgq+L24+tUl9Z94Wv3ReYKmUhVKSQLtb1G ylXPl/DstVlb6CzKFNnLYWTcYi5TcpZz3S3r5bnI27FEJjzgMEbbs7DAYJYFZhUW+9Df FRCftLeaOom27mnVOh6jBZ9QUEwnXvnqq8DbvjsgwbRQCMx3j9vJhr/omPEF2lWLpYfv 4Hvw== X-Gm-Message-State: AOAM532zhT7sA4ODN2yobK+pbepLB99x7kSJVp9I5DOjICG2FyeKmfze FAJxwH8vXuf6YT8iw6ME92FsXjOaND/wNU2tiP7SbF3UPO4++3zpaDHnrsMK68tjAC1RR1MGoMx rxcOSjIMIkPmlgk+UxHjquMEoMOjH0FtYwjZR3cpVBiIggolm6mfMyssGTw== X-Received: by 2002:a17:906:ed1:: with SMTP id u17mr16035058eji.304.1633332699389; Mon, 04 Oct 2021 00:31:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHAhKgffAcQ9Ok5Z/TiUwt7wu3AralX9OFoEmbqnI+tZ2U37Ef48COxQfqHUgegwirzhI9KM/V5gt3fvDAjXQ= X-Received: by 2002:a17:906:ed1:: with SMTP id u17mr16035032eji.304.1633332699195; Mon, 04 Oct 2021 00:31:39 -0700 (PDT) MIME-Version: 1.0 References: <20210929145113.1935778-1-alexandre.ghiti@canonical.com> <20210929145113.1935778-5-alexandre.ghiti@canonical.com> <748a2c58-4d69-6457-0aa5-89797cb45a5c@sholland.org> In-Reply-To: <748a2c58-4d69-6457-0aa5-89797cb45a5c@sholland.org> From: Alexandre Ghiti Date: Mon, 4 Oct 2021 09:31:26 +0200 Message-ID: Subject: Re: [PATCH v2 04/10] riscv: Implement sv48 support To: Samuel Holland Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Zong Li , Anup Patel , Atish Patra , Christoph Hellwig , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Ard Biesheuvel , Arnd Bergmann , Kees Cook , Guo Ren , Heinrich Schuchardt , Mayuresh Chitale , linux-doc@vger.kernel.org, linux-riscv , "linux-kernel@vger.kernel.org List" , kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 4, 2021 at 3:34 AM Samuel Holland wrote: > > On 9/29/21 9:51 AM, Alexandre Ghiti wrote: > > By adding a new 4th level of page table, give the possibility to 64bit > > kernel to address 2^48 bytes of virtual address: in practice, that offers > > 128TB of virtual address space to userspace and allows up to 64TB of > > physical memory. > > > > If the underlying hardware does not support sv48, we will automatically > > fallback to a standard 3-level page table by folding the new PUD level into > > PGDIR level. In order to detect HW capabilities at runtime, we > > use SATP feature that ignores writes with an unsupported mode. > > > > Signed-off-by: Alexandre Ghiti > > --- > > arch/riscv/Kconfig | 4 +- > > arch/riscv/include/asm/csr.h | 3 +- > > arch/riscv/include/asm/fixmap.h | 1 + > > arch/riscv/include/asm/kasan.h | 2 +- > > arch/riscv/include/asm/page.h | 10 + > > arch/riscv/include/asm/pgalloc.h | 40 ++++ > > arch/riscv/include/asm/pgtable-64.h | 108 ++++++++++- > > arch/riscv/include/asm/pgtable.h | 13 +- > > arch/riscv/kernel/head.S | 3 +- > > arch/riscv/mm/context.c | 4 +- > > arch/riscv/mm/init.c | 237 ++++++++++++++++++++---- > > arch/riscv/mm/kasan_init.c | 91 +++++++-- > > drivers/firmware/efi/libstub/efi-stub.c | 2 + > > 13 files changed, 453 insertions(+), 65 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 13e9c4298fbc..69c5533955ed 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -149,7 +149,7 @@ config PAGE_OFFSET > > hex > > default 0xC0000000 if 32BIT > > default 0x80000000 if 64BIT && !MMU > > - default 0xffffffe000000000 if 64BIT > > + default 0xffffc00000000000 if 64BIT > > > > config ARCH_FLATMEM_ENABLE > > def_bool !NUMA > > @@ -197,7 +197,7 @@ config FIX_EARLYCON_MEM > > > > config PGTABLE_LEVELS > > int > > - default 3 if 64BIT > > + default 4 if 64BIT > > default 2 > > > > config LOCKDEP_SUPPORT > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 87ac65696871..3fdb971c7896 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -40,14 +40,13 @@ > > #ifndef CONFIG_64BIT > > #define SATP_PPN _AC(0x003FFFFF, UL) > > #define SATP_MODE_32 _AC(0x80000000, UL) > > -#define SATP_MODE SATP_MODE_32 > > #define SATP_ASID_BITS 9 > > #define SATP_ASID_SHIFT 22 > > #define SATP_ASID_MASK _AC(0x1FF, UL) > > #else > > #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) > > #define SATP_MODE_39 _AC(0x8000000000000000, UL) > > -#define SATP_MODE SATP_MODE_39 > > +#define SATP_MODE_48 _AC(0x9000000000000000, UL) > > #define SATP_ASID_BITS 16 > > #define SATP_ASID_SHIFT 44 > > #define SATP_ASID_MASK _AC(0xFFFF, UL) > > diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h > > index 54cbf07fb4e9..58a718573ad6 100644 > > --- a/arch/riscv/include/asm/fixmap.h > > +++ b/arch/riscv/include/asm/fixmap.h > > @@ -24,6 +24,7 @@ enum fixed_addresses { > > FIX_HOLE, > > FIX_PTE, > > FIX_PMD, > > + FIX_PUD, > > FIX_TEXT_POKE1, > > FIX_TEXT_POKE0, > > FIX_EARLYCON_MEM_BASE, > > diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h > > index a2b3d9cdbc86..1dcf5fa93aa0 100644 > > --- a/arch/riscv/include/asm/kasan.h > > +++ b/arch/riscv/include/asm/kasan.h > > @@ -27,7 +27,7 @@ > > */ > > #define KASAN_SHADOW_SCALE_SHIFT 3 > > > > -#define KASAN_SHADOW_SIZE (UL(1) << ((CONFIG_VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > +#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > Does this change belong in patch 1, where you remove CONFIG_VA_BITS? Indeed, I fixed KASAN in this version and wrongly rebased the changes. Thanks! Alex > > Regards, > Samuel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2A05C433EF for ; Mon, 4 Oct 2021 07:32:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B14F61029 for ; Mon, 4 Oct 2021 07:32:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4B14F61029 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=canonical.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Oct 4, 2021 at 3:34 AM Samuel Holland wrote: > > On 9/29/21 9:51 AM, Alexandre Ghiti wrote: > > By adding a new 4th level of page table, give the possibility to 64bit > > kernel to address 2^48 bytes of virtual address: in practice, that offers > > 128TB of virtual address space to userspace and allows up to 64TB of > > physical memory. > > > > If the underlying hardware does not support sv48, we will automatically > > fallback to a standard 3-level page table by folding the new PUD level into > > PGDIR level. In order to detect HW capabilities at runtime, we > > use SATP feature that ignores writes with an unsupported mode. > > > > Signed-off-by: Alexandre Ghiti > > --- > > arch/riscv/Kconfig | 4 +- > > arch/riscv/include/asm/csr.h | 3 +- > > arch/riscv/include/asm/fixmap.h | 1 + > > arch/riscv/include/asm/kasan.h | 2 +- > > arch/riscv/include/asm/page.h | 10 + > > arch/riscv/include/asm/pgalloc.h | 40 ++++ > > arch/riscv/include/asm/pgtable-64.h | 108 ++++++++++- > > arch/riscv/include/asm/pgtable.h | 13 +- > > arch/riscv/kernel/head.S | 3 +- > > arch/riscv/mm/context.c | 4 +- > > arch/riscv/mm/init.c | 237 ++++++++++++++++++++---- > > arch/riscv/mm/kasan_init.c | 91 +++++++-- > > drivers/firmware/efi/libstub/efi-stub.c | 2 + > > 13 files changed, 453 insertions(+), 65 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 13e9c4298fbc..69c5533955ed 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -149,7 +149,7 @@ config PAGE_OFFSET > > hex > > default 0xC0000000 if 32BIT > > default 0x80000000 if 64BIT && !MMU > > - default 0xffffffe000000000 if 64BIT > > + default 0xffffc00000000000 if 64BIT > > > > config ARCH_FLATMEM_ENABLE > > def_bool !NUMA > > @@ -197,7 +197,7 @@ config FIX_EARLYCON_MEM > > > > config PGTABLE_LEVELS > > int > > - default 3 if 64BIT > > + default 4 if 64BIT > > default 2 > > > > config LOCKDEP_SUPPORT > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > > index 87ac65696871..3fdb971c7896 100644 > > --- a/arch/riscv/include/asm/csr.h > > +++ b/arch/riscv/include/asm/csr.h > > @@ -40,14 +40,13 @@ > > #ifndef CONFIG_64BIT > > #define SATP_PPN _AC(0x003FFFFF, UL) > > #define SATP_MODE_32 _AC(0x80000000, UL) > > -#define SATP_MODE SATP_MODE_32 > > #define SATP_ASID_BITS 9 > > #define SATP_ASID_SHIFT 22 > > #define SATP_ASID_MASK _AC(0x1FF, UL) > > #else > > #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) > > #define SATP_MODE_39 _AC(0x8000000000000000, UL) > > -#define SATP_MODE SATP_MODE_39 > > +#define SATP_MODE_48 _AC(0x9000000000000000, UL) > > #define SATP_ASID_BITS 16 > > #define SATP_ASID_SHIFT 44 > > #define SATP_ASID_MASK _AC(0xFFFF, UL) > > diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h > > index 54cbf07fb4e9..58a718573ad6 100644 > > --- a/arch/riscv/include/asm/fixmap.h > > +++ b/arch/riscv/include/asm/fixmap.h > > @@ -24,6 +24,7 @@ enum fixed_addresses { > > FIX_HOLE, > > FIX_PTE, > > FIX_PMD, > > + FIX_PUD, > > FIX_TEXT_POKE1, > > FIX_TEXT_POKE0, > > FIX_EARLYCON_MEM_BASE, > > diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h > > index a2b3d9cdbc86..1dcf5fa93aa0 100644 > > --- a/arch/riscv/include/asm/kasan.h > > +++ b/arch/riscv/include/asm/kasan.h > > @@ -27,7 +27,7 @@ > > */ > > #define KASAN_SHADOW_SCALE_SHIFT 3 > > > > -#define KASAN_SHADOW_SIZE (UL(1) << ((CONFIG_VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > +#define KASAN_SHADOW_SIZE (UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT)) > > Does this change belong in patch 1, where you remove CONFIG_VA_BITS? Indeed, I fixed KASAN in this version and wrongly rebased the changes. Thanks! Alex > > Regards, > Samuel _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv