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spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=i8Wl3UuMRC2nlOUxwD1uv9KtvlUtqhpl7emd3rUdLLE=; b=dcOAvFQKh9Us72rorLrUBftxkjuHxFY2CW0RlJE2aKy9QSqL2hos1p/nZCxdj+aycZA7rilGFV52CdcvFgjrWyNlQ/Amnw9DPps9/sBswRXvLbr3SAafGYk05IOEphafZh6iIt4Ti4F7HQ98f/KMKQ2LxIrgBiz57j8zg0Ob0GA= From: Bertrand Marquis To: Julien Grall CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Volodymyr Babchuk Subject: Re: [PATCH v3 7/7] xen/arm: Sanitize CTR_EL0 and emulate it if needed Thread-Topic: [PATCH v3 7/7] xen/arm: Sanitize CTR_EL0 and emulate it if needed Thread-Index: AQHXmbPyaqNt71/0B0WMx26sIln5R6uHdm2AgAYrXACAABkoAIAAGG+A Date: Tue, 31 Aug 2021 16:15:20 +0000 Message-ID: References: <14b1639e-c9e4-f8fb-e921-73d7f28681ac@xen.org> <98E8FB9D-3372-47D2-92F7-8AD401AC1092@arm.com> <6705127a-bde2-36cd-0fed-900eb1eace03@xen.org> In-Reply-To: <6705127a-bde2-36cd-0fed-900eb1eace03@xen.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3654.120.0.1.13) Authentication-Results-Original: xen.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2021 16:15:30.0533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9b70e50-a540-4898-3b1f-08d96c9a8d4e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6282 Hi Julien, > On 31 Aug 2021, at 15:47, Julien Grall wrote: >=20 >=20 >=20 > On 31/08/2021 14:17, Bertrand Marquis wrote: >> Hi Julien, >=20 > Hi Bertrand, >=20 >>> On 27 Aug 2021, at 16:05, Julien Grall wrote: >>>=20 >>> Hi Bertrand, >>>=20 >>> On 25/08/2021 14:18, Bertrand Marquis wrote: >>>> Sanitize CTR_EL0 value between cores. >>>> In most cases different values will taint Xen but if different >>>> i-cache policies are found, we choose the one which will be compatible >>>> between all cores in terms of invalidation/data cache flushing strateg= y. >>>=20 >>> I understand that all the CPUs in Xen needs to agree on the cache flush= strategy. However... >>>=20 >>>> In this case we need to activate the TID2 bit in HCR to emulate the >>>> TCR_EL0 register for guests. This patch is not activating TID2 bit all >>>> the time to limit the overhead when possible. >>>=20 >>> as we discussed in an earlier version, a vCPU is unlikely (at least in = short/medium) to be able move across pCPU of different type. So the vCPU wo= uld be pinned to a set of pCPUs. IOW, the guest would have to be big.LITTLE= aware and therefore would be able to do its own strategy decision. >>>=20 >>> So I think we should be able to get away from trappings the registers. >> I do agree that we should be able to get away from that in the long term= once >> we have cpupools properly set but right now this is the only way to have >> something useable (I will not say right). >> I will work on finding a way to setup properly cpupools (or something el= se as >> we discussed earlier) but in the short term I think this is the best we = can do. >=20 > My concern is you are making look like Xen will be able to deal nicely wi= th big.LITTLE when in fact there are a lot more potential issue by allow a = vCPU moving accross pCPU of different type (the errata is one example). I agree and this is why Xen is tainted. >=20 >> An other solution would be to discard this patch from the serie for now = until >> I have worked a proper solution for this case. >> Should we discard or merge or do you have an other idea ? > Please correct me if I am wrong, at the moment, it doesn't look like this= patch will be part of the longer plan. If so, then I think it should be pa= rked for now. Not sure it depends on what the final solution would be but this is highly = possible I agree. >=20 > This would also have the advantage to avoid spending too much time on res= olving the emulation issue I mentioned in my previous answer. >=20 > No need to resend a new version of this series yet. You can wait until th= e rest of the series get more feedback. Ok, I will wait for feedback and next serie will not include this patch any= more. >=20 > [...] >=20 >> If we get interrupted, someone could program CSSELR differently and the = next read >> will not be reflecting what the guest actually wants to do >=20 > AFAICT, CSSELR is preserved during the context switch of vCPU. So that so= meone would have to be Xen, right? >=20 > If so, what you describe would also be an issue even if we didn't trap th= e register. Therefore, if Xen would ever use CSSELR, then that code would n= eed to save the value, use the register and then restore the value with pre= emption disabled. I could just remove the comment, I added it as information, but if you thin= k it is misleading no problem. Anyway as we will park this for now no need to discuss that further. Cheers Bertrand >=20 >> The code is not preemptible right now so this cannot be an issue but I a= dded the >> comment more as a warning. >> This is not something from the documentation, this is because value writ= ten >> in CSSELR is defining what is read from CCSIDR >>>=20 >>>> + WRITE_SYSREG(v->arch.csselr, CSSELR_EL1); >>>> + set_user_reg(regs, regidx, READ_SYSREG(CCSIDR_EL1)); >>>> + } >=20 > Cheers, >=20 > --=20 > Julien Grall