From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oa1-f47.google.com (mail-oa1-f47.google.com [209.85.160.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FF9023A8 for ; Thu, 23 Jun 2022 21:00:48 +0000 (UTC) Received: by mail-oa1-f47.google.com with SMTP id 586e51a60fabf-101dc639636so1078272fac.6 for ; Thu, 23 Jun 2022 14:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YFZn+6KIIWp9gABMuWoR/dKCyEO4Zr5Rzf3hYjExeKM=; b=SLSQuGNHJV37cOtMEFG3uwEzqjiH7rjf8lBN6dlJxGi5K+qWAXGF9NaHB34fDTGnnG 5BO6KBC5M9pv9FZxmNICTOXTmCjuDmEFXatrzbKgwFgT5Xwxwx7ok4mIUzi9Zaw9ZH9j hPKLQ5ipJETzDMCc1BbrD2MIcLQZi9LLB3BXeXoa6G+i5m3Lx1QgXn15IUHKZkjT/GnV HRCmcy3hXV0Lzzz0YERx53i6O5/3isS7ABZxFZgI7IoNX1ywx7gub33tTSzKErrXnsAa P84cUd7O2iPNeHWqT+MEBYdPFRU5j5M8eVJefEmJlF34ljWH6wgP3O2BHg+Wg97ictpa mBvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YFZn+6KIIWp9gABMuWoR/dKCyEO4Zr5Rzf3hYjExeKM=; b=1YCd9GkXZbTT9BqMbcsfDe/aGLp3PNkL0FVvHSa9f55PfEdf7VvTZnGz51n6T7CnaI k8NaUjj7zZ+ugvEbSSmKWHsRCN5gs7Wxn1eTVSY24ABd/ArHoaEAmm8wGWYDXJYSC4eh LVdtC81gJmWzrEk+HfNGkQWS0H7c8TcDFkIhEJd4vlh7V+yk8gR/Im1kGN3K3cjBSmhG 8eLCkZ1BXj+K2yxACLKy1Vf7xCEAsH3cF41mIaQck7BZNCKsHFXledQiCGKjlakluki7 IHdlZj7SwEPT/MUY2l+ZHjCrCHxwVkTRuNIRUIf0+RADNoyPmr+XAjvEyFZNvMwcC3ck n1jA== X-Gm-Message-State: AJIora9EKsJ7sbqenvnhFNbhXHy8GFVSCe4BSx8RqPp8xFLzvlw/rURe zIoq9aCcwkjwf8TxZ0rs3wZ2VXLk10xBUZv7DjmRVA== X-Google-Smtp-Source: AGRyM1u+6NKJmTl5AxpFSRq+8aQW2BDLG8AB1hBjiM3k8m1AvB1fSE0FBJqFqc2vKOE78+7yBQ8YcxTcWmTVOZli3B8= X-Received: by 2002:a05:6870:b616:b0:e2:f8bb:5eb with SMTP id cm22-20020a056870b61600b000e2f8bb05ebmr3694057oab.218.1656018047090; Thu, 23 Jun 2022 14:00:47 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: In-Reply-To: From: Marc Orr Date: Thu, 23 Jun 2022 14:00:36 -0700 Message-ID: Subject: Re: [PATCH Part2 v6 04/49] x86/sev: set SYSCFG.MFMD To: Ashish Kalra Cc: x86 , LKML , kvm list , linux-coco@lists.linux.dev, linux-mm@kvack.org, Linux Crypto Mailing List , Thomas Gleixner , Ingo Molnar , Joerg Roedel , "Lendacky, Thomas" , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , "Roth, Michael" , Vlastimil Babka , "Kirill A . Shutemov" , Andi Kleen , Tony Luck , Sathyanarayanan Kuppuswamy , Alper Gun , "Dr . David Alan Gilbert" , jarkko@kernel.org Content-Type: text/plain; charset="UTF-8" On Mon, Jun 20, 2022 at 4:02 PM Ashish Kalra wrote: > > From: Brijesh Singh > > SEV-SNP FW >= 1.51 requires that SYSCFG.MFMD must be set. > > Subsequent CCP patches while require 1.51 as the minimum SEV-SNP > firmware version. > > Signed-off-by: Brijesh Singh > --- > arch/x86/include/asm/msr-index.h | 3 +++ > arch/x86/kernel/sev.c | 24 ++++++++++++++++++++++++ > 2 files changed, 27 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 57a8280e283a..1e36f16daa56 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -587,6 +587,9 @@ > #define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT) > #define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25 > #define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT) > +#define MSR_AMD64_SYSCFG_MFDM_BIT 19 > +#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT) nit: Similar to the previous patch, the alignment here doesn't look right. The bad alignment can be viewed on the github version of this patch: https://github.com/AMDESE/linux/commit/6d4469b86f90e67119ff110230857788a0d9dbd0 > + > #define MSR_K8_INT_PENDING_MSG 0xc0010055 > /* C1E active bits in int pending message */ > #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 > diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c > index 3a233b5d47c5..25c7feb367f6 100644 > --- a/arch/x86/kernel/sev.c > +++ b/arch/x86/kernel/sev.c > @@ -2257,6 +2257,27 @@ static __init void snp_enable(void *arg) > __snp_enable(smp_processor_id()); > } > > +static int __mfdm_enable(unsigned int cpu) > +{ > + u64 val; > + > + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) > + return 0; > + > + rdmsrl(MSR_AMD64_SYSCFG, val); > + > + val |= MSR_AMD64_SYSCFG_MFDM; Can we do this inside `__snp_enable()`, above? Then, we'll execute if a hotplug event happens as well. static int __snp_enable(unsigned int cpu) { u64 val; if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) return 0; rdmsrl(MSR_AMD64_SYSCFG, val); val |= MSR_AMD64_SYSCFG_SNP_EN; val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN; val |= MSR_AMD64_SYSCFG_MFDM; wrmsrl(MSR_AMD64_SYSCFG, val); return 0; } > + > + wrmsrl(MSR_AMD64_SYSCFG, val); > + > + return 0; > +} > + > +static __init void mfdm_enable(void *arg) > +{ > + __mfdm_enable(smp_processor_id()); > +} > + > static bool get_rmptable_info(u64 *start, u64 *len) > { > u64 calc_rmp_sz, rmp_sz, rmp_base, rmp_end, nr_pages; > @@ -2325,6 +2346,9 @@ static __init int __snp_rmptable_init(void) > /* Flush the caches to ensure that data is written before SNP is enabled. */ > wbinvd_on_all_cpus(); > > + /* MFDM must be enabled on all the CPUs prior to enabling SNP. */ > + on_each_cpu(mfdm_enable, NULL, 1); > + > /* Enable SNP on all CPUs. */ > on_each_cpu(snp_enable, NULL, 1); > > -- > 2.25.1 >