On Fri, Oct 31, 2014 at 5:27 AM, Rodrigo Vivi <= rodrigo.vivi@intel.com> wr= ote:
>
> Global GTT doesn't have pat_sel[2:0] so it always = point to pat_sel =3D 000;
> So the only way to avoid screen corruptio= ns is setting PAT 0 to Uncached.
>
> MOCS can still be used tho= ugh. But if userspace is trusting PTE for
> cache selection the safes= t thing to do is to let caches disabled.
>
> BSpec: "For G= GTT, there is NO pat_sel[2:0] from the entry,
> so RTL will always us= e the value corresponding to pat_sel =3D 000"
>
> v2: Clea= ner patch as suggested by Chris.
>
> Reference: https://bugs.freedesktop.= org/show_bug.cgi?id=3D85576
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: = James Ausmus <james.ausmus@int= el.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> = =C2=A0drivers/gpu/drm/i915/i915_gem_gtt.c | 9 +++++++++
> =C2=A01 fil= e changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i91= 5/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cb7ada= b..ae568a2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>= +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1920,6 +1920,15 @@ s= tatic void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
>= ; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 GEN8_PPAT(6, GEN8_PPAT_W= B | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
> =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |= GEN8_PPAT_AGE(3));
>
> + =C2=A0 =C2=A0 =C2=A0 if (!USES_PPGTT(= dev_priv->dev))
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
&g= t; + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* so RTL will a= lways use the value corresponding to
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0* pat_sel =3D 000".
> + =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* So let's disable cache for = GGTT to avoid screen corruptions.
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0* MOCS still can be used though.
> + =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> + =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pat =3D GEN8_PPAT(0, GEN8_PPAT_UC);
&= gt; +
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* XXX: spec defines this as 2 di= stinct registers. It's unclear if a 64b
> =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0* write would work. */
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 I91= 5_WRITE(GEN8_PRIVATE_PAT, pat);
> --
> 1.9.3
>

Tested<= /span>-<= span class=3D"" style=3D"font-family:arial,sans-serif;font-size:13px">by: James Aus= mus <james.ausmus@intel.com>

--

James Ausmus
Sr. Software Engineer=
SSG-OTC ChromeOS Integration