From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ilya Yanok <ilya.yanok@cogentembedded.com>
Date: Mon, 9 Jul 2012 02:32:46 +0400
Subject: [U-Boot] [PATCH] smsc95xx: align buffers to cache line size
In-Reply-To: <201207082331.29059.marek.vasut@gmail.com>
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	<201207082331.29059.marek.vasut@gmail.com>
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Dear Marek,

On Mon, Jul 9, 2012 at 1:31 AM, Marek Vasut <marek.vasut@gmail.com> wrote:

> > non-ARMv7 system now to do some testing...
> > But it used to work without any alignment, right? (with disabled dcache,
> of
> > course)
> > That makes me think that data buffers don't need any alignment (from USB
> > pov, not cache) and 32-byte alignment is required for internal structs
> > only.
>
> > Hm.. I have to admit I'm not very much into USB specs and I don't have
> any
> See ehci-r10.pdf ... chapter 3.5 ... the buffer pointer has to be aligned
> too it
> seems.
>

But in practice it works without any alignment... ok, you made me read the
spec ;)
page 55: "For the page 0 current offset interpretation, this field is the
byte offset into the current page"

Regards, Ilya.