From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 262B7C43334 for ; Wed, 15 Jun 2022 10:28:28 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id BC2E76066D; Wed, 15 Jun 2022 10:28:27 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z91iVo2GWFzd; Wed, 15 Jun 2022 10:28:27 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by smtp3.osuosl.org (Postfix) with ESMTPS id BA23D607C1; Wed, 15 Jun 2022 10:28:26 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 8FD48C0032; Wed, 15 Jun 2022 10:28:26 +0000 (UTC) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) by lists.linuxfoundation.org (Postfix) with ESMTP id F2B80C002D for ; Wed, 15 Jun 2022 10:28:24 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id E21FD83E16 for ; Wed, 15 Jun 2022 10:28:24 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Authentication-Results: smtp1.osuosl.org (amavisd-new); dkim=pass (2048-bit key) header.d=linaro.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Em0E8UgT9_N6 for ; Wed, 15 Jun 2022 10:28:24 +0000 (UTC) X-Greylist: whitelisted by SQLgrey-1.8.0 Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by smtp1.osuosl.org (Postfix) with ESMTPS id 1F7F783E12 for ; Wed, 15 Jun 2022 10:28:24 +0000 (UTC) Received: by mail-qt1-x834.google.com with SMTP id f13so7816519qtb.5 for ; Wed, 15 Jun 2022 03:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=eTPtLP4NDpa8P0aI9dKapfMCGv9h90H8cChydbnDbXwDM3c9dFce+zWip7UvMIpzAj MwWt4NSMWMqrTbGPwJOf7l27KNudx15eMZzj6SyR4Zlj5OpOoagmM2K/3bI+5LT3Niyi h1vN0EW/aD3emP+jNz1Zcr7cozm+JkmhQecbNLlW+mU39R/LAtqcL2ahfL9sPHZJmXtA n+McjAPLlSceH+/folG8esKMX+j5OcZkgls4MZ7OITX1SzUtIIuFxa5K+LPw/fz8Cv5V vwmBMQsLsRdxHoNvxi45kD3Ty/9jaUWcXcCG6j3dwqXXCZ+czmFsSDp+cv482KfCuh2i qjyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=Oc5QPGe9qOZMCKqwmiDjM0FRKGmDA2kx3uTE2AzUA/BguMSAFV/lzHjkUaccheQ5VJ lDEHFNCuUFvbmH7+nJ7WubaojDJxwf78QvaUZflRPlmG1zsukWDfB6fuMoP/uDEKZinw d/wBLJ5JfRfXI1SXiajxWh3/+Wj6NN0XbfvZyTDRWTAdJEbvaqyu306oAkewVXRhCOVg sU4wE2vH5R7T1KrqRg+ffyIEq72r2vqJ6PdegmacB3iDuRZZJAq8Hn9dMXtD7wQj2rPC a9woLEEBsn+MiS6IqE6HwHX3iuhgPMKWBHknzvpVxQbgKcV6lNamPvvjnVcxsPBD0Tsg Twtw== X-Gm-Message-State: AOAM531vM7NfmsbBd9mXqswaPBlTqTSqPeHd8EL0fB6DUVeasDZiZvY1 410fO8b6cl7GB0VQh1B562ID/w+A7xyFHFJAUejwKw== X-Google-Smtp-Source: ABdhPJzgorGZ/k2s8/OSl6pg37NaKBcKW1yennvKVAegxKpGmun7X2J8lIgtj5Inxl+I5AXypY0S3fE/EQB34TCAN80= X-Received: by 2002:a05:622a:1351:b0:305:2e58:939 with SMTP id w17-20020a05622a135100b003052e580939mr7765424qtk.295.1655288902992; Wed, 15 Jun 2022 03:28:22 -0700 (PDT) MIME-Version: 1.0 References: <20220614230136.3726047-1-emma@anholt.net> <20220614230136.3726047-2-emma@anholt.net> In-Reply-To: <20220614230136.3726047-2-emma@anholt.net> From: Dmitry Baryshkov Date: Wed, 15 Jun 2022 13:28:12 +0300 Message-ID: Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables. To: Emma Anholt Cc: Will Deacon , iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , dri-devel@lists.freedesktop.org, Rob Herring , Andy Gross , linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Robin Murphy X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote: > > This is an SMMU for the adreno gpu, and adding this compatible lets > the driver use per-fd page tables, which are required for security > between GPU clients. > > Signed-off-by: Emma Anholt > --- > > Tested with a full deqp-vk run on RB5, which did involve some iommu faults. > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a92230bec1dd..483c0e0f1d1a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { > }; > > adreno_smmu: iommu@3da0000 { > - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; > + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu"; I see that other dtsi files use a bit different order for the compatibility strings. They put "qcom,adreno-smmu" before "arm,mmu-500". Can we please follow them? With that fixed: Reviewed-by: Dmitry Baryshkov > reg = <0 0x03da0000 0 0x10000>; > #iommu-cells = <2>; > #global-interrupts = <2>; > -- > 2.36.1 > -- With best wishes Dmitry _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16715C433EF for ; Wed, 15 Jun 2022 10:28:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAD7110F305; Wed, 15 Jun 2022 10:28:24 +0000 (UTC) Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0375D10E10E for ; Wed, 15 Jun 2022 10:28:23 +0000 (UTC) Received: by mail-qt1-x82e.google.com with SMTP id x16so7781215qtw.12 for ; Wed, 15 Jun 2022 03:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=eTPtLP4NDpa8P0aI9dKapfMCGv9h90H8cChydbnDbXwDM3c9dFce+zWip7UvMIpzAj MwWt4NSMWMqrTbGPwJOf7l27KNudx15eMZzj6SyR4Zlj5OpOoagmM2K/3bI+5LT3Niyi h1vN0EW/aD3emP+jNz1Zcr7cozm+JkmhQecbNLlW+mU39R/LAtqcL2ahfL9sPHZJmXtA n+McjAPLlSceH+/folG8esKMX+j5OcZkgls4MZ7OITX1SzUtIIuFxa5K+LPw/fz8Cv5V vwmBMQsLsRdxHoNvxi45kD3Ty/9jaUWcXcCG6j3dwqXXCZ+czmFsSDp+cv482KfCuh2i qjyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=gThHluHfVdynNorjmSh5Fkt3N7CtCCDhop4k/hzD/DWBD2zYmYsAOI98ii4CyVZO7d yGUtRUpYUQBa9Q/Uda6OF5vXZYFvwU9sQnLF6pXrwnhh0i5/nVa73aJD1xUhc2g3e6VH +gDP3auAgfWcrfgzpHH7ao0i4TqAmgfuf2G6lptkOTWVZYIedJj/iU12XHn7YGZw20qY 7PkxXoFPFrigLqhhWswOb8S7PTMeUZwJYx5rTRg5NbRCDLNIcw73RuZOaLeVdCb7ZK6Q CaxCWGhev0o6lkjYZ6mMAOZwfAMkV0/lVG3LnEqqPO7rYF61E2UprQCBXQEWPb+ZGY4F qBRg== X-Gm-Message-State: AOAM530MS4UKDeB9CD2S4CuZ0bljTYBCwZ6MPHs3cNmzDb9nZI3c9NHZ TnFYM0iLkb4x5JHnrDWXUcRBLu2VC8fw/116ssLGow== X-Google-Smtp-Source: ABdhPJzgorGZ/k2s8/OSl6pg37NaKBcKW1yennvKVAegxKpGmun7X2J8lIgtj5Inxl+I5AXypY0S3fE/EQB34TCAN80= X-Received: by 2002:a05:622a:1351:b0:305:2e58:939 with SMTP id w17-20020a05622a135100b003052e580939mr7765424qtk.295.1655288902992; Wed, 15 Jun 2022 03:28:22 -0700 (PDT) MIME-Version: 1.0 References: <20220614230136.3726047-1-emma@anholt.net> <20220614230136.3726047-2-emma@anholt.net> In-Reply-To: <20220614230136.3726047-2-emma@anholt.net> From: Dmitry Baryshkov Date: Wed, 15 Jun 2022 13:28:12 +0300 Message-ID: Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables. To: Emma Anholt Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Joerg Roedel , Jordan Crouse , dri-devel@lists.freedesktop.org, Bjorn Andersson , Rob Herring , Andy Gross , linux-arm-kernel@lists.infradead.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Robin Murphy Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote: > > This is an SMMU for the adreno gpu, and adding this compatible lets > the driver use per-fd page tables, which are required for security > between GPU clients. > > Signed-off-by: Emma Anholt > --- > > Tested with a full deqp-vk run on RB5, which did involve some iommu faults. > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a92230bec1dd..483c0e0f1d1a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { > }; > > adreno_smmu: iommu@3da0000 { > - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; > + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu"; I see that other dtsi files use a bit different order for the compatibility strings. They put "qcom,adreno-smmu" before "arm,mmu-500". Can we please follow them? With that fixed: Reviewed-by: Dmitry Baryshkov > reg = <0 0x03da0000 0 0x10000>; > #iommu-cells = <2>; > #global-interrupts = <2>; > -- > 2.36.1 > -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F33C2C43334 for ; Wed, 15 Jun 2022 10:29:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245276AbiFOK3Z (ORCPT ); Wed, 15 Jun 2022 06:29:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347557AbiFOK20 (ORCPT ); Wed, 15 Jun 2022 06:28:26 -0400 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17D9B13F52 for ; Wed, 15 Jun 2022 03:28:23 -0700 (PDT) Received: by mail-qt1-x832.google.com with SMTP id b3so2391169qtp.4 for ; Wed, 15 Jun 2022 03:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=eTPtLP4NDpa8P0aI9dKapfMCGv9h90H8cChydbnDbXwDM3c9dFce+zWip7UvMIpzAj MwWt4NSMWMqrTbGPwJOf7l27KNudx15eMZzj6SyR4Zlj5OpOoagmM2K/3bI+5LT3Niyi h1vN0EW/aD3emP+jNz1Zcr7cozm+JkmhQecbNLlW+mU39R/LAtqcL2ahfL9sPHZJmXtA n+McjAPLlSceH+/folG8esKMX+j5OcZkgls4MZ7OITX1SzUtIIuFxa5K+LPw/fz8Cv5V vwmBMQsLsRdxHoNvxi45kD3Ty/9jaUWcXcCG6j3dwqXXCZ+czmFsSDp+cv482KfCuh2i qjyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=Y+ovBkcLUjD+bXwzMiDSOXDtyibA7KKRoltzVmulA/j83P7yXjEbTHQGTdVjoiD/k+ fYOZTZD88Zb/Ngys83l3fKt5qJ4P0GDmE3VO9kqZJJECDPL1e3Er+GAF+5tPBACVvJTD U34qFRvFiMEhtQrWRd4opjossCyM5Hf/DuES7DXtcRopujQXIv7i0FiEHBkVhmxg51fh 4oTj7mlixfhmTFMhgIB7EvpNZuOaGkWy9y6LxxPa9nilCJiHRnLoldd1WTOjKH+dHeTV l6BOCVlBntfsU3Ib8EyoO7sdFx+pmcHBQ70919yH5s4UkpC7uWMbhdpfIyHpm9cbes3f 56jg== X-Gm-Message-State: AOAM532DnSNhhEmYdID3p730ppArOXk8kOUOvPVpmvi/P2dLBon+/k9z aoOdQfGrNWokVqZH1FTg9h5KMXQFBhUhy5tarX8ISQ== X-Google-Smtp-Source: ABdhPJzgorGZ/k2s8/OSl6pg37NaKBcKW1yennvKVAegxKpGmun7X2J8lIgtj5Inxl+I5AXypY0S3fE/EQB34TCAN80= X-Received: by 2002:a05:622a:1351:b0:305:2e58:939 with SMTP id w17-20020a05622a135100b003052e580939mr7765424qtk.295.1655288902992; Wed, 15 Jun 2022 03:28:22 -0700 (PDT) MIME-Version: 1.0 References: <20220614230136.3726047-1-emma@anholt.net> <20220614230136.3726047-2-emma@anholt.net> In-Reply-To: <20220614230136.3726047-2-emma@anholt.net> From: Dmitry Baryshkov Date: Wed, 15 Jun 2022 13:28:12 +0300 Message-ID: Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables. To: Emma Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Jordan Crouse , Andy Gross , Bjorn Andersson , Rob Herring , Will Deacon , Robin Murphy , Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote: > > This is an SMMU for the adreno gpu, and adding this compatible lets > the driver use per-fd page tables, which are required for security > between GPU clients. > > Signed-off-by: Emma Anholt > --- > > Tested with a full deqp-vk run on RB5, which did involve some iommu faults. > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a92230bec1dd..483c0e0f1d1a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { > }; > > adreno_smmu: iommu@3da0000 { > - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; > + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu"; I see that other dtsi files use a bit different order for the compatibility strings. They put "qcom,adreno-smmu" before "arm,mmu-500". Can we please follow them? With that fixed: Reviewed-by: Dmitry Baryshkov > reg = <0 0x03da0000 0 0x10000>; > #iommu-cells = <2>; > #global-interrupts = <2>; > -- > 2.36.1 > -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5406AC433EF for ; Wed, 15 Jun 2022 10:33:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d1uGwxjVlKGCRu+4rbrVi3xvi7PO2CGRxWFyuffruOs=; b=rmjyBl7DmYS4HC rPGBFQF6WiEAfKpNaxeaVFuTFeC5Q4U4iWgi0Ct1axsniZudOIotNmiVpv5LrST06xJZPa2nNG957 0RyOEzjwvAagX/wMLqIIgfMMJLROarfvqDGTHQXNemZW/WRCS8YLVuchbbUTs8WEB2XrvQSLO1YCC jOkmyDMDpYqa/rJ8vVLOVyT7uJ+4SOrfAj+Y3fAcdBL3nyIZBMvTXF4I2pVxjcO0awEKPtiKxKjI6 9Pu3/GXhV5LQH0qYS8jHKc13E/k+8qpYfEJ4taftXJuGwD5kFgZPK3juB73UtG5FDB2n6i+ZouDFS +5THNOdr1cxHKOB1o1Kg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1QJG-00DqwL-7k; Wed, 15 Jun 2022 10:31:38 +0000 Received: from mail-qt1-x831.google.com ([2607:f8b0:4864:20::831]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o1QGA-00Dply-V9 for linux-arm-kernel@lists.infradead.org; Wed, 15 Jun 2022 10:28:28 +0000 Received: by mail-qt1-x831.google.com with SMTP id q6so118222qtn.7 for ; Wed, 15 Jun 2022 03:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=eTPtLP4NDpa8P0aI9dKapfMCGv9h90H8cChydbnDbXwDM3c9dFce+zWip7UvMIpzAj MwWt4NSMWMqrTbGPwJOf7l27KNudx15eMZzj6SyR4Zlj5OpOoagmM2K/3bI+5LT3Niyi h1vN0EW/aD3emP+jNz1Zcr7cozm+JkmhQecbNLlW+mU39R/LAtqcL2ahfL9sPHZJmXtA n+McjAPLlSceH+/folG8esKMX+j5OcZkgls4MZ7OITX1SzUtIIuFxa5K+LPw/fz8Cv5V vwmBMQsLsRdxHoNvxi45kD3Ty/9jaUWcXcCG6j3dwqXXCZ+czmFsSDp+cv482KfCuh2i qjyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VRRIXOfBq1yQuH5EfBFqRJA+XF3LzpkQlfmJRxNlHxM=; b=aIOjevdW5Z2+d05/+kJIOY1jbh70xy6qAJgiBc2lihFlhyKaQngCNqWOix9pC9E2+5 jCTJgCroS/vdO3oI+TMrMz91M5POkTq0YlV7RmaFCoT9ToUbqynflkph+1n7eeSEkGua mQyFKXVbkvMvnnnByngyN+1qw8rHSQG6MD2TEJnEFuS0gVUid+aGPJqnRW2v54O1gPvI lDhWxyChdxMslUqm7m7tVpL03zRZbtUmDNacYvt0oabGuS8ho1SFaA3RwnXJBFhDbakG Wy7LGm9CtPs2aDwOheOaiP/6aLWN/FTPf/getRYrthFRlbCE+lA8Ujas2Ij7wtLichxd EFsw== X-Gm-Message-State: AOAM53002kqeiEbI4wS67co2QocGOHq3kRMPr8wdcwYyPHVhSIrY9SmN mIMMEo3qT5d321nIor01zx6hqCPzJI3qN7m4Uf77qg== X-Google-Smtp-Source: ABdhPJzgorGZ/k2s8/OSl6pg37NaKBcKW1yennvKVAegxKpGmun7X2J8lIgtj5Inxl+I5AXypY0S3fE/EQB34TCAN80= X-Received: by 2002:a05:622a:1351:b0:305:2e58:939 with SMTP id w17-20020a05622a135100b003052e580939mr7765424qtk.295.1655288902992; Wed, 15 Jun 2022 03:28:22 -0700 (PDT) MIME-Version: 1.0 References: <20220614230136.3726047-1-emma@anholt.net> <20220614230136.3726047-2-emma@anholt.net> In-Reply-To: <20220614230136.3726047-2-emma@anholt.net> From: Dmitry Baryshkov Date: Wed, 15 Jun 2022 13:28:12 +0300 Message-ID: Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables. To: Emma Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Jordan Crouse , Andy Gross , Bjorn Andersson , Rob Herring , Will Deacon , Robin Murphy , Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220615_032827_165776_73C840D3 X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 15 Jun 2022 at 02:01, Emma Anholt wrote: > > This is an SMMU for the adreno gpu, and adding this compatible lets > the driver use per-fd page tables, which are required for security > between GPU clients. > > Signed-off-by: Emma Anholt > --- > > Tested with a full deqp-vk run on RB5, which did involve some iommu faults. > > arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a92230bec1dd..483c0e0f1d1a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d90000 { > }; > > adreno_smmu: iommu@3da0000 { > - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; > + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", "qcom,adreno-smmu"; I see that other dtsi files use a bit different order for the compatibility strings. They put "qcom,adreno-smmu" before "arm,mmu-500". Can we please follow them? With that fixed: Reviewed-by: Dmitry Baryshkov > reg = <0 0x03da0000 0 0x10000>; > #iommu-cells = <2>; > #global-interrupts = <2>; > -- > 2.36.1 > -- With best wishes Dmitry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel