From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A20C433EF for ; Fri, 3 Jun 2022 07:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234832AbiFCHDG (ORCPT ); Fri, 3 Jun 2022 03:03:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242176AbiFCHCw (ORCPT ); Fri, 3 Jun 2022 03:02:52 -0400 Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D88451C93F for ; Fri, 3 Jun 2022 00:02:37 -0700 (PDT) Received: by mail-qt1-x836.google.com with SMTP id x7so4981050qta.6 for ; Fri, 03 Jun 2022 00:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bpTxhe8d1wfl9cxmRQmaPd/25jnJpClicp4FOUimKUo=; b=d50+tzVxqEhaFcPBBGejf2UJbunWjF5Abb00attFnWFaI9oPYW5zWBgJKvXsSpCdKr yDamXzaOpr3WL1MkwYlxNubMOr7It+wygCcPJeO0zaOIocMJq8WI7DEQfvTptzNRHoFW pLzInGxQ0yH3fV+FooefbDug8iJCNNLTKatYYsaXIiZuI5JVBgm5hwu/6hQ7dxvvfSNH 0YSiAJS2kGeiHX8h/By+khNvN1NPsLUq3T+cTimx76r60JxFPn9PqTXBVF0c7HoDSP9D oM3nu4PnB+G98qyYwP6fz6PwwbpipeF4YuGDkCvSwf1sql+zht7Nk692c1ytM1bnUkNE goQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bpTxhe8d1wfl9cxmRQmaPd/25jnJpClicp4FOUimKUo=; b=qp7rrhurWlUWculjqrst1Wdq2hAMeWyIcvJuyxxzakd0OvH+9SIRNpfiAEApDl7oBp rHsqzHXkW4EVZLBSTunLSAXGAwK/qcQ+HMhWt2Bk99GvdJrnrbwD7zWvvxj9Vkue2ug6 ccrUk2+fmA/Sx3D0PKw2uPCgjLlLdkp0z8DAkLVEKJvYa6bj20tmfbOqmgqVc3idZ+yQ ARcHGU3SpveReQLMiBGhgM+BbHibaDSD48+BKXIS8XUkDBtpfWOdaJZZEE5LDgivnxD2 O+TAlif/WqehK+lNOEhBwKhlfxde5WPT37jzJ1QoxcRaUfqH1d/B12ggiBJ6f7UaEziT uydw== X-Gm-Message-State: AOAM532p4cXpyzd+aWv06eq4CfpWUJghHLGWnsHvEdTSppjQSwu7a3TW MqPD8Fd4A1der25GyM2tOecWs9qANNkJufZati9q9w== X-Google-Smtp-Source: ABdhPJx1Tn+p+ALdFrzKUULQPAzAC+KVROpMIwSkRoSORmiBsKP2vXzREITjvn4vZsl/fX/dydtl1JPNPXChp239G80= X-Received: by 2002:ac8:5990:0:b0:304:c8d6:3147 with SMTP id e16-20020ac85990000000b00304c8d63147mr6502086qte.370.1654239756957; Fri, 03 Jun 2022 00:02:36 -0700 (PDT) MIME-Version: 1.0 References: <20220527185407.162-1-quic_jesszhan@quicinc.com> <20220527185407.162-4-quic_jesszhan@quicinc.com> <266fdac1-db57-a729-3d73-42d2b34017cd@linaro.org> In-Reply-To: From: Dmitry Baryshkov Date: Fri, 3 Jun 2022 10:02:26 +0300 Message-ID: Subject: Re: [Freedreno] [PATCH 3/3] drm/msm/dpu: Add interface support for CRC debugfs To: Jessica Zhang Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, dri-devel@lists.freedesktop.org, swboyd@chromium.org, robdclark@gmail.com, seanpaul@chromium.org, quic_aravindh@quicinc.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, 3 Jun 2022 at 04:02, Jessica Zhang wrote: > On 6/2/2022 3:51 PM, Dmitry Baryshkov wrote: > > On 28/05/2022 01:23, Jessica Zhang wrote: > >> On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote: > >>> On 27/05/2022 21:54, Jessica Zhang wrote: > >>>> Add support for writing CRC values for the interface block to > >>>> the debugfs by calling the necessary MISR setup/collect methods. > >>>> > >>>> Signed-off-by: Jessica Zhang [skipped] > >>>> + > >>>> + phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); > >>>> + } > >>>> +} > >>>> + > >>>> +int dpu_encoder_get_crc(const struct drm_encoder *drm_enc) > >>>> +{ > >>>> + struct dpu_encoder_virt *dpu_enc; > >>>> + u32 crcs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; > >>>> + > >>>> + int i, rc; > >>>> + > >>>> + if (!drm_enc->crtc) { > >>>> + DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); > >>>> + return -EINVAL; > >>>> + } > >>>> + > >>>> + dpu_enc = to_dpu_encoder_virt(drm_enc); > >>>> + > >>>> + for (i = 0; i < dpu_enc->num_phys_encs; i++) { > >>>> + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; > >>>> + > >>>> + if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) > >>>> + continue; > >>>> + > >>>> + rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[i]); > >>> > >>> This doesn't look fully correct. Do we need to skip the indices for > >>> the phys without a backing hw_intf? > >> > >> Sorry if I'm misunderstanding your question, but don't we need to have > >> a backing hw_intf (and skip if there isn't any) since the methods for > >> collecting/setting MISR registers is within the hw_intf? > > > > Yes. So the question if we should skip the phys and leave the crcs[i] > > untouched, skip the phys and sset crcs[i] to 0 or change > > dpu_crtc_parse_crc_source() to return the number of intf-backed > > phys_enc's and do not skip any crcs[i]. > > Thanks for the clarification. > > Is it possible to hit a case where a phys_encoder won't have a > corresponding hw_intf? > > AFAIK, it seems guaranteed that a phys_encoder will have an hw_intf > since dpu_encoder_setup_display will skip incrementing num_phys_encs if > dpu_encoder_get_intf fails [1]. WB encoders won't have hw_intf. The code checks that either get_intf or get_wb succeeds. > > [1] > https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L2263 -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF111C433EF for ; Fri, 3 Jun 2022 07:02:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A452B113D7E; Fri, 3 Jun 2022 07:02:38 +0000 (UTC) Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by gabe.freedesktop.org (Postfix) with ESMTPS id E8346113D7F for ; Fri, 3 Jun 2022 07:02:37 +0000 (UTC) Received: by mail-qt1-x82a.google.com with SMTP id 2so5009865qtw.0 for ; Fri, 03 Jun 2022 00:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bpTxhe8d1wfl9cxmRQmaPd/25jnJpClicp4FOUimKUo=; b=d50+tzVxqEhaFcPBBGejf2UJbunWjF5Abb00attFnWFaI9oPYW5zWBgJKvXsSpCdKr yDamXzaOpr3WL1MkwYlxNubMOr7It+wygCcPJeO0zaOIocMJq8WI7DEQfvTptzNRHoFW pLzInGxQ0yH3fV+FooefbDug8iJCNNLTKatYYsaXIiZuI5JVBgm5hwu/6hQ7dxvvfSNH 0YSiAJS2kGeiHX8h/By+khNvN1NPsLUq3T+cTimx76r60JxFPn9PqTXBVF0c7HoDSP9D oM3nu4PnB+G98qyYwP6fz6PwwbpipeF4YuGDkCvSwf1sql+zht7Nk692c1ytM1bnUkNE goQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bpTxhe8d1wfl9cxmRQmaPd/25jnJpClicp4FOUimKUo=; b=CcAvgo3xkIGNAJYI0MyjvYJxa1YhmT7B6dqXnGaMuLcGdpC+LeljudnliGyWX4TP8Q NsZrOzGijV32w0SNfUXZEOgZIKUDVHzqdRoyDi+9lQsg3dgidDdHmgLxzzJX/fqUnKei yaOvQbH+R9UM9ecF2CEKXhGhfINam7DUo96wLIzKX15cH1X099kj+nFSDHXHDx+X9bf1 uI4eIxNWQ0cLqCXbnXxk7MxgCAKyEXPnkRGtwkJG0mb2WzeEr19GmPZ/FbjOsVU3FNez pkxHUt1hqr9xx7Ig6gjHiCav6dDBbJ9d9dg+RUF3hg3bl2t5o1sRoz1Q8m3tLrm0m8N0 tphQ== X-Gm-Message-State: AOAM533IJxit4k63hFm7p9jvQlWjzOp6lOuJKjFEMDKWMf5DJ50cygQ1 qFonG4PN20RL5oElo0x9wm046xHeaIx91xh0qD3SAw== X-Google-Smtp-Source: ABdhPJx1Tn+p+ALdFrzKUULQPAzAC+KVROpMIwSkRoSORmiBsKP2vXzREITjvn4vZsl/fX/dydtl1JPNPXChp239G80= X-Received: by 2002:ac8:5990:0:b0:304:c8d6:3147 with SMTP id e16-20020ac85990000000b00304c8d63147mr6502086qte.370.1654239756957; Fri, 03 Jun 2022 00:02:36 -0700 (PDT) MIME-Version: 1.0 References: <20220527185407.162-1-quic_jesszhan@quicinc.com> <20220527185407.162-4-quic_jesszhan@quicinc.com> <266fdac1-db57-a729-3d73-42d2b34017cd@linaro.org> In-Reply-To: From: Dmitry Baryshkov Date: Fri, 3 Jun 2022 10:02:26 +0300 Message-ID: Subject: Re: [Freedreno] [PATCH 3/3] drm/msm/dpu: Add interface support for CRC debugfs To: Jessica Zhang Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, quic_abhinavk@quicinc.com, dri-devel@lists.freedesktop.org, swboyd@chromium.org, seanpaul@chromium.org, quic_aravindh@quicinc.com, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, 3 Jun 2022 at 04:02, Jessica Zhang wrote: > On 6/2/2022 3:51 PM, Dmitry Baryshkov wrote: > > On 28/05/2022 01:23, Jessica Zhang wrote: > >> On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote: > >>> On 27/05/2022 21:54, Jessica Zhang wrote: > >>>> Add support for writing CRC values for the interface block to > >>>> the debugfs by calling the necessary MISR setup/collect methods. > >>>> > >>>> Signed-off-by: Jessica Zhang [skipped] > >>>> + > >>>> + phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); > >>>> + } > >>>> +} > >>>> + > >>>> +int dpu_encoder_get_crc(const struct drm_encoder *drm_enc) > >>>> +{ > >>>> + struct dpu_encoder_virt *dpu_enc; > >>>> + u32 crcs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; > >>>> + > >>>> + int i, rc; > >>>> + > >>>> + if (!drm_enc->crtc) { > >>>> + DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); > >>>> + return -EINVAL; > >>>> + } > >>>> + > >>>> + dpu_enc = to_dpu_encoder_virt(drm_enc); > >>>> + > >>>> + for (i = 0; i < dpu_enc->num_phys_encs; i++) { > >>>> + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; > >>>> + > >>>> + if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) > >>>> + continue; > >>>> + > >>>> + rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[i]); > >>> > >>> This doesn't look fully correct. Do we need to skip the indices for > >>> the phys without a backing hw_intf? > >> > >> Sorry if I'm misunderstanding your question, but don't we need to have > >> a backing hw_intf (and skip if there isn't any) since the methods for > >> collecting/setting MISR registers is within the hw_intf? > > > > Yes. So the question if we should skip the phys and leave the crcs[i] > > untouched, skip the phys and sset crcs[i] to 0 or change > > dpu_crtc_parse_crc_source() to return the number of intf-backed > > phys_enc's and do not skip any crcs[i]. > > Thanks for the clarification. > > Is it possible to hit a case where a phys_encoder won't have a > corresponding hw_intf? > > AFAIK, it seems guaranteed that a phys_encoder will have an hw_intf > since dpu_encoder_setup_display will skip incrementing num_phys_encs if > dpu_encoder_get_intf fails [1]. WB encoders won't have hw_intf. The code checks that either get_intf or get_wb succeeds. > > [1] > https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L2263 -- With best wishes Dmitry