From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA1AC433DB for ; Tue, 9 Mar 2021 15:15:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15AF06527B for ; Tue, 9 Mar 2021 15:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231842AbhCIPPH (ORCPT ); Tue, 9 Mar 2021 10:15:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231825AbhCIPO5 (ORCPT ); Tue, 9 Mar 2021 10:14:57 -0500 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1847AC06174A for ; Tue, 9 Mar 2021 07:14:57 -0800 (PST) Received: by mail-qk1-x733.google.com with SMTP id l4so13340025qkl.0 for ; Tue, 09 Mar 2021 07:14:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7MrPV8J5TBwRP2XTDenNEVDLqEA1C2gDo3lt+AylHJg=; b=kzpPHQlBIF4+6LV5REOgk4hd860I5fwmqU2hco2bMJsl2jvOVyhLCi3cxyUg+gYSnI S/3f0zavZsXfo583h+EDFc5NEFVxC/Bo6PIR/GQqOI9hawIfiNAeh9I53XsHUkUnPhtH ccqY6z9XUAB4/cGr2/ut5puxovjwn+g7GjjtqIulLitEP6myj0ItoWZEd1yrGczd4nWm /FJsGw3wXtNGtq75Xl2otJgxhFs3twc1MfwsBYHmBOru8ykOTRJxtPTdaNvx1Htaw3Yr fTTWMpyUv8LdTN641FtKq8sjmNGXYWiAREFq0QVHWlSZvbgj8uNNZMVJOw3z+am6bxiH xIew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7MrPV8J5TBwRP2XTDenNEVDLqEA1C2gDo3lt+AylHJg=; b=WXZeHHQ71lWXnW4EBv+iZUq6EKfXt/oMuXW9iIbdn2jv8+nD+3fcp7aFUIkYPN4Wnh fvRxLrHsPxBArXx/wM00oE/DG40VyFdabAj33cNpiqV0KjXzBEnCk3kLlN9esDJRAmEj I3W6+kyIDa5+T2u4sMT2lP+Bsaw6Vo0U6Ak+wiBP2mjA5AVjHu6dPnX40RZod0FU7t96 JDu7vOyySsP1DFFkgycs5IZgSrPxm3y6T8L5QdNKPBxfoi+YKhisuttC5mGWqiM01ULx vGDms8ayLFHlp3LO0S2TGSpqNQ3u9BzhlplzfaSu9SuVX/MAIh8csfgOMYeQluv5aBQm a3Hg== X-Gm-Message-State: AOAM530dokbBvQN5xnn3jD/UNg06VJl3kAwih5xXGudSo0KigIFLHG+1 o6BhpnnjnVMSPVKGH2rOOw/MAc9xbUMvdWvOqiXRhQ== X-Google-Smtp-Source: ABdhPJzVlEwNEHQWahsLhzstfMLZXkIj/+jRZQzIdcrvUeWVyWtSBn6T9++RBPWw8oTT696f0ki1+UBA3Fas0/UT2Jc= X-Received: by 2002:a37:8cd:: with SMTP id 196mr24729622qki.434.1615302896316; Tue, 09 Mar 2021 07:14:56 -0800 (PST) MIME-Version: 1.0 References: <20210224224751.1215018-1-dmitry.baryshkov@linaro.org> In-Reply-To: <20210224224751.1215018-1-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov Date: Tue, 9 Mar 2021 18:14:45 +0300 Message-ID: Subject: Re: [PATCH] drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code To: Rob Clark , Sean Paul Cc: "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno , Jonathan Marek Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rob, Any feedback on this? The patches were sent about two weeks ago. On Thu, 25 Feb 2021 at 01:47, Dmitry Baryshkov wrote: > > Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on > sm8250). Current code checks for pll->type before it is set (as it is > set in the msm_dsi_pll_init() after calling device-specific functions. > > Cc: Jonathan Marek > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 2 +- > drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 6 ++++-- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 5 +++-- > 3 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > index a45fe95aff49..3dc65877fa10 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > @@ -163,7 +163,7 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, > break; > case MSM_DSI_PHY_7NM: > case MSM_DSI_PHY_7NM_V4_1: > - pll = msm_dsi_pll_7nm_init(pdev, id); > + pll = msm_dsi_pll_7nm_init(pdev, type, id); > break; > default: > pll = ERR_PTR(-ENXIO); > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > index 3405982a092c..bbecb1de5678 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > @@ -117,10 +117,12 @@ msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) > } > #endif > #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id); > +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id); > #else > static inline struct msm_dsi_pll * > -msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > +msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id) > { > return ERR_PTR(-ENODEV); > } > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > index 93bf142e4a4e..c1f6708367ae 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > @@ -852,7 +852,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) > return ret; > } > > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id) > { > struct dsi_pll_7nm *pll_7nm; > struct msm_dsi_pll *pll; > @@ -885,7 +886,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > pll = &pll_7nm->base; > pll->min_rate = 1000000000UL; > pll->max_rate = 3500000000UL; > - if (pll->type == MSM_DSI_PHY_7NM_V4_1) { > + if (type == MSM_DSI_PHY_7NM_V4_1) { > pll->min_rate = 600000000UL; > pll->max_rate = (unsigned long)5000000000ULL; > /* workaround for max rate overflowing on 32-bit builds: */ > -- > 2.30.0 > -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96156C433DB for ; Tue, 9 Mar 2021 15:14:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E6C4651AE for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Rob, Any feedback on this? The patches were sent about two weeks ago. On Thu, 25 Feb 2021 at 01:47, Dmitry Baryshkov wrote: > > Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on > sm8250). Current code checks for pll->type before it is set (as it is > set in the msm_dsi_pll_init() after calling device-specific functions. > > Cc: Jonathan Marek > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 2 +- > drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 6 ++++-- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 5 +++-- > 3 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > index a45fe95aff49..3dc65877fa10 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c > @@ -163,7 +163,7 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, > break; > case MSM_DSI_PHY_7NM: > case MSM_DSI_PHY_7NM_V4_1: > - pll = msm_dsi_pll_7nm_init(pdev, id); > + pll = msm_dsi_pll_7nm_init(pdev, type, id); > break; > default: > pll = ERR_PTR(-ENXIO); > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > index 3405982a092c..bbecb1de5678 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h > @@ -117,10 +117,12 @@ msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) > } > #endif > #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id); > +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id); > #else > static inline struct msm_dsi_pll * > -msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > +msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id) > { > return ERR_PTR(-ENODEV); > } > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > index 93bf142e4a4e..c1f6708367ae 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c > @@ -852,7 +852,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm) > return ret; > } > > -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, > + enum msm_dsi_phy_type type, int id) > { > struct dsi_pll_7nm *pll_7nm; > struct msm_dsi_pll *pll; > @@ -885,7 +886,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) > pll = &pll_7nm->base; > pll->min_rate = 1000000000UL; > pll->max_rate = 3500000000UL; > - if (pll->type == MSM_DSI_PHY_7NM_V4_1) { > + if (type == MSM_DSI_PHY_7NM_V4_1) { > pll->min_rate = 600000000UL; > pll->max_rate = (unsigned long)5000000000ULL; > /* workaround for max rate overflowing on 32-bit builds: */ > -- > 2.30.0 > -- With best wishes Dmitry _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel