From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 3/3] clk: qcom: lcc-ipq806x: convert to parent data
Date: Tue, 21 Jun 2022 20:15:57 +0300 [thread overview]
Message-ID: <CAA8EJpqQTTevQa4pQg3E+x4_AOjYo8ajOqUrfwGsVtC8N=bpOw@mail.gmail.com> (raw)
In-Reply-To: <20220621163326.16858-3-ansuelsmth@gmail.com>
On Tue, 21 Jun 2022 at 19:33, Christian Marangi <ansuelsmth@gmail.com> wrote:
>
> Convert lcc-ipq806x driver to parent_data API.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> v2:
> - Fix Sob tag
>
> drivers/clk/qcom/lcc-ipq806x.c | 79 +++++++++++++++++++---------------
> 1 file changed, 44 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
> index ba90bebba597..c07ca8dc6e3a 100644
> --- a/drivers/clk/qcom/lcc-ipq806x.c
> +++ b/drivers/clk/qcom/lcc-ipq806x.c
> @@ -24,6 +24,10 @@
> #include "clk-regmap-mux.h"
> #include "reset.h"
>
> +static const struct clk_parent_data gcc_pxo[] = {
> + { .fw_name = "pxo", .name = "pxo" },
I think you'd use .name = "pxo_board" here. You don't need to use the
interim clock.
> +};
> +
> static struct clk_pll pll4 = {
> .l_reg = 0x4,
> .m_reg = 0x8,
> @@ -34,7 +38,7 @@ static struct clk_pll pll4 = {
> .status_bit = 16,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pll4",
> - .parent_names = (const char *[]){ "pxo" },
> + .parent_data = gcc_pxo,
> .num_parents = 1,
Could you please either inline the gcc_pxo here (yes, it's ugly, but
it works for small arrays) or use ARRAY_SIZE here.
> .ops = &clk_pll_ops,
> },
> @@ -64,9 +68,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = {
> { P_PLL4, 2 }
> };
>
> -static const char * const lcc_pxo_pll4[] = {
> - "pxo",
> - "pll4_vote",
> +static const struct clk_parent_data lcc_pxo_pll4[] = {
> + { .fw_name = "pxo", .name = "pxo" },
> + { .fw_name = "pll4_vote", .name = "pll4_vote" },
> };
>
> static struct freq_tbl clk_tbl_aif_mi2s[] = {
> @@ -131,18 +135,14 @@ static struct clk_rcg mi2s_osr_src = {
> .enable_mask = BIT(9),
> .hw.init = &(struct clk_init_data){
> .name = "mi2s_osr_src",
> - .parent_names = lcc_pxo_pll4,
> - .num_parents = 2,
> + .parent_data = lcc_pxo_pll4,
> + .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> },
> };
>
> -static const char * const lcc_mi2s_parents[] = {
> - "mi2s_osr_src",
> -};
> -
> static struct clk_branch mi2s_osr_clk = {
> .halt_reg = 0x50,
> .halt_bit = 1,
> @@ -152,7 +152,9 @@ static struct clk_branch mi2s_osr_clk = {
> .enable_mask = BIT(17),
> .hw.init = &(struct clk_init_data){
> .name = "mi2s_osr_clk",
> - .parent_names = lcc_mi2s_parents,
> + .parent_hws = (const struct clk_hw*[]){
> + &mi2s_osr_src.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_branch_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -167,7 +169,9 @@ static struct clk_regmap_div mi2s_div_clk = {
> .clkr = {
> .hw.init = &(struct clk_init_data){
> .name = "mi2s_div_clk",
> - .parent_names = lcc_mi2s_parents,
> + .parent_hws = (const struct clk_hw*[]){
> + &mi2s_osr_src.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_regmap_div_ops,
> },
> @@ -183,7 +187,9 @@ static struct clk_branch mi2s_bit_div_clk = {
> .enable_mask = BIT(15),
> .hw.init = &(struct clk_init_data){
> .name = "mi2s_bit_div_clk",
> - .parent_names = (const char *[]){ "mi2s_div_clk" },
> + .parent_hws = (const struct clk_hw*[]){
> + &mi2s_div_clk.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_branch_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -191,6 +197,10 @@ static struct clk_branch mi2s_bit_div_clk = {
> },
> };
>
> +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
> + { .hw = &mi2s_bit_div_clk.clkr.hw, },
> + { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" },
> +};
>
> static struct clk_regmap_mux mi2s_bit_clk = {
> .reg = 0x48,
> @@ -199,11 +209,8 @@ static struct clk_regmap_mux mi2s_bit_clk = {
> .clkr = {
> .hw.init = &(struct clk_init_data){
> .name = "mi2s_bit_clk",
> - .parent_names = (const char *[]){
> - "mi2s_bit_div_clk",
> - "mi2s_codec_clk",
> - },
> - .num_parents = 2,
> + .parent_data = lcc_mi2s_bit_div_codec_clk,
> + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
> .ops = &clk_regmap_mux_closest_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -245,8 +252,8 @@ static struct clk_rcg pcm_src = {
> .enable_mask = BIT(9),
> .hw.init = &(struct clk_init_data){
> .name = "pcm_src",
> - .parent_names = lcc_pxo_pll4,
> - .num_parents = 2,
> + .parent_data = lcc_pxo_pll4,
> + .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> @@ -262,7 +269,9 @@ static struct clk_branch pcm_clk_out = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "pcm_clk_out",
> - .parent_names = (const char *[]){ "pcm_src" },
> + .parent_hws = (const struct clk_hw*[]){
> + &pcm_src.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_branch_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -270,6 +279,11 @@ static struct clk_branch pcm_clk_out = {
> },
> };
>
> +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
> + { .hw = &pcm_clk_out.clkr.hw, },
> + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
> +};
> +
> static struct clk_regmap_mux pcm_clk = {
> .reg = 0x54,
> .shift = 10,
> @@ -277,11 +291,8 @@ static struct clk_regmap_mux pcm_clk = {
> .clkr = {
> .hw.init = &(struct clk_init_data){
> .name = "pcm_clk",
> - .parent_names = (const char *[]){
> - "pcm_clk_out",
> - "pcm_codec_clk",
> - },
> - .num_parents = 2,
> + .parent_data = lcc_pcm_clk_out_codec_clk,
> + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
> .ops = &clk_regmap_mux_closest_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -325,18 +336,14 @@ static struct clk_rcg spdif_src = {
> .enable_mask = BIT(9),
> .hw.init = &(struct clk_init_data){
> .name = "spdif_src",
> - .parent_names = lcc_pxo_pll4,
> - .num_parents = 2,
> + .parent_data = lcc_pxo_pll4,
> + .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
> .ops = &clk_rcg_ops,
> .flags = CLK_SET_RATE_GATE,
> },
> },
> };
>
> -static const char * const lcc_spdif_parents[] = {
> - "spdif_src",
> -};
> -
> static struct clk_branch spdif_clk = {
> .halt_reg = 0xd4,
> .halt_bit = 1,
> @@ -346,7 +353,9 @@ static struct clk_branch spdif_clk = {
> .enable_mask = BIT(12),
> .hw.init = &(struct clk_init_data){
> .name = "spdif_clk",
> - .parent_names = lcc_spdif_parents,
> + .parent_hws = (const struct clk_hw*[]){
> + &spdif_src.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_branch_ops,
> .flags = CLK_SET_RATE_PARENT,
> @@ -384,8 +393,8 @@ static struct clk_rcg ahbix_clk = {
> .enable_mask = BIT(11),
> .hw.init = &(struct clk_init_data){
> .name = "ahbix",
> - .parent_names = lcc_pxo_pll4,
> - .num_parents = 2,
> + .parent_data = lcc_pxo_pll4,
> + .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
> .ops = &clk_rcg_lcc_ops,
> },
> },
> --
> 2.36.1
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2022-06-21 17:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-21 16:33 [PATCH v2 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc Christian Marangi
2022-06-21 16:33 ` [PATCH v2 2/3] clk: qcom: lcc-ipq806x: add reset definition Christian Marangi
2022-06-21 17:16 ` Dmitry Baryshkov
2022-06-21 16:33 ` [PATCH v2 3/3] clk: qcom: lcc-ipq806x: convert to parent data Christian Marangi
2022-06-21 17:15 ` Dmitry Baryshkov [this message]
2022-06-21 20:23 ` Christian Marangi
2022-06-21 20:43 ` Dmitry Baryshkov
2022-07-05 20:21 ` Christian Marangi
2022-07-06 7:34 ` Dmitry Baryshkov
2022-07-06 10:07 ` Christian Marangi
2022-06-21 17:16 ` [PATCH v2 1/3] dt-bindings: clock: add pcm reset for ipq806x lcc Dmitry Baryshkov
2022-06-28 19:43 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAA8EJpqQTTevQa4pQg3E+x4_AOjYo8ajOqUrfwGsVtC8N=bpOw@mail.gmail.com' \
--to=dmitry.baryshkov@linaro.org \
--cc=agross@kernel.org \
--cc=ansuelsmth@gmail.com \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.