From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9376C433F5 for ; Tue, 5 Apr 2022 13:57:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3724410E92B; Tue, 5 Apr 2022 13:57:16 +0000 (UTC) Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by gabe.freedesktop.org (Postfix) with ESMTPS id C161810E92B for ; Tue, 5 Apr 2022 13:57:14 +0000 (UTC) Received: by mail-qt1-x833.google.com with SMTP id b18so11053642qtk.13 for ; Tue, 05 Apr 2022 06:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ooVTJG6qHCp0yXAPzRm26+nzLP9pRyshNnyYCdC2/cI=; b=IjO1lAYG9dMjEoFuBKubL4solYQl93gBLvk38hPySmUXvALA+uoqB5JW6jq462kv3w XAv4VTxdhTe/Ar+F3ht8PctXXH1Z/CEFWL8rIGHVVnKhc8NrYKoeNDSb+gwniYzUwdqy cPCbAw7DBwC9H/iGurSWWopq5BX213OioWQjNpms7RtaNWffKommNV11P0techfv+VWq jmsl/Xrr/T99SAhsTZABhIAE2rf0H6z4BIeaC/xRBzZudWiZxfRd5sdUll3mUyKzmwBM mhubX3e2dDLaS2a/nEk3lBLHP4BdREc3DkUve465WChVkkGjPKvW4m2oQ5IIZOJ7aAL6 m6WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ooVTJG6qHCp0yXAPzRm26+nzLP9pRyshNnyYCdC2/cI=; b=thngvv9JPN47d+8hesfG0wDySp4vwHrA9MG90bVuqhxBQ+PEEylH+gC++Mly3Getba ASOBO/tQhRQ64Alhvc6HzeDonV7OW4Ieuhw8oszg6v3HZkjAJgut3Dm0p4R5nLWqQxlr mNqigkO+/WmG5RWErJqCOQt5WSWB6c2Uj8SvH7aXfqHOXVklxJ+qt/9fImpkgLhiJM8E C9xrPWgZnKmDP/N3f14JY94zFGYkRXHL4+m+x+fampTJ3MSPCy63RMluNXlAMT7HLDbz 2m616gWTqaVWT8szHD8ZZfz0xBmGHyrIyeSMaEG+gBdT+isUcJnMBQsF95CgQbeKksf9 OVWA== X-Gm-Message-State: AOAM532j/ZG+2+xXDrxkfKJpWBDajVStvP+qETmdIfpU96Z1y+2iNSzA mjdUZBgDkcbMz0p/6RHow2lA1Hl9jlVQN6zus7zRew== X-Google-Smtp-Source: ABdhPJyvUqZgngY2xTxFZn28xhxZyEZiZ6UDJJnFxcDrOQUW4IEe+56aagmVfjuPhPAcWrPVD5R+J8V5qHnj4OpopWI= X-Received: by 2002:ac8:4e52:0:b0:2e1:dad8:5141 with SMTP id e18-20020ac84e52000000b002e1dad85141mr3050575qtw.62.1649167033885; Tue, 05 Apr 2022 06:57:13 -0700 (PDT) MIME-Version: 1.0 References: <20220404163436.956875-1-vkoul@kernel.org> <20220404163436.956875-14-vkoul@kernel.org> In-Reply-To: <20220404163436.956875-14-vkoul@kernel.org> From: Dmitry Baryshkov Date: Tue, 5 Apr 2022 16:57:02 +0300 Message-ID: Subject: Re: [PATCH v6 13/14] drm/msm: Update generated headers To: Vinod Koul Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , David Airlie , linux-arm-msm@vger.kernel.org, Abhinav Kumar , dri-devel@lists.freedesktop.org, Bjorn Andersson , freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote: > > Update headers from mesa commit: > > commit 28ae397be111c37c6ced397e12d453a7695701bd > Author: Vinod Koul > Date: Fri Apr 1 16:53:04 2022 +0530 > > freedreno/registers: update dsi registers to support dsc > > Display Stream compression (DSC) compresses the display stream in > host which is later decoded by panel. This requires addition of 3 new > DSI registers to support DSC over DSI. > > Signed-off-by: Vinod Koul > Part-of: > > Signed-off-by: Vinod Koul Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/dsi/dsi.xml.h | 80 +++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h > index 4dee6f0bdda6..d1b2a17b0a66 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h > @@ -704,5 +704,85 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) > > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 > > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001 > + > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001 > + > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; > +} > > #endif /* DSI_XML */ > -- > 2.34.1 > -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7603DC4332F for ; Tue, 5 Apr 2022 23:26:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391126AbiDEXFi (ORCPT ); Tue, 5 Apr 2022 19:05:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1443610AbiDEPj7 (ORCPT ); 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bh=ooVTJG6qHCp0yXAPzRm26+nzLP9pRyshNnyYCdC2/cI=; b=Rsg2V+NeLl1+n5hnJCEWl5c8IFsWX+kHnG8kYuHBNrqGvgvaQDI4MnVq0WivCMDP2X cLIWn5nq1G7dohrvy26EIr9n2HnDNpRsR8DhJ0bGjyF3cvWiEwNmIr8IinNJoUldk+s7 fsWxEKjPGEkvyUfPR76kz6fChT/IuOkWSOM0XxpyD3+eEzwWtCiWzv+lomX3mE2CooOR gUKfwAd1Ly616cQRenyTcuJXpbTnAP26TutC6A+3fx9eELYd6aSdE1w3LS17goTuNkHU 4DpefPrRhlUrlfIOVc/jb9ZUuQhh1V6R5PiyEu9fhFmIj4HJw+f9D1avZtg1rbQtQsBV tVNw== X-Gm-Message-State: AOAM530mX4d07JldJZq6qtnrSdMmoRbNisFjVeJwSQEIdKth77+c7xTa OLyMbys97idC4J7YovRHtXnGTZNisnwQXbc6OXTnVw== X-Google-Smtp-Source: ABdhPJyvUqZgngY2xTxFZn28xhxZyEZiZ6UDJJnFxcDrOQUW4IEe+56aagmVfjuPhPAcWrPVD5R+J8V5qHnj4OpopWI= X-Received: by 2002:ac8:4e52:0:b0:2e1:dad8:5141 with SMTP id e18-20020ac84e52000000b002e1dad85141mr3050575qtw.62.1649167033885; Tue, 05 Apr 2022 06:57:13 -0700 (PDT) MIME-Version: 1.0 References: <20220404163436.956875-1-vkoul@kernel.org> <20220404163436.956875-14-vkoul@kernel.org> In-Reply-To: <20220404163436.956875-14-vkoul@kernel.org> From: Dmitry Baryshkov Date: Tue, 5 Apr 2022 16:57:02 +0300 Message-ID: Subject: Re: [PATCH v6 13/14] drm/msm: Update generated headers To: Vinod Koul Cc: Rob Clark , linux-arm-msm@vger.kernel.org, Bjorn Andersson , David Airlie , Daniel Vetter , Jonathan Marek , Abhinav Kumar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, 4 Apr 2022 at 19:35, Vinod Koul wrote: > > Update headers from mesa commit: > > commit 28ae397be111c37c6ced397e12d453a7695701bd > Author: Vinod Koul > Date: Fri Apr 1 16:53:04 2022 +0530 > > freedreno/registers: update dsi registers to support dsc > > Display Stream compression (DSC) compresses the display stream in > host which is later decoded by panel. This requires addition of 3 new > DSI registers to support DSC over DSI. > > Signed-off-by: Vinod Koul > Part-of: > > Signed-off-by: Vinod Koul Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/dsi/dsi.xml.h | 80 +++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h > index 4dee6f0bdda6..d1b2a17b0a66 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h > @@ -704,5 +704,85 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) > > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 > > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030 > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4 > +static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK; > +} > +#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001 > + > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001 > + > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000 > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK; > +} > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff > +#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0 > +static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val) > +{ > + return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; > +} > > #endif /* DSI_XML */ > -- > 2.34.1 > -- With best wishes Dmitry