From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Date: Fri, 12 Jul 2013 00:41:59 -0300
Subject: [U-Boot] [PATCH] net: fec: Avoid MX28 bus sync issue
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References: <1373583784-7129-1-git-send-email-marex@denx.de>
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On Thu, Jul 11, 2013 at 8:18 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Jul 11, 2013 at 8:03 PM, Marek Vasut <marex@denx.de> wrote:
>> The MX28 multi-layer AHB bus can be too slow and trigger the
>> FEC DMA too early, before all the data hit the DRAM. This patch
>> ensures the data are written in the RAM before the DMA starts.
>> Please see the comment in the patch for full details.
>>
>> This patch was produced with an amazing help from Albert Aribaud,
>> who pointed out it can possibly be such a bus synchronisation
>> issue.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>
> Excellent, managed to transfer 90MB via TFTP on mx28evk without a
> single timeout.
>
> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>

It's working here too.

Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>