From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78F91C43214 for ; Sun, 29 Aug 2021 20:50:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59E5360F46 for ; Sun, 29 Aug 2021 20:50:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235475AbhH2Uvj (ORCPT ); Sun, 29 Aug 2021 16:51:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234955AbhH2Uvh (ORCPT ); Sun, 29 Aug 2021 16:51:37 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 335C2C0613D9 for ; Sun, 29 Aug 2021 13:50:45 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id j13so13209835edv.13 for ; Sun, 29 Aug 2021 13:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=XZidhiGGeZHDe0k1/vjoba3xx0Zek1MPYwws0fBuZuQfZCHvE9gFzJahUipyyF9pEx az0Y4VAokmxqq1+HBUWytSLzqZNgDtxlvMKMLAMgKFo4Ne3GFtslK7IsJcNXqK7WINyg R01vqgdhHItsymuoUX4yGGgKLsuUI/ws9KV09shFCyhyRTLV9QXESf00woZGJWkkXw7l 5RnLxcP+yCJ9AI6r9QiHDhJuQcAKNgr1WgSS8e/0IsQeKnK48toJvUo3L/vsgET0xWFR 6D8XI+UBxApXehLnd+jtJGfmsJlr2NAzLwz8q0/0CyBvxqPPioDiSpzXd1u+NsslpR3O qLeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=QvbvJFcdN5nv02nrxWoU3RYm4eUxTP9eek74/8xB8OEeFnL2c0E+n6BfCnZfn01RNS eSwIsTwndbCJnmvCy+hMqe6kascpei8Pmg8zg/PnCdoomOw/IQh15Ub/EnXAn9Ym3Dam fsMJ05e5DC3S4g1AIJ8y3mOUT8l7fPGRkDSmjPH9YXywXxYR670/5RX0f7JDrsaOUIGT FpX2bWfP6aPwGCwrHbGRGBC66BS9+CSnVb2ihynSPqQP6lPfiLAPk5YGowQuQM7d6XVo yIT1mB3UZCd/vrbWaVvhH8tXB/UcFX3Wb8C+42dABZiew2+ZkQIW31o5BMdaiym2VJo8 gk3A== X-Gm-Message-State: AOAM5306ujGgUcVGJtmIpsapmnIB+9APh9AdqboF4hftKHLYeiFVswtD SzuhcI6BO5tlIhet2er/JQWOlvJ8yTrqazJC4fwytQ== X-Google-Smtp-Source: ABdhPJyTYIXkeNUZ78XZeBzzgBGieSJ37P8sW+ZQpTHTbP0ZiZXot4HF8VDGsgAhSnXVEMcHGQJEAR4F+Yz13AYvoZA= X-Received: by 2002:aa7:db8b:: with SMTP id u11mr20368778edt.362.1630270243611; Sun, 29 Aug 2021 13:50:43 -0700 (PDT) MIME-Version: 1.0 References: <20210811025801.21597-1-yunfei.dong@mediatek.com> <20210811025801.21597-14-yunfei.dong@mediatek.com> In-Reply-To: From: Ezequiel Garcia Date: Sun, 29 Aug 2021 17:50:31 -0300 Message-ID: Subject: Re: [PATCH v5, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 To: Laurent Pinchart Cc: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Fritz Koenig , Irui Wang , linux-media , devicetree , Linux Kernel Mailing List , linux-arm-kernel , srv_heupstream , "moderated list:ARM/Mediatek SoC support" , Project_Global_Chrome_Upstream_Group , George Sun Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 11 Aug 2021 at 14:59, Laurent Pinchart wrote: > > Hi Yunfei, > > Thank you for the patch. > > On Wed, Aug 11, 2021 at 10:57:59AM +0800, Yunfei Dong wrote: > > Adds decoder dt-bindings for mt8192. > > > > Signed-off-by: Yunfei Dong > > --- > > v5: no changes > > > > This patch depends on "Mediatek MT8192 clock support"[1]. > > > > The definition of decoder clocks are in mt8192-clk.h, need to include them in case of build fail [1]. > > > > [1]https://patchwork.kernel.org/project/linux-mediatek/list/?series=511175 > > --- > > .../media/mediatek,vcodec-comp-decoder.yaml | 172 ++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > new file mode 100644 > > index 000000000000..083c89933917 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > @@ -0,0 +1,172 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek Video Decode Accelerator With Component > > + > > +maintainers: > > + - Yunfei Dong > > + > > +description: |+ > > + Mediatek Video Decode is the video decode hardware present in Mediatek > > + SoCs which supports high resolution decoding functionalities. Required > > + master and component node. > > This should explain how the three IP cores relate to each other. > > > + > > +properties: > > + compatible: > > + oneOf: > > + - enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 5 > > + > > + clock-names: > > + items: > > + - const: vdec-sel > > + - const: vdec-soc-vdec > > + - const: vdec-soc-lat > > + - const: vdec-vdec > > + - const: vdec-top > > + > > + assigned-clocks: true > > + > > + assigned-clock-parents: true > > + > > + power-domains: > > + maxItems: 1 > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + dma-ranges: > > + maxItems: 1 > > + description: | > > + Describes the physical address space of IOMMU maps to memory. > > + > > + mediatek,scp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + maxItems: 1 > > + description: > > + Describes point to scp. > > + > > +required: > > + - compatible > > + - reg > > + - iommus > > + - dma-ranges > > + > > +allOf: > > + - if: #master node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + > > + then: > > + required: > > + - mediatek,scp > > + > > + - if: #component node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + then: > > + required: > > + - interrupts > > + - clocks > > + - clock-names > > + - assigned-clocks > > + - assigned-clock-parents > > + - power-domains > > + > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #include > > + #include > > + #include > > + > > + vcodec_dec: vcodec_dec@16000000 { > > + compatible = "mediatek,mt8192-vcodec-dec"; > > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ > > + mediatek,scp = <&scp>; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + }; > > + > > + vcodec_lat: vcodec_lat@0x16010000 { > > + compatible = "mediatek,mtk-vcodec-lat"; > > + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > > + }; > > + > > + vcodec_core: vcodec_core@0x16025000 { > > + compatible = "mediatek,mtk-vcodec-core"; > > + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys CLK_VDEC_VDEC>, > > + <&vdecsys CLK_VDEC_LAT>, > > + <&vdecsys CLK_VDEC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > > + }; > > I'm a bit late in the game, reviewing v5 only, but I'm wondering if > those IP cores need to be modelled in separate nodes. It would be much > easier, from a software point of view, to have a single node, with > multiple register ranges. > > Are some of those IP cores used in different SoCs, combined in different > ways, that make a modular design better ? > Yeah, I agree with Laurent here. This way of modelling the different parts of the CODEC as different pieces is the reason why you need a framework to pull them together, such as the component API (I guess v4l2-async could have been used as well). I normally don't bother with driver internals, as its up to each driver author to decide what is best. However, I believe this design is too convoluted, and it may lead other developers to follow the same pattern, so please avoid it. There are several ways of modelling this and initializing or probing the sub-devices, without using any async framework. Thanks, Ezequiel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFFC1C432BE for ; Sun, 29 Aug 2021 20:51:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7608460F46 for ; Sun, 29 Aug 2021 20:51:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7608460F46 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vanguardiasur.com.ar Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=63dUmorCB8f01Ci5Ma0WEUWrA5p/rS+mzxiuQ82NZ5M=; b=1PE9vU8qwXi4So H7W/1atgkh0bNJCRLDy6bLnJ6I4Zc5TN1dnKMJrgNud2KeRRc9X1jEwwh/KU6o4HqtXNQECauKncC pk7wkFaLl5sqRnECrxXjdQy0lmMRAAOlKxN+6nZXl6WjUnxSu+rBFRqhqrOCAnFX7YBgLPQqohxMl Gg81oFimC3rrl+AgPaGmg6eAIbsXh0XH4UQIPNP/kZvBbzoanWbvtDqI10DQLdN2rtejaFHequsUG ygYCiRBQ/VUzuWGGnObhpJeEQEVCBxPqG50Th2ajwSTAuYfAqzq4Ozm/J1m8JV6KhWUXeVEehvI2l MlZv5NCzZU5TH3PS8Jpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKRlT-00G0rB-Ev; Sun, 29 Aug 2021 20:50:51 +0000 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKRlO-00G0pg-5g for linux-mediatek@lists.infradead.org; Sun, 29 Aug 2021 20:50:50 +0000 Received: by mail-ed1-x52f.google.com with SMTP id r7so2550668edd.6 for ; Sun, 29 Aug 2021 13:50:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=XZidhiGGeZHDe0k1/vjoba3xx0Zek1MPYwws0fBuZuQfZCHvE9gFzJahUipyyF9pEx az0Y4VAokmxqq1+HBUWytSLzqZNgDtxlvMKMLAMgKFo4Ne3GFtslK7IsJcNXqK7WINyg R01vqgdhHItsymuoUX4yGGgKLsuUI/ws9KV09shFCyhyRTLV9QXESf00woZGJWkkXw7l 5RnLxcP+yCJ9AI6r9QiHDhJuQcAKNgr1WgSS8e/0IsQeKnK48toJvUo3L/vsgET0xWFR 6D8XI+UBxApXehLnd+jtJGfmsJlr2NAzLwz8q0/0CyBvxqPPioDiSpzXd1u+NsslpR3O qLeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=hS5csBe8j26INdEwnG5OZfUXUd5/VADfi/pQsRg7JCNViHeLjCu2xDNhAXp2EubuUW qwYvX++cwN2PE0x1O7EtJeWurIehJBYSHkzEMwZKoslD5LDTC/WHAFOHzHrbKi8BBF4u iFzB3phOu4IuKT8La6CO1NIns1H80dB2C8g5hC38FYmt+/tGr+tejUdP+o7BazOlC9Sc bQ36XlIa3pFmFdJQepmx1Q9oFkGyBhcKWHFYtUogIdhhtwpSh8QkpZsBbdrvSUGv6cWb BkOFWngAAb15BNO8EfEGblPHf3Kpz72kw0NpB47itDBOYQiFtJXgdi8QW263w8JVWThW rBKg== X-Gm-Message-State: AOAM533yNVdTQ6d1LU2G/hevMWx2FLrwLPkw3oAsjmQLyAw8BnU5XfWn 7aokIjAr/hPgpbcNuc7f5DPbxL91kyd8BnmyZfAnJA== X-Google-Smtp-Source: ABdhPJyTYIXkeNUZ78XZeBzzgBGieSJ37P8sW+ZQpTHTbP0ZiZXot4HF8VDGsgAhSnXVEMcHGQJEAR4F+Yz13AYvoZA= X-Received: by 2002:aa7:db8b:: with SMTP id u11mr20368778edt.362.1630270243611; Sun, 29 Aug 2021 13:50:43 -0700 (PDT) MIME-Version: 1.0 References: <20210811025801.21597-1-yunfei.dong@mediatek.com> <20210811025801.21597-14-yunfei.dong@mediatek.com> In-Reply-To: From: Ezequiel Garcia Date: Sun, 29 Aug 2021 17:50:31 -0300 Message-ID: Subject: Re: [PATCH v5, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 To: Laurent Pinchart Cc: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Fritz Koenig , Irui Wang , linux-media , devicetree , Linux Kernel Mailing List , linux-arm-kernel , srv_heupstream , "moderated list:ARM/Mediatek SoC support" , Project_Global_Chrome_Upstream_Group , George Sun X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_135046_433021_5C7C48BF X-CRM114-Status: GOOD ( 30.90 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 11 Aug 2021 at 14:59, Laurent Pinchart wrote: > > Hi Yunfei, > > Thank you for the patch. > > On Wed, Aug 11, 2021 at 10:57:59AM +0800, Yunfei Dong wrote: > > Adds decoder dt-bindings for mt8192. > > > > Signed-off-by: Yunfei Dong > > --- > > v5: no changes > > > > This patch depends on "Mediatek MT8192 clock support"[1]. > > > > The definition of decoder clocks are in mt8192-clk.h, need to include them in case of build fail [1]. > > > > [1]https://patchwork.kernel.org/project/linux-mediatek/list/?series=511175 > > --- > > .../media/mediatek,vcodec-comp-decoder.yaml | 172 ++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > new file mode 100644 > > index 000000000000..083c89933917 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > @@ -0,0 +1,172 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek Video Decode Accelerator With Component > > + > > +maintainers: > > + - Yunfei Dong > > + > > +description: |+ > > + Mediatek Video Decode is the video decode hardware present in Mediatek > > + SoCs which supports high resolution decoding functionalities. Required > > + master and component node. > > This should explain how the three IP cores relate to each other. > > > + > > +properties: > > + compatible: > > + oneOf: > > + - enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 5 > > + > > + clock-names: > > + items: > > + - const: vdec-sel > > + - const: vdec-soc-vdec > > + - const: vdec-soc-lat > > + - const: vdec-vdec > > + - const: vdec-top > > + > > + assigned-clocks: true > > + > > + assigned-clock-parents: true > > + > > + power-domains: > > + maxItems: 1 > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + dma-ranges: > > + maxItems: 1 > > + description: | > > + Describes the physical address space of IOMMU maps to memory. > > + > > + mediatek,scp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + maxItems: 1 > > + description: > > + Describes point to scp. > > + > > +required: > > + - compatible > > + - reg > > + - iommus > > + - dma-ranges > > + > > +allOf: > > + - if: #master node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + > > + then: > > + required: > > + - mediatek,scp > > + > > + - if: #component node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + then: > > + required: > > + - interrupts > > + - clocks > > + - clock-names > > + - assigned-clocks > > + - assigned-clock-parents > > + - power-domains > > + > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #include > > + #include > > + #include > > + > > + vcodec_dec: vcodec_dec@16000000 { > > + compatible = "mediatek,mt8192-vcodec-dec"; > > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ > > + mediatek,scp = <&scp>; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + }; > > + > > + vcodec_lat: vcodec_lat@0x16010000 { > > + compatible = "mediatek,mtk-vcodec-lat"; > > + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > > + }; > > + > > + vcodec_core: vcodec_core@0x16025000 { > > + compatible = "mediatek,mtk-vcodec-core"; > > + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys CLK_VDEC_VDEC>, > > + <&vdecsys CLK_VDEC_LAT>, > > + <&vdecsys CLK_VDEC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > > + }; > > I'm a bit late in the game, reviewing v5 only, but I'm wondering if > those IP cores need to be modelled in separate nodes. It would be much > easier, from a software point of view, to have a single node, with > multiple register ranges. > > Are some of those IP cores used in different SoCs, combined in different > ways, that make a modular design better ? > Yeah, I agree with Laurent here. This way of modelling the different parts of the CODEC as different pieces is the reason why you need a framework to pull them together, such as the component API (I guess v4l2-async could have been used as well). I normally don't bother with driver internals, as its up to each driver author to decide what is best. However, I believe this design is too convoluted, and it may lead other developers to follow the same pattern, so please avoid it. There are several ways of modelling this and initializing or probing the sub-devices, without using any async framework. Thanks, Ezequiel _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE82BC432BE for ; Sun, 29 Aug 2021 20:53:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 473F260F45 for ; Sun, 29 Aug 2021 20:53:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 473F260F45 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vanguardiasur.com.ar Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ivOZDOjRDicmTRjTYX2U4RbDsGf+QwiibkSD2v5VTzY=; b=Yvt61nBxEiIlLA FGMchDUNhk1HxC7zk8rXhwwtnz+iQB4zoGKKuozav6R+yF+u3qn0bMbuFqSjv/21nvKwdvuYbpKYB VhCyp9uIiWcQF4t0HUuDRzojObRoh9N+wxWzMxQ+e9ciCYDHwammEkFZ6E11weMyvxPnn1LQvgonT f7HlulLg/gT0mBslJLnVOQHltLJ/4oz/pIWCrS/DbRRN9SkItXaCilc5gFXhTCs9U1HUIdEyIEKSG d8jchwIaqFYpa1vKajGIq7p7GDEzfH+yFsLDcmkTkEM4bJKpHo8gwE6jB83fO1ZTtXgA+BWSPdPbH fgeOdThK31t+u/ZHwKTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKRlV-00G0rN-B7; Sun, 29 Aug 2021 20:50:53 +0000 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKRlO-00G0pf-4w for linux-arm-kernel@lists.infradead.org; Sun, 29 Aug 2021 20:50:50 +0000 Received: by mail-ed1-x52d.google.com with SMTP id s25so18634507edw.0 for ; Sun, 29 Aug 2021 13:50:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=XZidhiGGeZHDe0k1/vjoba3xx0Zek1MPYwws0fBuZuQfZCHvE9gFzJahUipyyF9pEx az0Y4VAokmxqq1+HBUWytSLzqZNgDtxlvMKMLAMgKFo4Ne3GFtslK7IsJcNXqK7WINyg R01vqgdhHItsymuoUX4yGGgKLsuUI/ws9KV09shFCyhyRTLV9QXESf00woZGJWkkXw7l 5RnLxcP+yCJ9AI6r9QiHDhJuQcAKNgr1WgSS8e/0IsQeKnK48toJvUo3L/vsgET0xWFR 6D8XI+UBxApXehLnd+jtJGfmsJlr2NAzLwz8q0/0CyBvxqPPioDiSpzXd1u+NsslpR3O qLeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=bdNYVnY8wew5VKV8LOdUkcIS13QxalxT7B4uy/fmPwU=; b=Q7Y6n7nZY4Jwq7vFp9L1b8oKXY8+oIObY0F5S16mUlNWo39AXo0FdZqaj20MH4aOzh U7SSEIKGuk5LLHE114bmwV+Hlzt+nYfY8255H96XUo74gKEWjJzc/i31/MvY6GDYz/5R A/pCdQdxWE6Rhl8Ur9WBQi/cAyTI2uwzw5TRtJD3giCMn4Ld8q3oQWSxnfuD5yXibled jSvUTrigPK+yBFNGvZVUOC/30ivhAufx1Gbr/mWlVHwG4jKbWfns404l6KyzbrSVa9rS JX3603V8ipU5ExtTUQHixNRG6zPS75xIlk4Jw6jyZ+o/AGnbPk9enyAHVwSoxlS09l/h 6/Ag== X-Gm-Message-State: AOAM532c8duL3hARtF3wx+DAOiI4+Ul/LIRjMzFQXp6P7cAmK4qFGUnu p9SbrpYSFQZfhAyEtxwDQRDkpUuUGkFtskwFa0xbuQ== X-Google-Smtp-Source: ABdhPJyTYIXkeNUZ78XZeBzzgBGieSJ37P8sW+ZQpTHTbP0ZiZXot4HF8VDGsgAhSnXVEMcHGQJEAR4F+Yz13AYvoZA= X-Received: by 2002:aa7:db8b:: with SMTP id u11mr20368778edt.362.1630270243611; Sun, 29 Aug 2021 13:50:43 -0700 (PDT) MIME-Version: 1.0 References: <20210811025801.21597-1-yunfei.dong@mediatek.com> <20210811025801.21597-14-yunfei.dong@mediatek.com> In-Reply-To: From: Ezequiel Garcia Date: Sun, 29 Aug 2021 17:50:31 -0300 Message-ID: Subject: Re: [PATCH v5, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 To: Laurent Pinchart Cc: Yunfei Dong , Alexandre Courbot , Hans Verkuil , Tzung-Bi Shih , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa , Hsin-Yi Wang , Fritz Koenig , Irui Wang , linux-media , devicetree , Linux Kernel Mailing List , linux-arm-kernel , srv_heupstream , "moderated list:ARM/Mediatek SoC support" , Project_Global_Chrome_Upstream_Group , George Sun X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210829_135046_433183_6F82EB45 X-CRM114-Status: GOOD ( 32.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 11 Aug 2021 at 14:59, Laurent Pinchart wrote: > > Hi Yunfei, > > Thank you for the patch. > > On Wed, Aug 11, 2021 at 10:57:59AM +0800, Yunfei Dong wrote: > > Adds decoder dt-bindings for mt8192. > > > > Signed-off-by: Yunfei Dong > > --- > > v5: no changes > > > > This patch depends on "Mediatek MT8192 clock support"[1]. > > > > The definition of decoder clocks are in mt8192-clk.h, need to include them in case of build fail [1]. > > > > [1]https://patchwork.kernel.org/project/linux-mediatek/list/?series=511175 > > --- > > .../media/mediatek,vcodec-comp-decoder.yaml | 172 ++++++++++++++++++ > > 1 file changed, 172 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > new file mode 100644 > > index 000000000000..083c89933917 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml > > @@ -0,0 +1,172 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek Video Decode Accelerator With Component > > + > > +maintainers: > > + - Yunfei Dong > > + > > +description: |+ > > + Mediatek Video Decode is the video decode hardware present in Mediatek > > + SoCs which supports high resolution decoding functionalities. Required > > + master and component node. > > This should explain how the three IP cores relate to each other. > > > + > > +properties: > > + compatible: > > + oneOf: > > + - enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 5 > > + > > + clock-names: > > + items: > > + - const: vdec-sel > > + - const: vdec-soc-vdec > > + - const: vdec-soc-lat > > + - const: vdec-vdec > > + - const: vdec-top > > + > > + assigned-clocks: true > > + > > + assigned-clock-parents: true > > + > > + power-domains: > > + maxItems: 1 > > + > > + iommus: > > + minItems: 1 > > + maxItems: 32 > > + description: | > > + List of the hardware port in respective IOMMU block for current Socs. > > + Refer to bindings/iommu/mediatek,iommu.yaml. > > + > > + dma-ranges: > > + maxItems: 1 > > + description: | > > + Describes the physical address space of IOMMU maps to memory. > > + > > + mediatek,scp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + maxItems: 1 > > + description: > > + Describes point to scp. > > + > > +required: > > + - compatible > > + - reg > > + - iommus > > + - dma-ranges > > + > > +allOf: > > + - if: #master node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mt8192-vcodec-dec # for lat hardware > > + > > + then: > > + required: > > + - mediatek,scp > > + > > + - if: #component node > > + properties: > > + compatible: > > + contains: > > + enum: > > + - mediatek,mtk-vcodec-lat # for core hardware > > + - mediatek,mtk-vcodec-core > > + > > + then: > > + required: > > + - interrupts > > + - clocks > > + - clock-names > > + - assigned-clocks > > + - assigned-clock-parents > > + - power-domains > > + > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #include > > + #include > > + #include > > + > > + vcodec_dec: vcodec_dec@16000000 { > > + compatible = "mediatek,mt8192-vcodec-dec"; > > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ > > + mediatek,scp = <&scp>; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + }; > > + > > + vcodec_lat: vcodec_lat@0x16010000 { > > + compatible = "mediatek,mtk-vcodec-lat"; > > + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, > > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, > > + <&vdecsys_soc CLK_VDEC_SOC_LAT>, > > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; > > + }; > > + > > + vcodec_core: vcodec_core@0x16025000 { > > + compatible = "mediatek,mtk-vcodec-core"; > > + reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */ > > + interrupts = ; > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, > > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>, > > + <&vdecsys CLK_VDEC_VDEC>, > > + <&vdecsys CLK_VDEC_LAT>, > > + <&vdecsys CLK_VDEC_LARB1>, > > + <&topckgen CLK_TOP_MAINPLL_D4>; > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat", > > + "vdec-vdec", "vdec-top"; > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; > > + }; > > I'm a bit late in the game, reviewing v5 only, but I'm wondering if > those IP cores need to be modelled in separate nodes. It would be much > easier, from a software point of view, to have a single node, with > multiple register ranges. > > Are some of those IP cores used in different SoCs, combined in different > ways, that make a modular design better ? > Yeah, I agree with Laurent here. This way of modelling the different parts of the CODEC as different pieces is the reason why you need a framework to pull them together, such as the component API (I guess v4l2-async could have been used as well). I normally don't bother with driver internals, as its up to each driver author to decide what is best. However, I believe this design is too convoluted, and it may lead other developers to follow the same pattern, so please avoid it. There are several ways of modelling this and initializing or probing the sub-devices, without using any async framework. Thanks, Ezequiel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel