From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw0-f194.google.com ([209.85.161.194]:44978 "EHLO mail-yw0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935997AbeFRJoi (ORCPT ); Mon, 18 Jun 2018 05:44:38 -0400 Received: by mail-yw0-f194.google.com with SMTP id k18-v6so4866774ywm.11 for ; Mon, 18 Jun 2018 02:44:37 -0700 (PDT) Received: from mail-yb0-f170.google.com (mail-yb0-f170.google.com. [209.85.213.170]) by smtp.gmail.com with ESMTPSA id u195-v6sm5423871ywf.83.2018.06.18.02.44.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Jun 2018 02:44:36 -0700 (PDT) Received: by mail-yb0-f170.google.com with SMTP id a16-v6so2882821ybm.2 for ; Mon, 18 Jun 2018 02:44:35 -0700 (PDT) MIME-Version: 1.0 References: <20180612132028.27490-1-heiko@sntech.de> <20180612132028.27490-2-heiko@sntech.de> In-Reply-To: <20180612132028.27490-2-heiko@sntech.de> From: Tomasz Figa Date: Mon, 18 Jun 2018 18:44:24 +0900 Message-ID: Subject: Re: [PATCH v4 1/2] drm/rockchip: vop: split out core clock enablement into separate functions To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: dri-devel , "open list:ARM/Rockchip SoC..." , Ezequiel Garcia , Robin Murphy , marc.zyngier@arm.com, Jeffy , Sandy Huang , enric.balletbo@collabora.co.uk, Tomeu Vizoso , stable@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: stable-owner@vger.kernel.org List-ID: Hi Heiko, On Tue, Jun 12, 2018 at 10:20 PM Heiko Stuebner wrote: > > Judging from the iommu code, both the hclk and aclk are necessary for > register access. Split them off into separate functions from the regular > vop enablement, so that we can use them elsewhere as well. > > Fixes: d0b912bd4c23 ("iommu/rockchip: Request irqs in rk_iommu_probe()") > Cc: stable@vger.kernel.org > Signed-off-by: Heiko Stuebner > Tested-by: Ezequiel Garcia > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 44 +++++++++++++++------ > 1 file changed, 31 insertions(+), 13 deletions(-) Reviewed-by: Tomasz Figa Best regards, Tomasz From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH v4 1/2] drm/rockchip: vop: split out core clock enablement into separate functions Date: Mon, 18 Jun 2018 18:44:24 +0900 Message-ID: References: <20180612132028.27490-1-heiko@sntech.de> <20180612132028.27490-2-heiko@sntech.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180612132028.27490-2-heiko@sntech.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: marc.zyngier@arm.com, Robin Murphy , Jeffy , dri-devel , Tomeu Vizoso , "open list:ARM/Rockchip SoC..." , enric.balletbo@collabora.co.uk, stable@vger.kernel.org, Ezequiel Garcia List-Id: linux-rockchip.vger.kernel.org SGkgSGVpa28sCgpPbiBUdWUsIEp1biAxMiwgMjAxOCBhdCAxMDoyMCBQTSBIZWlrbyBTdHVlYm5l ciA8aGVpa29Ac250ZWNoLmRlPiB3cm90ZToKPgo+IEp1ZGdpbmcgZnJvbSB0aGUgaW9tbXUgY29k ZSwgYm90aCB0aGUgaGNsayBhbmQgYWNsayBhcmUgbmVjZXNzYXJ5IGZvcgo+IHJlZ2lzdGVyIGFj Y2Vzcy4gU3BsaXQgdGhlbSBvZmYgaW50byBzZXBhcmF0ZSBmdW5jdGlvbnMgZnJvbSB0aGUgcmVn dWxhcgo+IHZvcCBlbmFibGVtZW50LCBzbyB0aGF0IHdlIGNhbiB1c2UgdGhlbSBlbHNld2hlcmUg YXMgd2VsbC4KPgo+IEZpeGVzOiBkMGI5MTJiZDRjMjMgKCJpb21tdS9yb2NrY2hpcDogUmVxdWVz dCBpcnFzIGluIHJrX2lvbW11X3Byb2JlKCkiKQo+IENjOiBzdGFibGVAdmdlci5rZXJuZWwub3Jn Cj4gU2lnbmVkLW9mZi1ieTogSGVpa28gU3R1ZWJuZXIgPGhlaWtvQHNudGVjaC5kZT4KPiBUZXN0 ZWQtYnk6IEV6ZXF1aWVsIEdhcmNpYSA8ZXplcXVpZWxAY29sbGFib3JhLmNvbT4KPiAtLS0KPiAg ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuYyB8IDQ0ICsrKysrKysr KysrKysrKy0tLS0tLQo+ICAxIGZpbGUgY2hhbmdlZCwgMzEgaW5zZXJ0aW9ucygrKSwgMTMgZGVs ZXRpb25zKC0pCgpSZXZpZXdlZC1ieTogVG9tYXN6IEZpZ2EgPHRmaWdhQGNocm9taXVtLm9yZz4K CkJlc3QgcmVnYXJkcywKVG9tYXN6Cl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVk ZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZv L2RyaS1kZXZlbAo=