From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932281AbbLBAKe (ORCPT ); Tue, 1 Dec 2015 19:10:34 -0500 Received: from mail-wm0-f53.google.com ([74.125.82.53]:37699 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932128AbbLBAKb (ORCPT ); Tue, 1 Dec 2015 19:10:31 -0500 MIME-Version: 1.0 In-Reply-To: <1449013103-23238-6-git-send-email-tony@atomide.com> References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> From: Matthijs van Duin Date: Wed, 2 Dec 2015 01:10:10 +0100 Message-ID: Subject: Re: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx To: Tony Lindgren Cc: lkml , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Brian Hutchinson , Delio Brignoli , Neil Armstrong , Philipp Rosenberger , Paul Walmsley Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2 December 2015 at 00:38, Tony Lindgren wrote: > Looks like GPIO softreset status bit on both dm8168 and dm8148 > is broken and only goes high initially. After writing to sysc > softreset bit, the resetdone bit never goes high again. The resetdone bit works fine, but it needs all clocks active to come up. You're neglecting to enable the debounce clock to the GPIO module: > # mw.l 0x4818155c 0x2 That should write 0x102 instead. You can disable the debounce clock after resetting the module if you don't need it, though I doubt there's any significant power savings there. (More likely it exists as a separate bit to allow it to stay enabled even if the module isn't, for wakeup on debounced inputs.) Matthijs From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthijs van Duin Subject: Re: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx Date: Wed, 2 Dec 2015 01:10:10 +0100 Message-ID: References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1449013103-23238-6-git-send-email-tony@atomide.com> Sender: linux-kernel-owner@vger.kernel.org To: Tony Lindgren Cc: lkml , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Brian Hutchinson , Delio Brignoli , Neil Armstrong , Philipp Rosenberger , Paul Walmsley List-Id: linux-omap@vger.kernel.org On 2 December 2015 at 00:38, Tony Lindgren wrote: > Looks like GPIO softreset status bit on both dm8168 and dm8148 > is broken and only goes high initially. After writing to sysc > softreset bit, the resetdone bit never goes high again. The resetdone bit works fine, but it needs all clocks active to come up. You're neglecting to enable the debounce clock to the GPIO module: > # mw.l 0x4818155c 0x2 That should write 0x102 instead. You can disable the debounce clock after resetting the module if you don't need it, though I doubt there's any significant power savings there. (More likely it exists as a separate bit to allow it to stay enabled even if the module isn't, for wakeup on debounced inputs.) Matthijs From mboxrd@z Thu Jan 1 00:00:00 1970 From: matthijsvanduin@gmail.com (Matthijs van Duin) Date: Wed, 2 Dec 2015 01:10:10 +0100 Subject: [PATCH 05/10] ARM: OMAP2+: Disable GPIO softreset for dm81xx In-Reply-To: <1449013103-23238-6-git-send-email-tony@atomide.com> References: <1449013103-23238-1-git-send-email-tony@atomide.com> <1449013103-23238-6-git-send-email-tony@atomide.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2 December 2015 at 00:38, Tony Lindgren wrote: > Looks like GPIO softreset status bit on both dm8168 and dm8148 > is broken and only goes high initially. After writing to sysc > softreset bit, the resetdone bit never goes high again. The resetdone bit works fine, but it needs all clocks active to come up. You're neglecting to enable the debounce clock to the GPIO module: > # mw.l 0x4818155c 0x2 That should write 0x102 instead. You can disable the debounce clock after resetting the module if you don't need it, though I doubt there's any significant power savings there. (More likely it exists as a separate bit to allow it to stay enabled even if the module isn't, for wakeup on debounced inputs.) Matthijs