[PATCH v6 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195

[PATCH v6 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195

[jason-jh.lin]

The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (7):
  arm64: dts: mt8195: add display node for vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: adjust to the alphabetic order for mediatek-drm
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

 arch/arm64/boot/dts/mediatek/mt8195.dtsi    | 112 +++++++++
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c    |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 242 +++++++++++-------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  24 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 108 +++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 drivers/soc/mediatek/mt8195-mmsys.h         |  96 +++++++
 drivers/soc/mediatek/mtk-mmsys.c            |  11 +
 drivers/soc/mediatek/mtk-mutex.c            |  93 ++++++-
 include/linux/soc/mediatek/mtk-mmsys.h      |   9 +
 13 files changed, 825 insertions(+), 149 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195

[jason-jh.lin]

The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (7):
  arm64: dts: mt8195: add display node for vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: adjust to the alphabetic order for mediatek-drm
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

 arch/arm64/boot/dts/mediatek/mt8195.dtsi    | 112 +++++++++
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c    |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 242 +++++++++++-------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  24 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 108 +++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 drivers/soc/mediatek/mt8195-mmsys.h         |  96 +++++++
 drivers/soc/mediatek/mtk-mmsys.c            |  11 +
 drivers/soc/mediatek/mtk-mutex.c            |  93 ++++++-
 include/linux/soc/mediatek/mtk-mmsys.h      |   9 +
 13 files changed, 825 insertions(+), 149 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195

[jason-jh.lin]

The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (7):
  arm64: dts: mt8195: add display node for vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: adjust to the alphabetic order for mediatek-drm
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

 arch/arm64/boot/dts/mediatek/mt8195.dtsi    | 112 +++++++++
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c    |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 242 +++++++++++-------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  24 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 108 +++++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 drivers/soc/mediatek/mt8195-mmsys.h         |  96 +++++++
 drivers/soc/mediatek/mtk-mmsys.c            |  11 +
 drivers/soc/mediatek/mtk-mutex.c            |  93 ++++++-
 include/linux/soc/mediatek/mtk-mmsys.h      |   9 +
 13 files changed, 825 insertions(+), 149 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0

[PATCH v6 1/7] arm64: dts: mt8195: add display node for vdosys0

[jason-jh.lin]

Add display node for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3][4]

[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
[4]add mt8195 SoC DRM binding
https://patchwork.kernel.org/project/linux-mediatek/list/?series=527069
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..4fa47cb2bede 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,121 @@
 			#clock-cells = <1>;
 		};
 
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl",
+				     "mediatek,mt8183-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr",
+				     "mediatek,mt8183-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal",
+				     "mediatek,mt8173-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma",
+				     "mediatek,mt8173-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+		};
+
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+		};
+
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			clock-names = "vdo0_mutex";
+			mediatek,gce-events =
+				 <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
 		};
 
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 1/7] arm64: dts: mt8195: add display node for vdosys0

[jason-jh.lin]

Add display node for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3][4]

[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
[4]add mt8195 SoC DRM binding
https://patchwork.kernel.org/project/linux-mediatek/list/?series=527069
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..4fa47cb2bede 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,121 @@
 			#clock-cells = <1>;
 		};
 
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl",
+				     "mediatek,mt8183-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr",
+				     "mediatek,mt8183-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal",
+				     "mediatek,mt8173-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma",
+				     "mediatek,mt8173-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+		};
+
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+		};
+
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			clock-names = "vdo0_mutex";
+			mediatek,gce-events =
+				 <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
 		};
 
-- 
2.18.0
_______________________________________________
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[PATCH v6 1/7] arm64: dts: mt8195: add display node for vdosys0

[jason-jh.lin]

Add display node for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3][4]

[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
[4]add mt8195 SoC DRM binding
https://patchwork.kernel.org/project/linux-mediatek/list/?series=527069
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..4fa47cb2bede 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,121 @@
 			#clock-cells = <1>;
 		};
 
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl",
+				     "mediatek,mt8183-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr",
+				     "mediatek,mt8183-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal",
+				     "mediatek,mt8173-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma",
+				     "mediatek,mt8173-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+		};
+
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+		};
+
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			clock-names = "vdo0_mutex";
+			mediatek,gce-events =
+				 <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
 		};
 
-- 
2.18.0

[PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[jason-jh.lin]

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
 3 files changed, 116 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..9339a786ec5d
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
 #include "mtk-mmsys.h"
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8183-mmsys",
 		.data = &mt8183_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{ }
 };
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..01bedfb08094 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[jason-jh.lin]

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
 3 files changed, 116 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..9339a786ec5d
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
 #include "mtk-mmsys.h"
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8183-mmsys",
 		.data = &mt8183_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{ }
 };
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..01bedfb08094 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0
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[PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[jason-jh.lin]

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
 3 files changed, 116 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..9339a786ec5d
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
 #include "mtk-mmsys.h"
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8183-mmsys",
 		.data = &mt8183_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{ }
 };
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..01bedfb08094 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0

[PATCH v6 3/7] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[jason-jh.lin]

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mtk-mutex.c | 93 ++++++++++++++++++++++++++++++--
 1 file changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..cb8bbf7f3fd8 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -101,12 +134,27 @@
 #define MT2712_MUTEX_SOF_DSI3			6
 #define MT8167_MUTEX_SOF_DPI0			2
 #define MT8167_MUTEX_SOF_DPI1			3
+
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
+
 struct mtk_mutex {
 	int id;
 	bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +290,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +298,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
 };
 
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +353,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +592,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8173_mutex_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 3/7] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[jason-jh.lin]

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mtk-mutex.c | 93 ++++++++++++++++++++++++++++++--
 1 file changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..cb8bbf7f3fd8 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -101,12 +134,27 @@
 #define MT2712_MUTEX_SOF_DSI3			6
 #define MT8167_MUTEX_SOF_DPI0			2
 #define MT8167_MUTEX_SOF_DPI1			3
+
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
+
 struct mtk_mutex {
 	int id;
 	bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +290,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +298,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
 };
 
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +353,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +592,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8173_mutex_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 3/7] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[jason-jh.lin]

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/soc/mediatek/mtk-mutex.c | 93 ++++++++++++++++++++++++++++++--
 1 file changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..cb8bbf7f3fd8 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -101,12 +134,27 @@
 #define MT2712_MUTEX_SOF_DSI3			6
 #define MT8167_MUTEX_SOF_DPI0			2
 #define MT8167_MUTEX_SOF_DPI1			3
+
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
 
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
+
 struct mtk_mutex {
 	int id;
 	bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +290,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +298,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
 };
 
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +353,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +592,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8173_mutex_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0

[PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[jason-jh.lin]

1. Adjust to the alphabetic order for the define, function, struct
   and array in mediatek-drm driver
2. Remove the unsed define in mtk_drm_ddp_comp.c

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
 3 files changed, 133 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..328ee19f931e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -20,50 +20,36 @@
 #include "mtk_drm_ddp_comp.h"
 #include "mtk_drm_crtc.h"
 
-#define DISP_OD_EN				0x0000
-#define DISP_OD_INTEN				0x0008
-#define DISP_OD_INTSTA				0x000c
-#define DISP_OD_CFG				0x0020
-#define DISP_OD_SIZE				0x0030
-#define DISP_DITHER_5				0x0114
-#define DISP_DITHER_7				0x011c
-#define DISP_DITHER_15				0x013c
-#define DISP_DITHER_16				0x0140
-
-#define DISP_REG_UFO_START			0x0000
-
-#define DISP_AAL_EN				0x0000
-#define DISP_AAL_SIZE				0x0030
+#define DISP_REG_AAL_EN				0x0000
+#define AAL_EN					BIT(0)
+#define DISP_REG_AAL_SIZE			0x0030
 
-#define DISP_DITHER_EN				0x0000
+#define DISP_REG_DITHER_EN			0x0000
 #define DITHER_EN				BIT(0)
-#define DISP_DITHER_CFG				0x0020
+#define DISP_REG_DITHER_CFG			0x0020
 #define DITHER_RELAY_MODE			BIT(0)
 #define DITHER_ENGINE_EN			BIT(1)
-#define DISP_DITHER_SIZE			0x0030
-
-#define LUT_10BIT_MASK				0x03ff
-
-#define OD_RELAYMODE				BIT(0)
-
-#define UFO_BYPASS				BIT(2)
-
-#define AAL_EN					BIT(0)
-
 #define DISP_DITHERING				BIT(2)
+#define DISP_REG_DITHER_SIZE			0x0030
+#define DISP_REG_DITHER_5			0x0114
+#define DISP_REG_DITHER_7			0x011c
+#define DISP_REG_DITHER_15			0x013c
 #define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)
 #define DITHER_NEW_BIT_MODE			BIT(0)
+#define DISP_REG_DITHER_16			0x0140
 #define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
-#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
-#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)
+
+#define DISP_REG_OD_EN				0x0000
+#define DISP_REG_OD_CFG				0x0020
+#define OD_RELAYMODE				BIT(0)
+#define DISP_REG_OD_SIZE			0x0030
+
+#define DISP_REG_UFO_START			0x0000
+#define UFO_BYPASS				BIT(2)
 
 struct mtk_ddp_comp_dev {
 	struct clk *clk;
@@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 #endif
 }
 
-static int mtk_ddp_clk_enable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	return clk_prepare_enable(priv->clk);
-}
-
-static void mtk_ddp_clk_disable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	clk_disable_unprepare(priv->clk);
-}
-
 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 			   unsigned int bpc, unsigned int cfg,
 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
@@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 		return;
 
 	if (bpc >= MTK_MIN_BPC) {
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_NEW_BIT_MODE,
-			      cmdq_reg, regs, DISP_DITHER_15);
+			      cmdq_reg, regs, DISP_REG_DITHER_15);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
-			      cmdq_reg, regs, DISP_DITHER_16);
+			      cmdq_reg, regs, DISP_REG_DITHER_16);
 		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
 	}
 }
 
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
-		    unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
-			      DISP_DITHERING, cmdq_pkt);
-}
-
-static void mtk_od_config(struct device *dev, unsigned int w,
-			  unsigned int h, unsigned int vrefresh,
-			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
-	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
-	mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
-}
-
-static void mtk_od_start(struct device *dev)
+static int mtk_ddp_clk_enable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(1, priv->regs + DISP_OD_EN);
+	return clk_prepare_enable(priv->clk);
 }
 
-static void mtk_ufoe_start(struct device *dev)
+static void mtk_ddp_clk_disable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
+	clk_disable_unprepare(priv->clk);
 }
 
 static void mtk_aal_config(struct device *dev, unsigned int w,
@@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
 }
 
 static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
@@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(AAL_EN, priv->regs + DISP_AAL_EN);
+	writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_aal_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_dither_config(struct device *dev, unsigned int w,
@@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
-	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_SIZE);
+	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_CFG);
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
 			      DITHER_ENGINE_EN, cmdq_pkt);
 }
 
@@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
+	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
 }
 
 static void mtk_dither_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
+}
+
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
+			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
+			      DISP_DITHERING, cmdq_pkt);
+}
+
+static void mtk_od_config(struct device *dev, unsigned int w,
+			  unsigned int h, unsigned int vrefresh,
+			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
+	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
+	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
+}
+
+static void mtk_od_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(1, priv->regs + DISP_REG_OD_EN);
+}
+
+static void mtk_ufoe_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
 static const struct mtk_ddp_comp_funcs ddp_aal = {
@@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 };
 
 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
+	[MTK_DISP_AAL] = "aal",
+	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_CCORR] = "ccorr",
+	[MTK_DISP_COLOR] = "color",
+	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MUTEX] = "mutex",
+	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
 	[MTK_DISP_OVL_2L] = "ovl-2l",
+	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
-	[MTK_DISP_WDMA] = "wdma",
-	[MTK_DISP_COLOR] = "color",
-	[MTK_DISP_CCORR] = "ccorr",
-	[MTK_DISP_AAL] = "aal",
-	[MTK_DISP_GAMMA] = "gamma",
-	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_UFOE] = "ufoe",
-	[MTK_DSI] = "dsi",
+	[MTK_DISP_WDMA] = "wdma",
 	[MTK_DPI] = "dpi",
-	[MTK_DISP_PWM] = "pwm",
-	[MTK_DISP_MUTEX] = "mutex",
-	[MTK_DISP_OD] = "od",
-	[MTK_DISP_BLS] = "bls",
+	[MTK_DSI] = "dsi",
 };
 
 struct mtk_ddp_comp_match {
@@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
-	    type == MTK_DPI ||
-	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
-	    type == MTK_DISP_RDMA)
+	    type == MTK_DISP_RDMA ||
+	    type == MTK_DPI ||
+	    type == MTK_DSI)
 		return 0;
 
 	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..d317b944df66 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -18,22 +18,22 @@ struct mtk_plane_state;
 struct drm_crtc_state;
 
 enum mtk_ddp_comp_type {
-	MTK_DISP_OVL,
-	MTK_DISP_OVL_2L,
-	MTK_DISP_RDMA,
-	MTK_DISP_WDMA,
-	MTK_DISP_COLOR,
+	MTK_DISP_AAL,
+	MTK_DISP_BLS,
 	MTK_DISP_CCORR,
+	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
-	MTK_DISP_AAL,
 	MTK_DISP_GAMMA,
-	MTK_DISP_UFOE,
-	MTK_DSI,
-	MTK_DPI,
-	MTK_DISP_PWM,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-	MTK_DISP_BLS,
+	MTK_DISP_OVL,
+	MTK_DISP_OVL_2L,
+	MTK_DISP_PWM,
+	MTK_DISP_RDMA,
+	MTK_DISP_UFOE,
+	MTK_DISP_WDMA,
+	MTK_DPI,
+	MTK_DSI,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..a95dc1006b82 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
 };
 
 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
-	{ .compatible = "mediatek,mt2701-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8173-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
-	  .data = (void *)MTK_DISP_OVL_2L },
-	{ .compatible = "mediatek,mt2701-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8183-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-wdma",
-	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt8173-disp-aal",
+	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = (void *)MTK_DISP_CCORR },
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
-	{ .compatible = "mediatek,mt8173-disp-aal",
-	  .data = (void *)MTK_DISP_AAL},
+	{ .compatible = "mediatek,mt8183-disp-dither",
+	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
-	{ .compatible = "mediatek,mt8183-disp-dither",
-	  .data = (void *)MTK_DISP_DITHER },
-	{ .compatible = "mediatek,mt8173-disp-ufoe",
-	  .data = (void *)MTK_DISP_UFOE },
-	{ .compatible = "mediatek,mt2701-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8173-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8183-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt2701-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8173-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8183-dpi",
-	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8173-disp-od",
+	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8173-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
+	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
 	  .data = (void *)MTK_DISP_PWM },
-	{ .compatible = "mediatek,mt8173-disp-od",
-	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8183-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-ufoe",
+	  .data = (void *)MTK_DISP_UFOE },
+	{ .compatible = "mediatek,mt8173-disp-wdma",
+	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8183-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt2701-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8173-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8183-dsi",
+	  .data = (void *)MTK_DSI },
 	{ }
 };
 
@@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
-		    comp_type == MTK_DSI ||
-		    comp_type == MTK_DPI) {
+		    comp_type == MTK_DPI ||
+		    comp_type == MTK_DSI) {
 			dev_info(dev, "Adding component match for %pOF\n",
 				 node);
 			drm_of_component_match_add(dev, &match, compare_of,
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[jason-jh.lin]

1. Adjust to the alphabetic order for the define, function, struct
   and array in mediatek-drm driver
2. Remove the unsed define in mtk_drm_ddp_comp.c

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
 3 files changed, 133 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..328ee19f931e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -20,50 +20,36 @@
 #include "mtk_drm_ddp_comp.h"
 #include "mtk_drm_crtc.h"
 
-#define DISP_OD_EN				0x0000
-#define DISP_OD_INTEN				0x0008
-#define DISP_OD_INTSTA				0x000c
-#define DISP_OD_CFG				0x0020
-#define DISP_OD_SIZE				0x0030
-#define DISP_DITHER_5				0x0114
-#define DISP_DITHER_7				0x011c
-#define DISP_DITHER_15				0x013c
-#define DISP_DITHER_16				0x0140
-
-#define DISP_REG_UFO_START			0x0000
-
-#define DISP_AAL_EN				0x0000
-#define DISP_AAL_SIZE				0x0030
+#define DISP_REG_AAL_EN				0x0000
+#define AAL_EN					BIT(0)
+#define DISP_REG_AAL_SIZE			0x0030
 
-#define DISP_DITHER_EN				0x0000
+#define DISP_REG_DITHER_EN			0x0000
 #define DITHER_EN				BIT(0)
-#define DISP_DITHER_CFG				0x0020
+#define DISP_REG_DITHER_CFG			0x0020
 #define DITHER_RELAY_MODE			BIT(0)
 #define DITHER_ENGINE_EN			BIT(1)
-#define DISP_DITHER_SIZE			0x0030
-
-#define LUT_10BIT_MASK				0x03ff
-
-#define OD_RELAYMODE				BIT(0)
-
-#define UFO_BYPASS				BIT(2)
-
-#define AAL_EN					BIT(0)
-
 #define DISP_DITHERING				BIT(2)
+#define DISP_REG_DITHER_SIZE			0x0030
+#define DISP_REG_DITHER_5			0x0114
+#define DISP_REG_DITHER_7			0x011c
+#define DISP_REG_DITHER_15			0x013c
 #define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)
 #define DITHER_NEW_BIT_MODE			BIT(0)
+#define DISP_REG_DITHER_16			0x0140
 #define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
-#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
-#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)
+
+#define DISP_REG_OD_EN				0x0000
+#define DISP_REG_OD_CFG				0x0020
+#define OD_RELAYMODE				BIT(0)
+#define DISP_REG_OD_SIZE			0x0030
+
+#define DISP_REG_UFO_START			0x0000
+#define UFO_BYPASS				BIT(2)
 
 struct mtk_ddp_comp_dev {
 	struct clk *clk;
@@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 #endif
 }
 
-static int mtk_ddp_clk_enable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	return clk_prepare_enable(priv->clk);
-}
-
-static void mtk_ddp_clk_disable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	clk_disable_unprepare(priv->clk);
-}
-
 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 			   unsigned int bpc, unsigned int cfg,
 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
@@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 		return;
 
 	if (bpc >= MTK_MIN_BPC) {
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_NEW_BIT_MODE,
-			      cmdq_reg, regs, DISP_DITHER_15);
+			      cmdq_reg, regs, DISP_REG_DITHER_15);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
-			      cmdq_reg, regs, DISP_DITHER_16);
+			      cmdq_reg, regs, DISP_REG_DITHER_16);
 		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
 	}
 }
 
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
-		    unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
-			      DISP_DITHERING, cmdq_pkt);
-}
-
-static void mtk_od_config(struct device *dev, unsigned int w,
-			  unsigned int h, unsigned int vrefresh,
-			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
-	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
-	mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
-}
-
-static void mtk_od_start(struct device *dev)
+static int mtk_ddp_clk_enable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(1, priv->regs + DISP_OD_EN);
+	return clk_prepare_enable(priv->clk);
 }
 
-static void mtk_ufoe_start(struct device *dev)
+static void mtk_ddp_clk_disable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
+	clk_disable_unprepare(priv->clk);
 }
 
 static void mtk_aal_config(struct device *dev, unsigned int w,
@@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
 }
 
 static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
@@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(AAL_EN, priv->regs + DISP_AAL_EN);
+	writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_aal_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_dither_config(struct device *dev, unsigned int w,
@@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
-	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_SIZE);
+	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_CFG);
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
 			      DITHER_ENGINE_EN, cmdq_pkt);
 }
 
@@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
+	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
 }
 
 static void mtk_dither_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
+}
+
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
+			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
+			      DISP_DITHERING, cmdq_pkt);
+}
+
+static void mtk_od_config(struct device *dev, unsigned int w,
+			  unsigned int h, unsigned int vrefresh,
+			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
+	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
+	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
+}
+
+static void mtk_od_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(1, priv->regs + DISP_REG_OD_EN);
+}
+
+static void mtk_ufoe_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
 static const struct mtk_ddp_comp_funcs ddp_aal = {
@@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 };
 
 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
+	[MTK_DISP_AAL] = "aal",
+	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_CCORR] = "ccorr",
+	[MTK_DISP_COLOR] = "color",
+	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MUTEX] = "mutex",
+	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
 	[MTK_DISP_OVL_2L] = "ovl-2l",
+	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
-	[MTK_DISP_WDMA] = "wdma",
-	[MTK_DISP_COLOR] = "color",
-	[MTK_DISP_CCORR] = "ccorr",
-	[MTK_DISP_AAL] = "aal",
-	[MTK_DISP_GAMMA] = "gamma",
-	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_UFOE] = "ufoe",
-	[MTK_DSI] = "dsi",
+	[MTK_DISP_WDMA] = "wdma",
 	[MTK_DPI] = "dpi",
-	[MTK_DISP_PWM] = "pwm",
-	[MTK_DISP_MUTEX] = "mutex",
-	[MTK_DISP_OD] = "od",
-	[MTK_DISP_BLS] = "bls",
+	[MTK_DSI] = "dsi",
 };
 
 struct mtk_ddp_comp_match {
@@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
-	    type == MTK_DPI ||
-	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
-	    type == MTK_DISP_RDMA)
+	    type == MTK_DISP_RDMA ||
+	    type == MTK_DPI ||
+	    type == MTK_DSI)
 		return 0;
 
 	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..d317b944df66 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -18,22 +18,22 @@ struct mtk_plane_state;
 struct drm_crtc_state;
 
 enum mtk_ddp_comp_type {
-	MTK_DISP_OVL,
-	MTK_DISP_OVL_2L,
-	MTK_DISP_RDMA,
-	MTK_DISP_WDMA,
-	MTK_DISP_COLOR,
+	MTK_DISP_AAL,
+	MTK_DISP_BLS,
 	MTK_DISP_CCORR,
+	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
-	MTK_DISP_AAL,
 	MTK_DISP_GAMMA,
-	MTK_DISP_UFOE,
-	MTK_DSI,
-	MTK_DPI,
-	MTK_DISP_PWM,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-	MTK_DISP_BLS,
+	MTK_DISP_OVL,
+	MTK_DISP_OVL_2L,
+	MTK_DISP_PWM,
+	MTK_DISP_RDMA,
+	MTK_DISP_UFOE,
+	MTK_DISP_WDMA,
+	MTK_DPI,
+	MTK_DSI,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..a95dc1006b82 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
 };
 
 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
-	{ .compatible = "mediatek,mt2701-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8173-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
-	  .data = (void *)MTK_DISP_OVL_2L },
-	{ .compatible = "mediatek,mt2701-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8183-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-wdma",
-	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt8173-disp-aal",
+	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = (void *)MTK_DISP_CCORR },
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
-	{ .compatible = "mediatek,mt8173-disp-aal",
-	  .data = (void *)MTK_DISP_AAL},
+	{ .compatible = "mediatek,mt8183-disp-dither",
+	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
-	{ .compatible = "mediatek,mt8183-disp-dither",
-	  .data = (void *)MTK_DISP_DITHER },
-	{ .compatible = "mediatek,mt8173-disp-ufoe",
-	  .data = (void *)MTK_DISP_UFOE },
-	{ .compatible = "mediatek,mt2701-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8173-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8183-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt2701-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8173-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8183-dpi",
-	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8173-disp-od",
+	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8173-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
+	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
 	  .data = (void *)MTK_DISP_PWM },
-	{ .compatible = "mediatek,mt8173-disp-od",
-	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8183-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-ufoe",
+	  .data = (void *)MTK_DISP_UFOE },
+	{ .compatible = "mediatek,mt8173-disp-wdma",
+	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8183-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt2701-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8173-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8183-dsi",
+	  .data = (void *)MTK_DSI },
 	{ }
 };
 
@@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
-		    comp_type == MTK_DSI ||
-		    comp_type == MTK_DPI) {
+		    comp_type == MTK_DPI ||
+		    comp_type == MTK_DSI) {
 			dev_info(dev, "Adding component match for %pOF\n",
 				 node);
 			drm_of_component_match_add(dev, &match, compare_of,
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[jason-jh.lin]

1. Adjust to the alphabetic order for the define, function, struct
   and array in mediatek-drm driver
2. Remove the unsed define in mtk_drm_ddp_comp.c

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
 3 files changed, 133 insertions(+), 145 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..328ee19f931e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -20,50 +20,36 @@
 #include "mtk_drm_ddp_comp.h"
 #include "mtk_drm_crtc.h"
 
-#define DISP_OD_EN				0x0000
-#define DISP_OD_INTEN				0x0008
-#define DISP_OD_INTSTA				0x000c
-#define DISP_OD_CFG				0x0020
-#define DISP_OD_SIZE				0x0030
-#define DISP_DITHER_5				0x0114
-#define DISP_DITHER_7				0x011c
-#define DISP_DITHER_15				0x013c
-#define DISP_DITHER_16				0x0140
-
-#define DISP_REG_UFO_START			0x0000
-
-#define DISP_AAL_EN				0x0000
-#define DISP_AAL_SIZE				0x0030
+#define DISP_REG_AAL_EN				0x0000
+#define AAL_EN					BIT(0)
+#define DISP_REG_AAL_SIZE			0x0030
 
-#define DISP_DITHER_EN				0x0000
+#define DISP_REG_DITHER_EN			0x0000
 #define DITHER_EN				BIT(0)
-#define DISP_DITHER_CFG				0x0020
+#define DISP_REG_DITHER_CFG			0x0020
 #define DITHER_RELAY_MODE			BIT(0)
 #define DITHER_ENGINE_EN			BIT(1)
-#define DISP_DITHER_SIZE			0x0030
-
-#define LUT_10BIT_MASK				0x03ff
-
-#define OD_RELAYMODE				BIT(0)
-
-#define UFO_BYPASS				BIT(2)
-
-#define AAL_EN					BIT(0)
-
 #define DISP_DITHERING				BIT(2)
+#define DISP_REG_DITHER_SIZE			0x0030
+#define DISP_REG_DITHER_5			0x0114
+#define DISP_REG_DITHER_7			0x011c
+#define DISP_REG_DITHER_15			0x013c
 #define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)
 #define DITHER_NEW_BIT_MODE			BIT(0)
+#define DISP_REG_DITHER_16			0x0140
 #define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
-#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)
 #define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
-#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
-#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
-#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)
+
+#define DISP_REG_OD_EN				0x0000
+#define DISP_REG_OD_CFG				0x0020
+#define OD_RELAYMODE				BIT(0)
+#define DISP_REG_OD_SIZE			0x0030
+
+#define DISP_REG_UFO_START			0x0000
+#define UFO_BYPASS				BIT(2)
 
 struct mtk_ddp_comp_dev {
 	struct clk *clk;
@@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 #endif
 }
 
-static int mtk_ddp_clk_enable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	return clk_prepare_enable(priv->clk);
-}
-
-static void mtk_ddp_clk_disable(struct device *dev)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	clk_disable_unprepare(priv->clk);
-}
-
 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 			   unsigned int bpc, unsigned int cfg,
 			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
@@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 		return;
 
 	if (bpc >= MTK_MIN_BPC) {
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
-		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
+		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 			      DITHER_NEW_BIT_MODE,
-			      cmdq_reg, regs, DISP_DITHER_15);
+			      cmdq_reg, regs, DISP_REG_DITHER_15);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
-			      cmdq_reg, regs, DISP_DITHER_16);
+			      cmdq_reg, regs, DISP_REG_DITHER_16);
 		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
 	}
 }
 
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
-		    unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
-			      DISP_DITHERING, cmdq_pkt);
-}
-
-static void mtk_od_config(struct device *dev, unsigned int w,
-			  unsigned int h, unsigned int vrefresh,
-			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
-	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
-	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
-	mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
-}
-
-static void mtk_od_start(struct device *dev)
+static int mtk_ddp_clk_enable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(1, priv->regs + DISP_OD_EN);
+	return clk_prepare_enable(priv->clk);
 }
 
-static void mtk_ufoe_start(struct device *dev)
+static void mtk_ddp_clk_disable(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
+	clk_disable_unprepare(priv->clk);
 }
 
 static void mtk_aal_config(struct device *dev, unsigned int w,
@@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
 }
 
 static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
@@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(AAL_EN, priv->regs + DISP_AAL_EN);
+	writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_aal_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
 }
 
 static void mtk_dither_config(struct device *dev, unsigned int w,
@@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
-	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
-	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_SIZE);
+	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_DITHER_CFG);
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
 			      DITHER_ENGINE_EN, cmdq_pkt);
 }
 
@@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
+	writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
 }
 
 static void mtk_dither_stop(struct device *dev)
 {
 	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
-	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
+	writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
+}
+
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
+			   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
+			      DISP_DITHERING, cmdq_pkt);
+}
+
+static void mtk_od_config(struct device *dev, unsigned int w,
+			  unsigned int h, unsigned int vrefresh,
+			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
+	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
+	mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
+}
+
+static void mtk_od_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(1, priv->regs + DISP_REG_OD_EN);
+}
+
+static void mtk_ufoe_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
 static const struct mtk_ddp_comp_funcs ddp_aal = {
@@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 };
 
 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
+	[MTK_DISP_AAL] = "aal",
+	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_CCORR] = "ccorr",
+	[MTK_DISP_COLOR] = "color",
+	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MUTEX] = "mutex",
+	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
 	[MTK_DISP_OVL_2L] = "ovl-2l",
+	[MTK_DISP_PWM] = "pwm",
 	[MTK_DISP_RDMA] = "rdma",
-	[MTK_DISP_WDMA] = "wdma",
-	[MTK_DISP_COLOR] = "color",
-	[MTK_DISP_CCORR] = "ccorr",
-	[MTK_DISP_AAL] = "aal",
-	[MTK_DISP_GAMMA] = "gamma",
-	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_UFOE] = "ufoe",
-	[MTK_DSI] = "dsi",
+	[MTK_DISP_WDMA] = "wdma",
 	[MTK_DPI] = "dpi",
-	[MTK_DISP_PWM] = "pwm",
-	[MTK_DISP_MUTEX] = "mutex",
-	[MTK_DISP_OD] = "od",
-	[MTK_DISP_BLS] = "bls",
+	[MTK_DSI] = "dsi",
 };
 
 struct mtk_ddp_comp_match {
@@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
-	    type == MTK_DPI ||
-	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
-	    type == MTK_DISP_RDMA)
+	    type == MTK_DISP_RDMA ||
+	    type == MTK_DPI ||
+	    type == MTK_DSI)
 		return 0;
 
 	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..d317b944df66 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -18,22 +18,22 @@ struct mtk_plane_state;
 struct drm_crtc_state;
 
 enum mtk_ddp_comp_type {
-	MTK_DISP_OVL,
-	MTK_DISP_OVL_2L,
-	MTK_DISP_RDMA,
-	MTK_DISP_WDMA,
-	MTK_DISP_COLOR,
+	MTK_DISP_AAL,
+	MTK_DISP_BLS,
 	MTK_DISP_CCORR,
+	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
-	MTK_DISP_AAL,
 	MTK_DISP_GAMMA,
-	MTK_DISP_UFOE,
-	MTK_DSI,
-	MTK_DPI,
-	MTK_DISP_PWM,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-	MTK_DISP_BLS,
+	MTK_DISP_OVL,
+	MTK_DISP_OVL_2L,
+	MTK_DISP_PWM,
+	MTK_DISP_RDMA,
+	MTK_DISP_UFOE,
+	MTK_DISP_WDMA,
+	MTK_DPI,
+	MTK_DSI,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..a95dc1006b82 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
 };
 
 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
-	{ .compatible = "mediatek,mt2701-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8173-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl",
-	  .data = (void *)MTK_DISP_OVL },
-	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
-	  .data = (void *)MTK_DISP_OVL_2L },
-	{ .compatible = "mediatek,mt2701-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8183-disp-rdma",
-	  .data = (void *)MTK_DISP_RDMA },
-	{ .compatible = "mediatek,mt8173-disp-wdma",
-	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt8173-disp-aal",
+	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = (void *)MTK_DISP_CCORR },
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
-	{ .compatible = "mediatek,mt8173-disp-aal",
-	  .data = (void *)MTK_DISP_AAL},
+	{ .compatible = "mediatek,mt8183-disp-dither",
+	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
-	{ .compatible = "mediatek,mt8183-disp-dither",
-	  .data = (void *)MTK_DISP_DITHER },
-	{ .compatible = "mediatek,mt8173-disp-ufoe",
-	  .data = (void *)MTK_DISP_UFOE },
-	{ .compatible = "mediatek,mt2701-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8173-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt8183-dsi",
-	  .data = (void *)MTK_DSI },
-	{ .compatible = "mediatek,mt2701-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8173-dpi",
-	  .data = (void *)MTK_DPI },
-	{ .compatible = "mediatek,mt8183-dpi",
-	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8173-disp-od",
+	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8173-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
+	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
 	  .data = (void *)MTK_DISP_PWM },
-	{ .compatible = "mediatek,mt8173-disp-od",
-	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt2701-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8183-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8173-disp-ufoe",
+	  .data = (void *)MTK_DISP_UFOE },
+	{ .compatible = "mediatek,mt8173-disp-wdma",
+	  .data = (void *)MTK_DISP_WDMA },
+	{ .compatible = "mediatek,mt2701-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8173-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt8183-dpi",
+	  .data = (void *)MTK_DPI },
+	{ .compatible = "mediatek,mt2701-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8173-dsi",
+	  .data = (void *)MTK_DSI },
+	{ .compatible = "mediatek,mt8183-dsi",
+	  .data = (void *)MTK_DSI },
 	{ }
 };
 
@@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
-		    comp_type == MTK_DSI ||
-		    comp_type == MTK_DPI) {
+		    comp_type == MTK_DPI ||
+		    comp_type == MTK_DSI) {
 			dev_info(dev, "Adding component match for %pOF\n",
 				 node);
 			drm_of_component_match_add(dev, &match, compare_of,
-- 
2.18.0

[PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[jason-jh.lin]

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 328ee19f931e..24c7b004fe4d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -43,6 +43,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]	= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]	= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]	= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index d317b944df66..560be6bc9d0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[jason-jh.lin]

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 328ee19f931e..24c7b004fe4d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -43,6 +43,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]	= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]	= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]	= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index d317b944df66..560be6bc9d0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[jason-jh.lin]

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 328ee19f931e..24c7b004fe4d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -43,6 +43,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]	= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]	= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]	= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index d317b944df66..560be6bc9d0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0

[PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[jason-jh.lin]

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 6 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..538e0087a44c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
 mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..f407cd9d873e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..f3d262792054
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN			1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE			0
+#define FLD_SWAP_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE	6
+#define CFG_10_10_2PI_2PO_BUF_MODE	8
+#define FLD_CFG_MERGE_MODE		GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN			1
+#define PREULTRA_EN			1
+#define HALT_FOR_DVFS_EN		0
+#define FLD_ULTRA_EN			GENMASK(0, 0)
+#define FLD_PREULTRA_EN			GENMASK(4, 4)
+#define FLD_HALT_FOR_DVFS_EN		GENMASK(8, 8)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE			3
+#define FLD_BUFFER_MODE			GENMASK(1, 0)
+#define DISP_REG_MERGE_CFG_38		0x0a8
+#define FLD_VDE_BLOCK_ULTRA		GENMASK(0, 0)
+#define FLD_VALID_TH_BLOCK_ULTRA	GENMASK(4, 4)
+#define FLD_ULTRA_FIFO_VALID_TH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_39		0x0ac
+#define FLD_NVDE_FORCE_PREULTRA		GENMASK(8, 8)
+#define FLD_NVALID_TH_FORCE_PREULTRA	GENMASK(12, 12)
+#define FLD_PREULTRA_FIFO_VALID_TH	GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 600M pixel/sec */
+#define ULTRA_TH_LOW			(6 * 600)
+/* 8 us, 600M pixel/sec */
+#define ULTRA_TH_HIGH			(8 * 600)
+#define FLD_ULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 600M pixel/sec */
+#define PREULTRA_TH_LOW			(8 * 600)
+/* 9 us, 600M pixel/sec */
+#define PREULTRA_TH_HIGH		(9 * 600)
+#define FLD_PREULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH		GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem *regs;
+	struct clk *clk;
+	struct clk *async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *handle)
+{
+	mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
+			   FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
+
+	mtk_ddp_write_mask(handle, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
+			   FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
+			   FLD_ULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
+			   FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
+			   FLD_PREULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, handle);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		pr_err("merge clk prepare enable failed\n");
+
+	if (priv->async_clk) {
+		ret = clk_prepare_enable(priv->async_clk);
+		if (ret)
+			pr_err("async clk prepare enable failed\n");
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	if (priv->async_clk)
+		clk_disable_unprepare(priv->async_clk);
+
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = of_clk_get(dev->of_node, 1);
+	if (IS_ERR(priv->async_clk)) {
+		ret = PTR_ERR(priv->async_clk);
+		dev_dbg(dev, "No merge async clock: %d\n", ret);
+		priv->async_clk = NULL;
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 560be6bc9d0e..b42a47c06956 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a95dc1006b82..5eb9c0a04447 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
 		if (comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..0fa417219a69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,6 +49,7 @@ struct mtk_drm_private {
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[jason-jh.lin]

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 6 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..538e0087a44c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
 mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..f407cd9d873e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..f3d262792054
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN			1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE			0
+#define FLD_SWAP_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE	6
+#define CFG_10_10_2PI_2PO_BUF_MODE	8
+#define FLD_CFG_MERGE_MODE		GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN			1
+#define PREULTRA_EN			1
+#define HALT_FOR_DVFS_EN		0
+#define FLD_ULTRA_EN			GENMASK(0, 0)
+#define FLD_PREULTRA_EN			GENMASK(4, 4)
+#define FLD_HALT_FOR_DVFS_EN		GENMASK(8, 8)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE			3
+#define FLD_BUFFER_MODE			GENMASK(1, 0)
+#define DISP_REG_MERGE_CFG_38		0x0a8
+#define FLD_VDE_BLOCK_ULTRA		GENMASK(0, 0)
+#define FLD_VALID_TH_BLOCK_ULTRA	GENMASK(4, 4)
+#define FLD_ULTRA_FIFO_VALID_TH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_39		0x0ac
+#define FLD_NVDE_FORCE_PREULTRA		GENMASK(8, 8)
+#define FLD_NVALID_TH_FORCE_PREULTRA	GENMASK(12, 12)
+#define FLD_PREULTRA_FIFO_VALID_TH	GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 600M pixel/sec */
+#define ULTRA_TH_LOW			(6 * 600)
+/* 8 us, 600M pixel/sec */
+#define ULTRA_TH_HIGH			(8 * 600)
+#define FLD_ULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 600M pixel/sec */
+#define PREULTRA_TH_LOW			(8 * 600)
+/* 9 us, 600M pixel/sec */
+#define PREULTRA_TH_HIGH		(9 * 600)
+#define FLD_PREULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH		GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem *regs;
+	struct clk *clk;
+	struct clk *async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *handle)
+{
+	mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
+			   FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
+
+	mtk_ddp_write_mask(handle, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
+			   FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
+			   FLD_ULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
+			   FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
+			   FLD_PREULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, handle);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		pr_err("merge clk prepare enable failed\n");
+
+	if (priv->async_clk) {
+		ret = clk_prepare_enable(priv->async_clk);
+		if (ret)
+			pr_err("async clk prepare enable failed\n");
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	if (priv->async_clk)
+		clk_disable_unprepare(priv->async_clk);
+
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = of_clk_get(dev->of_node, 1);
+	if (IS_ERR(priv->async_clk)) {
+		ret = PTR_ERR(priv->async_clk);
+		dev_dbg(dev, "No merge async clock: %d\n", ret);
+		priv->async_clk = NULL;
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 560be6bc9d0e..b42a47c06956 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a95dc1006b82..5eb9c0a04447 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
 		if (comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..0fa417219a69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,6 +49,7 @@ struct mtk_drm_private {
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[jason-jh.lin]

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 6 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..538e0087a44c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
 mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..f407cd9d873e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..f3d262792054
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN			1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE			0
+#define FLD_SWAP_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE	6
+#define CFG_10_10_2PI_2PO_BUF_MODE	8
+#define FLD_CFG_MERGE_MODE		GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN			1
+#define PREULTRA_EN			1
+#define HALT_FOR_DVFS_EN		0
+#define FLD_ULTRA_EN			GENMASK(0, 0)
+#define FLD_PREULTRA_EN			GENMASK(4, 4)
+#define FLD_HALT_FOR_DVFS_EN		GENMASK(8, 8)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE			3
+#define FLD_BUFFER_MODE			GENMASK(1, 0)
+#define DISP_REG_MERGE_CFG_38		0x0a8
+#define FLD_VDE_BLOCK_ULTRA		GENMASK(0, 0)
+#define FLD_VALID_TH_BLOCK_ULTRA	GENMASK(4, 4)
+#define FLD_ULTRA_FIFO_VALID_TH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_39		0x0ac
+#define FLD_NVDE_FORCE_PREULTRA		GENMASK(8, 8)
+#define FLD_NVALID_TH_FORCE_PREULTRA	GENMASK(12, 12)
+#define FLD_PREULTRA_FIFO_VALID_TH	GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 600M pixel/sec */
+#define ULTRA_TH_LOW			(6 * 600)
+/* 8 us, 600M pixel/sec */
+#define ULTRA_TH_HIGH			(8 * 600)
+#define FLD_ULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH		GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 600M pixel/sec */
+#define PREULTRA_TH_LOW			(8 * 600)
+/* 9 us, 600M pixel/sec */
+#define PREULTRA_TH_HIGH		(9 * 600)
+#define FLD_PREULTRA_TH_LOW		GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH		GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem *regs;
+	struct clk *clk;
+	struct clk *async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *handle)
+{
+	mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
+			   FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
+
+	mtk_ddp_write_mask(handle, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
+			   FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
+			   FLD_ULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, 0,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
+			   FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
+			   FLD_PREULTRA_FIFO_VALID_TH);
+
+	mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, handle);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		pr_err("merge clk prepare enable failed\n");
+
+	if (priv->async_clk) {
+		ret = clk_prepare_enable(priv->async_clk);
+		if (ret)
+			pr_err("async clk prepare enable failed\n");
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	if (priv->async_clk)
+		clk_disable_unprepare(priv->async_clk);
+
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = of_clk_get(dev->of_node, 1);
+	if (IS_ERR(priv->async_clk)) {
+		ret = PTR_ERR(priv->async_clk);
+		dev_dbg(dev, "No merge async clock: %d\n", ret);
+		priv->async_clk = NULL;
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 560be6bc9d0e..b42a47c06956 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a95dc1006b82..5eb9c0a04447 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
 		if (comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..0fa417219a69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,6 +49,7 @@ struct mtk_drm_private {
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0

[PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[jason-jh.lin]

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5eb9c0a04447..9aebf73144c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0
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[PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[jason-jh.lin]

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5eb9c0a04447..9aebf73144c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0
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[PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[jason-jh.lin]

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]

[1] dt-bindings: mediatek: display: add mt8195 SoC binding
https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5eb9c0a04447..9aebf73144c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0

Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Matthias Brugger]

Hi Jason,

On 05/08/2021 22:52, jason-jh.lin wrote:
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
> 

I'd like to see the implementation of vdosys1 as well, to better understand why
we need two compatibles.

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
> 
> [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/

Please add the binding description to this series.

> ---
>  drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
>  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
>  3 files changed, 116 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..9339a786ec5d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN					0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN					0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT					0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0

Please update the struct to the new version that includes a mask field.

Regards,
Matthias

Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Matthias Brugger]

Hi Jason,

On 05/08/2021 22:52, jason-jh.lin wrote:
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
> 

I'd like to see the implementation of vdosys1 as well, to better understand why
we need two compatibles.

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
> 
> [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/

Please add the binding description to this series.

> ---
>  drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
>  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
>  3 files changed, 116 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..9339a786ec5d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN					0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN					0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT					0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0

Please update the struct to the new version that includes a mask field.

Regards,
Matthias

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Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Matthias Brugger]

Hi Jason,

On 05/08/2021 22:52, jason-jh.lin wrote:
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
> 

I'd like to see the implementation of vdosys1 as well, to better understand why
we need two compatibles.

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
> 
> [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/

Please add the binding description to this series.

> ---
>  drivers/soc/mediatek/mt8195-mmsys.h    | 96 ++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
>  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
>  3 files changed, 116 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..9339a786ec5d
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN					0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN					0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT					0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			(1 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> +	{
> +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> +		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0

Please update the struct to the new version that includes a mask field.

Regards,
Matthias

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Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
>  2 files changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 328ee19f931e..24c7b004fe4d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -43,6 +43,12 @@
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                 BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_BYPASS                             BIT(4)
> +#define DSC_UFOE_SEL                           BIT(16)
> +
>  #define DISP_REG_OD_EN                         0x0000
>  #define DISP_REG_OD_CFG                                0x0020
>  #define OD_RELAYMODE                           BIT(0)
> @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
>                               DISP_DITHERING, cmdq_pkt);
>  }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> +                          unsigned int h, unsigned int vrefresh,
> +                          unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
>  static void mtk_od_config(struct device *dev, unsigned int w,
>                           unsigned int h, unsigned int vrefresh,
>                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
>         .stop = mtk_dpi_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .clk_enable = mtk_ddp_clk_enable,
> +       .clk_disable = mtk_ddp_clk_disable,
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_dsi = {
>         .start = mtk_dsi_ddp_start,
>         .stop = mtk_dsi_ddp_stop,
> @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
>         .stop = mtk_gamma_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};

Move the merge modification to the patch of merge.

> +
>  static const struct mtk_ddp_comp_funcs ddp_od = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_CCORR] = "ccorr",
>         [MTK_DISP_COLOR] = "color",
>         [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_DSC] = "dsc",
>         [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MERGE] = "merge",

Ditto.

>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
> @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
>         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi },
>         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi },
>         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi },
>         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi },
>         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi },
>         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },

Ditto.

>         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
>         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
>         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl },
> @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_MERGE ||

Ditto.

Regards,
Chun-Kuang.

>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_CCORR,
>         MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> +       MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> --
> 2.18.0
>

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Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
>  2 files changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 328ee19f931e..24c7b004fe4d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -43,6 +43,12 @@
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                 BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_BYPASS                             BIT(4)
> +#define DSC_UFOE_SEL                           BIT(16)
> +
>  #define DISP_REG_OD_EN                         0x0000
>  #define DISP_REG_OD_CFG                                0x0020
>  #define OD_RELAYMODE                           BIT(0)
> @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
>                               DISP_DITHERING, cmdq_pkt);
>  }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> +                          unsigned int h, unsigned int vrefresh,
> +                          unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
>  static void mtk_od_config(struct device *dev, unsigned int w,
>                           unsigned int h, unsigned int vrefresh,
>                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
>         .stop = mtk_dpi_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .clk_enable = mtk_ddp_clk_enable,
> +       .clk_disable = mtk_ddp_clk_disable,
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_dsi = {
>         .start = mtk_dsi_ddp_start,
>         .stop = mtk_dsi_ddp_stop,
> @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
>         .stop = mtk_gamma_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};

Move the merge modification to the patch of merge.

> +
>  static const struct mtk_ddp_comp_funcs ddp_od = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_CCORR] = "ccorr",
>         [MTK_DISP_COLOR] = "color",
>         [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_DSC] = "dsc",
>         [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MERGE] = "merge",

Ditto.

>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
> @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
>         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi },
>         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi },
>         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi },
>         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi },
>         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi },
>         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },

Ditto.

>         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
>         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
>         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl },
> @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_MERGE ||

Ditto.

Regards,
Chun-Kuang.

>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_CCORR,
>         MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> +       MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> --
> 2.18.0
>

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Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
>  2 files changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 328ee19f931e..24c7b004fe4d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -43,6 +43,12 @@
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
>
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                 BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_BYPASS                             BIT(4)
> +#define DSC_UFOE_SEL                           BIT(16)
> +
>  #define DISP_REG_OD_EN                         0x0000
>  #define DISP_REG_OD_CFG                                0x0020
>  #define OD_RELAYMODE                           BIT(0)
> @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
>                               DISP_DITHERING, cmdq_pkt);
>  }
>
> +static void mtk_dsc_config(struct device *dev, unsigned int w,
> +                          unsigned int h, unsigned int vrefresh,
> +                          unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> +}
> +
> +static void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> +}
> +
>  static void mtk_od_config(struct device *dev, unsigned int w,
>                           unsigned int h, unsigned int vrefresh,
>                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
>         .stop = mtk_dpi_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .clk_enable = mtk_ddp_clk_enable,
> +       .clk_disable = mtk_ddp_clk_disable,
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_dsi = {
>         .start = mtk_dsi_ddp_start,
>         .stop = mtk_dsi_ddp_stop,
> @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
>         .stop = mtk_gamma_stop,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};

Move the merge modification to the patch of merge.

> +
>  static const struct mtk_ddp_comp_funcs ddp_od = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -333,7 +384,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_CCORR] = "ccorr",
>         [MTK_DISP_COLOR] = "color",
>         [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_DSC] = "dsc",
>         [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MERGE] = "merge",

Ditto.

>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
> @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
>         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi },
>         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi },
>         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi },
>         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi },
>         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi },
>         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },

Ditto.

>         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
>         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
>         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl },
> @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_MERGE ||

Ditto.

Regards,
Chun-Kuang.

>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d317b944df66..560be6bc9d0e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_CCORR,
>         MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> +       MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> --
> 2.18.0
>

Re: [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5eb9c0a04447..9aebf73144c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,
> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8173-disp-od",
>           .data = (void *)MTK_DISP_OD },
>         { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

Re: [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5eb9c0a04447..9aebf73144c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,
> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8173-disp-od",
>           .data = (void *)MTK_DISP_OD },
>         { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

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Re: [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5eb9c0a04447..9aebf73144c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,
> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8173-disp-od",
>           .data = (void *)MTK_DISP_OD },
>         { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

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Re: [PATCH v6 7/7] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5eb9c0a04447..9aebf73144c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,
> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8173-disp-od",
>           .data = (void *)MTK_DISP_OD },
>         { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  6 files changed, 277 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..538e0087a44c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
>  mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_color.o \
>                   mtk_disp_gamma.o \
> +                 mtk_disp_merge.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
>                   mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..f407cd9d873e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
>  void mtk_gamma_start(struct device *dev);
>  void mtk_gamma_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +                     unsigned int height, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  void mtk_ovl_bgclr_in_on(struct device *dev);
>  void mtk_ovl_bgclr_in_off(struct device *dev);
>  void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..f3d262792054
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL            0x000
> +#define MERGE_EN                       1

One more indent for the bitwise value.

> +#define DISP_REG_MERGE_CFG_0           0x010
> +#define DISP_REG_MERGE_CFG_4           0x020
> +#define DISP_REG_MERGE_CFG_10          0x038
> +/* no swap */
> +#define SWAP_MODE                      0
> +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_12          0x040
> +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_24          0x070
> +#define DISP_REG_MERGE_CFG_25          0x074
> +#define DISP_REG_MERGE_CFG_36          0x0a0
> +#define ULTRA_EN                       1
> +#define PREULTRA_EN                    1
> +#define HALT_FOR_DVFS_EN               0
> +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> +#define DISP_REG_MERGE_CFG_37          0x0a4
> +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> +#define BUFFER_MODE                    3
> +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> +#define DISP_REG_MERGE_CFG_38          0x0a8
> +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_39          0x0ac
> +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_40          0x0b0
> +/* 6 us, 600M pixel/sec */
> +#define ULTRA_TH_LOW                   (6 * 600)
> +/* 8 us, 600M pixel/sec */
> +#define ULTRA_TH_HIGH                  (8 * 600)
> +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_41          0x0b4
> +/* 8 us, 600M pixel/sec */
> +#define PREULTRA_TH_LOW                        (8 * 600)
> +/* 9 us, 600M pixel/sec */

Add comment that "6 us ~ 9us is experience value and max mmsys clock
frequency is 594MHz", and I think you should use 594 instead of 600.

Regards,
Chun-Kuang.

> +#define PREULTRA_TH_HIGH               (9 * 600)
> +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> +
> +struct mtk_disp_merge {
> +       void __iomem *regs;
> +       struct clk *clk;
> +       struct clk *async_clk;
> +       struct cmdq_client_reg          cmdq_reg;
> +       bool                            fifo_en;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> +                                  struct cmdq_pkt *handle)
> +{
> +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
> +                          FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
> +
> +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
> +                          FLD_BUFFER_MODE);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
> +                          FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
> +                          FLD_ULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
> +                          FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
> +                          FLD_PREULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
> +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> +
> +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
> +                          FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +                     unsigned int h, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> +
> +       if (!h || !w) {
> +               dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> +               return;
> +       }
> +
> +       if (priv->fifo_en) {
> +               mtk_merge_fifo_setting(priv, handle);
> +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +       }
> +
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_0);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_4);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_24);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_25);
> +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +       int ret = 0;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       ret = clk_prepare_enable(priv->clk);
> +       if (ret)
> +               pr_err("merge clk prepare enable failed\n");
> +
> +       if (priv->async_clk) {
> +               ret = clk_prepare_enable(priv->async_clk);
> +               if (ret)
> +                       pr_err("async clk prepare enable failed\n");
> +       }
> +
> +       return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       if (priv->async_clk)
> +               clk_disable_unprepare(priv->async_clk);
> +
> +       clk_disable_unprepare(priv->clk);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +                              void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +                                 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +       .bind   = mtk_disp_merge_bind,
> +       .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_merge *priv;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap merge\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get merge clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       priv->async_clk = of_clk_get(dev->of_node, 1);
> +       if (IS_ERR(priv->async_clk)) {
> +               ret = PTR_ERR(priv->async_clk);
> +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> +               priv->async_clk = NULL;
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       priv->fifo_en = of_property_read_bool(dev->of_node,
> +                                             "mediatek,merge-fifo-en");
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> +       if (ret != 0)
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-merge", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +       .probe = mtk_disp_merge_probe,
> +       .remove = mtk_disp_merge_remove,
> +       .driver = {
> +               .name = "mediatek-disp-merge",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_merge_driver_dt_match,
> +       },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 560be6bc9d0e..b42a47c06956 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_DITHER,
>         MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
> +       MTK_DISP_MERGE,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
>         MTK_DISP_OVL,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index a95dc1006b82..5eb9c0a04447 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                 private->comp_node[comp_id] = of_node_get(node);
>
>                 /*
> -                * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
> +                * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
>                  * blocks have separate component platform drivers and initialize their own
>                  * DDP component structure. The others are initialized here.
>                  */
>                 if (comp_type == MTK_DISP_CCORR ||
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
> +                   comp_type == MTK_DISP_MERGE ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_ccorr_driver,
>         &mtk_disp_color_driver,
>         &mtk_disp_gamma_driver,
> +       &mtk_disp_merge_driver,
>         &mtk_disp_ovl_driver,
>         &mtk_disp_rdma_driver,
>         &mtk_dpi_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..0fa417219a69 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -49,6 +49,7 @@ struct mtk_drm_private {
>  extern struct platform_driver mtk_disp_ccorr_driver;
>  extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>

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Linux-mediatek@lists.infradead.org
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Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  6 files changed, 277 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..538e0087a44c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
>  mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_color.o \
>                   mtk_disp_gamma.o \
> +                 mtk_disp_merge.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
>                   mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..f407cd9d873e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
>  void mtk_gamma_start(struct device *dev);
>  void mtk_gamma_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +                     unsigned int height, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  void mtk_ovl_bgclr_in_on(struct device *dev);
>  void mtk_ovl_bgclr_in_off(struct device *dev);
>  void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..f3d262792054
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL            0x000
> +#define MERGE_EN                       1

One more indent for the bitwise value.

> +#define DISP_REG_MERGE_CFG_0           0x010
> +#define DISP_REG_MERGE_CFG_4           0x020
> +#define DISP_REG_MERGE_CFG_10          0x038
> +/* no swap */
> +#define SWAP_MODE                      0
> +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_12          0x040
> +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_24          0x070
> +#define DISP_REG_MERGE_CFG_25          0x074
> +#define DISP_REG_MERGE_CFG_36          0x0a0
> +#define ULTRA_EN                       1
> +#define PREULTRA_EN                    1
> +#define HALT_FOR_DVFS_EN               0
> +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> +#define DISP_REG_MERGE_CFG_37          0x0a4
> +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> +#define BUFFER_MODE                    3
> +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> +#define DISP_REG_MERGE_CFG_38          0x0a8
> +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_39          0x0ac
> +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_40          0x0b0
> +/* 6 us, 600M pixel/sec */
> +#define ULTRA_TH_LOW                   (6 * 600)
> +/* 8 us, 600M pixel/sec */
> +#define ULTRA_TH_HIGH                  (8 * 600)
> +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_41          0x0b4
> +/* 8 us, 600M pixel/sec */
> +#define PREULTRA_TH_LOW                        (8 * 600)
> +/* 9 us, 600M pixel/sec */

Add comment that "6 us ~ 9us is experience value and max mmsys clock
frequency is 594MHz", and I think you should use 594 instead of 600.

Regards,
Chun-Kuang.

> +#define PREULTRA_TH_HIGH               (9 * 600)
> +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> +
> +struct mtk_disp_merge {
> +       void __iomem *regs;
> +       struct clk *clk;
> +       struct clk *async_clk;
> +       struct cmdq_client_reg          cmdq_reg;
> +       bool                            fifo_en;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> +                                  struct cmdq_pkt *handle)
> +{
> +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
> +                          FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
> +
> +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
> +                          FLD_BUFFER_MODE);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
> +                          FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
> +                          FLD_ULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
> +                          FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
> +                          FLD_PREULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
> +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> +
> +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
> +                          FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +                     unsigned int h, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> +
> +       if (!h || !w) {
> +               dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> +               return;
> +       }
> +
> +       if (priv->fifo_en) {
> +               mtk_merge_fifo_setting(priv, handle);
> +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +       }
> +
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_0);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_4);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_24);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_25);
> +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +       int ret = 0;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       ret = clk_prepare_enable(priv->clk);
> +       if (ret)
> +               pr_err("merge clk prepare enable failed\n");
> +
> +       if (priv->async_clk) {
> +               ret = clk_prepare_enable(priv->async_clk);
> +               if (ret)
> +                       pr_err("async clk prepare enable failed\n");
> +       }
> +
> +       return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       if (priv->async_clk)
> +               clk_disable_unprepare(priv->async_clk);
> +
> +       clk_disable_unprepare(priv->clk);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +                              void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +                                 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +       .bind   = mtk_disp_merge_bind,
> +       .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_merge *priv;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap merge\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get merge clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       priv->async_clk = of_clk_get(dev->of_node, 1);
> +       if (IS_ERR(priv->async_clk)) {
> +               ret = PTR_ERR(priv->async_clk);
> +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> +               priv->async_clk = NULL;
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       priv->fifo_en = of_property_read_bool(dev->of_node,
> +                                             "mediatek,merge-fifo-en");
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> +       if (ret != 0)
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-merge", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +       .probe = mtk_disp_merge_probe,
> +       .remove = mtk_disp_merge_remove,
> +       .driver = {
> +               .name = "mediatek-disp-merge",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_merge_driver_dt_match,
> +       },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 560be6bc9d0e..b42a47c06956 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_DITHER,
>         MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
> +       MTK_DISP_MERGE,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
>         MTK_DISP_OVL,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index a95dc1006b82..5eb9c0a04447 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                 private->comp_node[comp_id] = of_node_get(node);
>
>                 /*
> -                * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
> +                * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
>                  * blocks have separate component platform drivers and initialize their own
>                  * DDP component structure. The others are initialized here.
>                  */
>                 if (comp_type == MTK_DISP_CCORR ||
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
> +                   comp_type == MTK_DISP_MERGE ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_ccorr_driver,
>         &mtk_disp_color_driver,
>         &mtk_disp_gamma_driver,
> +       &mtk_disp_merge_driver,
>         &mtk_disp_ovl_driver,
>         &mtk_disp_rdma_driver,
>         &mtk_dpi_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..0fa417219a69 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -49,6 +49,7 @@ struct mtk_drm_private {
>  extern struct platform_driver mtk_disp_ccorr_driver;
>  extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>

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Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> Add MERGE engine file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  6 files changed, 277 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..538e0087a44c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
>  mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_color.o \
>                   mtk_disp_gamma.o \
> +                 mtk_disp_merge.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
>                   mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..f407cd9d873e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
>  void mtk_gamma_start(struct device *dev);
>  void mtk_gamma_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +                     unsigned int height, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  void mtk_ovl_bgclr_in_on(struct device *dev);
>  void mtk_ovl_bgclr_in_off(struct device *dev);
>  void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..f3d262792054
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL            0x000
> +#define MERGE_EN                       1

One more indent for the bitwise value.

> +#define DISP_REG_MERGE_CFG_0           0x010
> +#define DISP_REG_MERGE_CFG_4           0x020
> +#define DISP_REG_MERGE_CFG_10          0x038
> +/* no swap */
> +#define SWAP_MODE                      0
> +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_12          0x040
> +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> +#define DISP_REG_MERGE_CFG_24          0x070
> +#define DISP_REG_MERGE_CFG_25          0x074
> +#define DISP_REG_MERGE_CFG_36          0x0a0
> +#define ULTRA_EN                       1
> +#define PREULTRA_EN                    1
> +#define HALT_FOR_DVFS_EN               0
> +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> +#define DISP_REG_MERGE_CFG_37          0x0a4
> +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> +#define BUFFER_MODE                    3
> +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> +#define DISP_REG_MERGE_CFG_38          0x0a8
> +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_39          0x0ac
> +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_40          0x0b0
> +/* 6 us, 600M pixel/sec */
> +#define ULTRA_TH_LOW                   (6 * 600)
> +/* 8 us, 600M pixel/sec */
> +#define ULTRA_TH_HIGH                  (8 * 600)
> +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> +#define DISP_REG_MERGE_CFG_41          0x0b4
> +/* 8 us, 600M pixel/sec */
> +#define PREULTRA_TH_LOW                        (8 * 600)
> +/* 9 us, 600M pixel/sec */

Add comment that "6 us ~ 9us is experience value and max mmsys clock
frequency is 594MHz", and I think you should use 594 instead of 600.

Regards,
Chun-Kuang.

> +#define PREULTRA_TH_HIGH               (9 * 600)
> +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> +
> +struct mtk_disp_merge {
> +       void __iomem *regs;
> +       struct clk *clk;
> +       struct clk *async_clk;
> +       struct cmdq_client_reg          cmdq_reg;
> +       bool                            fifo_en;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> +}
> +
> +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> +                                  struct cmdq_pkt *handle)
> +{
> +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 | HALT_FOR_DVFS_EN << 8,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36,
> +                          FLD_ULTRA_EN | FLD_PREULTRA_EN | FLD_HALT_FOR_DVFS_EN);
> +
> +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
> +                          FLD_BUFFER_MODE);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_38,
> +                          FLD_VDE_BLOCK_ULTRA | FLD_VALID_TH_BLOCK_ULTRA |
> +                          FLD_ULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, 0,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_39,
> +                          FLD_NVDE_FORCE_PREULTRA | FLD_NVALID_TH_FORCE_PREULTRA |
> +                          FLD_PREULTRA_FIFO_VALID_TH);
> +
> +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
> +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> +
> +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
> +                          &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
> +                          FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +                     unsigned int h, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> +
> +       if (!h || !w) {
> +               dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> +               return;
> +       }
> +
> +       if (priv->fifo_en) {
> +               mtk_merge_fifo_setting(priv, handle);
> +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +       }
> +
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_0);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_4);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_24);
> +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CFG_25);
> +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +       int ret = 0;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       ret = clk_prepare_enable(priv->clk);
> +       if (ret)
> +               pr_err("merge clk prepare enable failed\n");
> +
> +       if (priv->async_clk) {
> +               ret = clk_prepare_enable(priv->async_clk);
> +               if (ret)
> +                       pr_err("async clk prepare enable failed\n");
> +       }
> +
> +       return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       if (priv->async_clk)
> +               clk_disable_unprepare(priv->async_clk);
> +
> +       clk_disable_unprepare(priv->clk);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +                              void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +                                 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +       .bind   = mtk_disp_merge_bind,
> +       .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_merge *priv;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap merge\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get merge clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       priv->async_clk = of_clk_get(dev->of_node, 1);
> +       if (IS_ERR(priv->async_clk)) {
> +               ret = PTR_ERR(priv->async_clk);
> +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> +               priv->async_clk = NULL;
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       priv->fifo_en = of_property_read_bool(dev->of_node,
> +                                             "mediatek,merge-fifo-en");
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> +       if (ret != 0)
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-merge", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +       .probe = mtk_disp_merge_probe,
> +       .remove = mtk_disp_merge_remove,
> +       .driver = {
> +               .name = "mediatek-disp-merge",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_merge_driver_dt_match,
> +       },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 560be6bc9d0e..b42a47c06956 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_DITHER,
>         MTK_DISP_DSC,
>         MTK_DISP_GAMMA,
> +       MTK_DISP_MERGE,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
>         MTK_DISP_OVL,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index a95dc1006b82..5eb9c0a04447 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                 private->comp_node[comp_id] = of_node_get(node);
>
>                 /*
> -                * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
> +                * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
>                  * blocks have separate component platform drivers and initialize their own
>                  * DDP component structure. The others are initialized here.
>                  */
>                 if (comp_type == MTK_DISP_CCORR ||
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
> +                   comp_type == MTK_DISP_MERGE ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -639,6 +640,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_ccorr_driver,
>         &mtk_disp_color_driver,
>         &mtk_disp_gamma_driver,
> +       &mtk_disp_merge_driver,
>         &mtk_disp_ovl_driver,
>         &mtk_disp_rdma_driver,
>         &mtk_dpi_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..0fa417219a69 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -49,6 +49,7 @@ struct mtk_drm_private {
>  extern struct platform_driver mtk_disp_ccorr_driver;
>  extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>

Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> 1. Adjust to the alphabetic order for the define, function, struct
>    and array in mediatek-drm driver
> 2. Remove the unsed define in mtk_drm_ddp_comp.c

Separate the 2nd part to another patch.

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
>  3 files changed, 133 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..328ee19f931e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,50 +20,36 @@
>  #include "mtk_drm_ddp_comp.h"
>  #include "mtk_drm_crtc.h"
>
> -#define DISP_OD_EN                             0x0000
> -#define DISP_OD_INTEN                          0x0008
> -#define DISP_OD_INTSTA                         0x000c
> -#define DISP_OD_CFG                            0x0020
> -#define DISP_OD_SIZE                           0x0030
> -#define DISP_DITHER_5                          0x0114
> -#define DISP_DITHER_7                          0x011c
> -#define DISP_DITHER_15                         0x013c
> -#define DISP_DITHER_16                         0x0140
> -
> -#define DISP_REG_UFO_START                     0x0000
> -
> -#define DISP_AAL_EN                            0x0000
> -#define DISP_AAL_SIZE                          0x0030
> +#define DISP_REG_AAL_EN                                0x0000
> +#define AAL_EN                                 BIT(0)
> +#define DISP_REG_AAL_SIZE                      0x0030
>
> -#define DISP_DITHER_EN                         0x0000
> +#define DISP_REG_DITHER_EN                     0x0000

I think we should not change the register name just for alphabetic
order. We list the register in the order of its address.
If you have another reason to change register name, add another patch
to do this.

Regards,
Chun-Kuang.

>  #define DITHER_EN                              BIT(0)
> -#define DISP_DITHER_CFG                                0x0020
> +#define DISP_REG_DITHER_CFG                    0x0020
>  #define DITHER_RELAY_MODE                      BIT(0)
>  #define DITHER_ENGINE_EN                       BIT(1)
> -#define DISP_DITHER_SIZE                       0x0030
> -
> -#define LUT_10BIT_MASK                         0x03ff
> -
> -#define OD_RELAYMODE                           BIT(0)
> -
> -#define UFO_BYPASS                             BIT(2)
> -
> -#define AAL_EN                                 BIT(0)
> -
>  #define DISP_DITHERING                         BIT(2)
> +#define DISP_REG_DITHER_SIZE                   0x0030
> +#define DISP_REG_DITHER_5                      0x0114
> +#define DISP_REG_DITHER_7                      0x011c
> +#define DISP_REG_DITHER_15                     0x013c
>  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
>  #define DITHER_NEW_BIT_MODE                    BIT(0)
> +#define DISP_REG_DITHER_16                     0x0140
>  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> +
> +#define DISP_REG_OD_EN                         0x0000
> +#define DISP_REG_OD_CFG                                0x0020
> +#define OD_RELAYMODE                           BIT(0)
> +#define DISP_REG_OD_SIZE                       0x0030
> +
> +#define DISP_REG_UFO_START                     0x0000
> +#define UFO_BYPASS                             BIT(2)
>
>  struct mtk_ddp_comp_dev {
>         struct clk *clk;
> @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  #endif
>  }
>
> -static int mtk_ddp_clk_enable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       return clk_prepare_enable(priv->clk);
> -}
> -
> -static void mtk_ddp_clk_disable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       clk_disable_unprepare(priv->clk);
> -}
> -
>  void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                            unsigned int bpc, unsigned int cfg,
>                            unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                 return;
>
>         if (bpc >= MTK_MIN_BPC) {
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_NEW_BIT_MODE,
> -                             cmdq_reg, regs, DISP_DITHER_15);
> +                             cmdq_reg, regs, DISP_REG_DITHER_15);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> -                             cmdq_reg, regs, DISP_DITHER_16);
> +                             cmdq_reg, regs, DISP_REG_DITHER_16);
>                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
>         }
>  }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> -                             DISP_DITHERING, cmdq_pkt);
> -}
> -
> -static void mtk_od_config(struct device *dev, unsigned int w,
> -                         unsigned int h, unsigned int vrefresh,
> -                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
> -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
> -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> -}
> -
> -static void mtk_od_start(struct device *dev)
> +static int mtk_ddp_clk_enable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(1, priv->regs + DISP_OD_EN);
> +       return clk_prepare_enable(priv->clk);
>  }
>
> -static void mtk_ufoe_start(struct device *dev)
> +static void mtk_ddp_clk_disable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> +       clk_disable_unprepare(priv->clk);
>  }
>
>  static void mtk_aal_config(struct device *dev, unsigned int w,
> @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
>  }
>
>  static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_aal_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_dither_config(struct device *dev, unsigned int w,
> @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
> +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_SIZE);
> +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_CFG);
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
>                               DITHER_ENGINE_EN, cmdq_pkt);
>  }
>
> @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
>  }
>
>  static void mtk_dither_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> +}
> +
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> +                          unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> +                             DISP_DITHERING, cmdq_pkt);
> +}
> +
> +static void mtk_od_config(struct device *dev, unsigned int w,
> +                         unsigned int h, unsigned int vrefresh,
> +                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> +}
> +
> +static void mtk_od_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(1, priv->regs + DISP_REG_OD_EN);
> +}
> +
> +static void mtk_ufoe_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
>  }
>
>  static const struct mtk_ddp_comp_funcs ddp_aal = {
> @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>  };
>
>  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> +       [MTK_DISP_AAL] = "aal",
> +       [MTK_DISP_BLS] = "bls",
> +       [MTK_DISP_CCORR] = "ccorr",
> +       [MTK_DISP_COLOR] = "color",
> +       [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MUTEX] = "mutex",
> +       [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
>         [MTK_DISP_OVL_2L] = "ovl-2l",
> +       [MTK_DISP_PWM] = "pwm",
>         [MTK_DISP_RDMA] = "rdma",
> -       [MTK_DISP_WDMA] = "wdma",
> -       [MTK_DISP_COLOR] = "color",
> -       [MTK_DISP_CCORR] = "ccorr",
> -       [MTK_DISP_AAL] = "aal",
> -       [MTK_DISP_GAMMA] = "gamma",
> -       [MTK_DISP_DITHER] = "dither",
>         [MTK_DISP_UFOE] = "ufoe",
> -       [MTK_DSI] = "dsi",
> +       [MTK_DISP_WDMA] = "wdma",
>         [MTK_DPI] = "dpi",
> -       [MTK_DISP_PWM] = "pwm",
> -       [MTK_DISP_MUTEX] = "mutex",
> -       [MTK_DISP_OD] = "od",
> -       [MTK_DISP_BLS] = "bls",
> +       [MTK_DSI] = "dsi",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> -           type == MTK_DPI ||
> -           type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> -           type == MTK_DISP_RDMA)
> +           type == MTK_DISP_RDMA ||
> +           type == MTK_DPI ||
> +           type == MTK_DSI)
>                 return 0;
>
>         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..d317b944df66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -18,22 +18,22 @@ struct mtk_plane_state;
>  struct drm_crtc_state;
>
>  enum mtk_ddp_comp_type {
> -       MTK_DISP_OVL,
> -       MTK_DISP_OVL_2L,
> -       MTK_DISP_RDMA,
> -       MTK_DISP_WDMA,
> -       MTK_DISP_COLOR,
> +       MTK_DISP_AAL,
> +       MTK_DISP_BLS,
>         MTK_DISP_CCORR,
> +       MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> -       MTK_DISP_AAL,
>         MTK_DISP_GAMMA,
> -       MTK_DISP_UFOE,
> -       MTK_DSI,
> -       MTK_DPI,
> -       MTK_DISP_PWM,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> -       MTK_DISP_BLS,
> +       MTK_DISP_OVL,
> +       MTK_DISP_OVL_2L,
> +       MTK_DISP_PWM,
> +       MTK_DISP_RDMA,
> +       MTK_DISP_UFOE,
> +       MTK_DISP_WDMA,
> +       MTK_DPI,
> +       MTK_DSI,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..a95dc1006b82 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
>  };
>
>  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> -       { .compatible = "mediatek,mt2701-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8173-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> -         .data = (void *)MTK_DISP_OVL_2L },
> -       { .compatible = "mediatek,mt2701-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8183-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-wdma",
> -         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt8173-disp-aal",
> +         .data = (void *)MTK_DISP_AAL},
>         { .compatible = "mediatek,mt8183-disp-ccorr",
>           .data = (void *)MTK_DISP_CCORR },
>         { .compatible = "mediatek,mt2701-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8173-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
> -       { .compatible = "mediatek,mt8173-disp-aal",
> -         .data = (void *)MTK_DISP_AAL},
> +       { .compatible = "mediatek,mt8183-disp-dither",
> +         .data = (void *)MTK_DISP_DITHER },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> -       { .compatible = "mediatek,mt8183-disp-dither",
> -         .data = (void *)MTK_DISP_DITHER },
> -       { .compatible = "mediatek,mt8173-disp-ufoe",
> -         .data = (void *)MTK_DISP_UFOE },
> -       { .compatible = "mediatek,mt2701-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8173-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8183-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt2701-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8173-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8183-dpi",
> -         .data = (void *)MTK_DPI },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8173-disp-od",
> +         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8173-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> +         .data = (void *)MTK_DISP_OVL_2L },
>         { .compatible = "mediatek,mt2701-disp-pwm",
>           .data = (void *)MTK_DISP_BLS },
>         { .compatible = "mediatek,mt8173-disp-pwm",
>           .data = (void *)MTK_DISP_PWM },
> -       { .compatible = "mediatek,mt8173-disp-od",
> -         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8183-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-ufoe",
> +         .data = (void *)MTK_DISP_UFOE },
> +       { .compatible = "mediatek,mt8173-disp-wdma",
> +         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt2701-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8173-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8183-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt2701-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8173-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8183-dsi",
> +         .data = (void *)MTK_DSI },
>         { }
>  };
>
> @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> -                   comp_type == MTK_DSI ||
> -                   comp_type == MTK_DPI) {
> +                   comp_type == MTK_DPI ||
> +                   comp_type == MTK_DSI) {
>                         dev_info(dev, "Adding component match for %pOF\n",
>                                  node);
>                         drm_of_component_match_add(dev, &match, compare_of,
> --
> 2.18.0
>

_______________________________________________
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Linux-mediatek@lists.infradead.org
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Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> 1. Adjust to the alphabetic order for the define, function, struct
>    and array in mediatek-drm driver
> 2. Remove the unsed define in mtk_drm_ddp_comp.c

Separate the 2nd part to another patch.

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
>  3 files changed, 133 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..328ee19f931e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,50 +20,36 @@
>  #include "mtk_drm_ddp_comp.h"
>  #include "mtk_drm_crtc.h"
>
> -#define DISP_OD_EN                             0x0000
> -#define DISP_OD_INTEN                          0x0008
> -#define DISP_OD_INTSTA                         0x000c
> -#define DISP_OD_CFG                            0x0020
> -#define DISP_OD_SIZE                           0x0030
> -#define DISP_DITHER_5                          0x0114
> -#define DISP_DITHER_7                          0x011c
> -#define DISP_DITHER_15                         0x013c
> -#define DISP_DITHER_16                         0x0140
> -
> -#define DISP_REG_UFO_START                     0x0000
> -
> -#define DISP_AAL_EN                            0x0000
> -#define DISP_AAL_SIZE                          0x0030
> +#define DISP_REG_AAL_EN                                0x0000
> +#define AAL_EN                                 BIT(0)
> +#define DISP_REG_AAL_SIZE                      0x0030
>
> -#define DISP_DITHER_EN                         0x0000
> +#define DISP_REG_DITHER_EN                     0x0000

I think we should not change the register name just for alphabetic
order. We list the register in the order of its address.
If you have another reason to change register name, add another patch
to do this.

Regards,
Chun-Kuang.

>  #define DITHER_EN                              BIT(0)
> -#define DISP_DITHER_CFG                                0x0020
> +#define DISP_REG_DITHER_CFG                    0x0020
>  #define DITHER_RELAY_MODE                      BIT(0)
>  #define DITHER_ENGINE_EN                       BIT(1)
> -#define DISP_DITHER_SIZE                       0x0030
> -
> -#define LUT_10BIT_MASK                         0x03ff
> -
> -#define OD_RELAYMODE                           BIT(0)
> -
> -#define UFO_BYPASS                             BIT(2)
> -
> -#define AAL_EN                                 BIT(0)
> -
>  #define DISP_DITHERING                         BIT(2)
> +#define DISP_REG_DITHER_SIZE                   0x0030
> +#define DISP_REG_DITHER_5                      0x0114
> +#define DISP_REG_DITHER_7                      0x011c
> +#define DISP_REG_DITHER_15                     0x013c
>  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
>  #define DITHER_NEW_BIT_MODE                    BIT(0)
> +#define DISP_REG_DITHER_16                     0x0140
>  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> +
> +#define DISP_REG_OD_EN                         0x0000
> +#define DISP_REG_OD_CFG                                0x0020
> +#define OD_RELAYMODE                           BIT(0)
> +#define DISP_REG_OD_SIZE                       0x0030
> +
> +#define DISP_REG_UFO_START                     0x0000
> +#define UFO_BYPASS                             BIT(2)
>
>  struct mtk_ddp_comp_dev {
>         struct clk *clk;
> @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  #endif
>  }
>
> -static int mtk_ddp_clk_enable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       return clk_prepare_enable(priv->clk);
> -}
> -
> -static void mtk_ddp_clk_disable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       clk_disable_unprepare(priv->clk);
> -}
> -
>  void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                            unsigned int bpc, unsigned int cfg,
>                            unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                 return;
>
>         if (bpc >= MTK_MIN_BPC) {
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_NEW_BIT_MODE,
> -                             cmdq_reg, regs, DISP_DITHER_15);
> +                             cmdq_reg, regs, DISP_REG_DITHER_15);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> -                             cmdq_reg, regs, DISP_DITHER_16);
> +                             cmdq_reg, regs, DISP_REG_DITHER_16);
>                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
>         }
>  }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> -                             DISP_DITHERING, cmdq_pkt);
> -}
> -
> -static void mtk_od_config(struct device *dev, unsigned int w,
> -                         unsigned int h, unsigned int vrefresh,
> -                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
> -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
> -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> -}
> -
> -static void mtk_od_start(struct device *dev)
> +static int mtk_ddp_clk_enable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(1, priv->regs + DISP_OD_EN);
> +       return clk_prepare_enable(priv->clk);
>  }
>
> -static void mtk_ufoe_start(struct device *dev)
> +static void mtk_ddp_clk_disable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> +       clk_disable_unprepare(priv->clk);
>  }
>
>  static void mtk_aal_config(struct device *dev, unsigned int w,
> @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
>  }
>
>  static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_aal_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_dither_config(struct device *dev, unsigned int w,
> @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
> +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_SIZE);
> +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_CFG);
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
>                               DITHER_ENGINE_EN, cmdq_pkt);
>  }
>
> @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
>  }
>
>  static void mtk_dither_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> +}
> +
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> +                          unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> +                             DISP_DITHERING, cmdq_pkt);
> +}
> +
> +static void mtk_od_config(struct device *dev, unsigned int w,
> +                         unsigned int h, unsigned int vrefresh,
> +                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> +}
> +
> +static void mtk_od_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(1, priv->regs + DISP_REG_OD_EN);
> +}
> +
> +static void mtk_ufoe_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
>  }
>
>  static const struct mtk_ddp_comp_funcs ddp_aal = {
> @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>  };
>
>  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> +       [MTK_DISP_AAL] = "aal",
> +       [MTK_DISP_BLS] = "bls",
> +       [MTK_DISP_CCORR] = "ccorr",
> +       [MTK_DISP_COLOR] = "color",
> +       [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MUTEX] = "mutex",
> +       [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
>         [MTK_DISP_OVL_2L] = "ovl-2l",
> +       [MTK_DISP_PWM] = "pwm",
>         [MTK_DISP_RDMA] = "rdma",
> -       [MTK_DISP_WDMA] = "wdma",
> -       [MTK_DISP_COLOR] = "color",
> -       [MTK_DISP_CCORR] = "ccorr",
> -       [MTK_DISP_AAL] = "aal",
> -       [MTK_DISP_GAMMA] = "gamma",
> -       [MTK_DISP_DITHER] = "dither",
>         [MTK_DISP_UFOE] = "ufoe",
> -       [MTK_DSI] = "dsi",
> +       [MTK_DISP_WDMA] = "wdma",
>         [MTK_DPI] = "dpi",
> -       [MTK_DISP_PWM] = "pwm",
> -       [MTK_DISP_MUTEX] = "mutex",
> -       [MTK_DISP_OD] = "od",
> -       [MTK_DISP_BLS] = "bls",
> +       [MTK_DSI] = "dsi",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> -           type == MTK_DPI ||
> -           type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> -           type == MTK_DISP_RDMA)
> +           type == MTK_DISP_RDMA ||
> +           type == MTK_DPI ||
> +           type == MTK_DSI)
>                 return 0;
>
>         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..d317b944df66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -18,22 +18,22 @@ struct mtk_plane_state;
>  struct drm_crtc_state;
>
>  enum mtk_ddp_comp_type {
> -       MTK_DISP_OVL,
> -       MTK_DISP_OVL_2L,
> -       MTK_DISP_RDMA,
> -       MTK_DISP_WDMA,
> -       MTK_DISP_COLOR,
> +       MTK_DISP_AAL,
> +       MTK_DISP_BLS,
>         MTK_DISP_CCORR,
> +       MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> -       MTK_DISP_AAL,
>         MTK_DISP_GAMMA,
> -       MTK_DISP_UFOE,
> -       MTK_DSI,
> -       MTK_DPI,
> -       MTK_DISP_PWM,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> -       MTK_DISP_BLS,
> +       MTK_DISP_OVL,
> +       MTK_DISP_OVL_2L,
> +       MTK_DISP_PWM,
> +       MTK_DISP_RDMA,
> +       MTK_DISP_UFOE,
> +       MTK_DISP_WDMA,
> +       MTK_DPI,
> +       MTK_DSI,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..a95dc1006b82 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
>  };
>
>  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> -       { .compatible = "mediatek,mt2701-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8173-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> -         .data = (void *)MTK_DISP_OVL_2L },
> -       { .compatible = "mediatek,mt2701-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8183-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-wdma",
> -         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt8173-disp-aal",
> +         .data = (void *)MTK_DISP_AAL},
>         { .compatible = "mediatek,mt8183-disp-ccorr",
>           .data = (void *)MTK_DISP_CCORR },
>         { .compatible = "mediatek,mt2701-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8173-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
> -       { .compatible = "mediatek,mt8173-disp-aal",
> -         .data = (void *)MTK_DISP_AAL},
> +       { .compatible = "mediatek,mt8183-disp-dither",
> +         .data = (void *)MTK_DISP_DITHER },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> -       { .compatible = "mediatek,mt8183-disp-dither",
> -         .data = (void *)MTK_DISP_DITHER },
> -       { .compatible = "mediatek,mt8173-disp-ufoe",
> -         .data = (void *)MTK_DISP_UFOE },
> -       { .compatible = "mediatek,mt2701-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8173-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8183-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt2701-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8173-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8183-dpi",
> -         .data = (void *)MTK_DPI },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8173-disp-od",
> +         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8173-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> +         .data = (void *)MTK_DISP_OVL_2L },
>         { .compatible = "mediatek,mt2701-disp-pwm",
>           .data = (void *)MTK_DISP_BLS },
>         { .compatible = "mediatek,mt8173-disp-pwm",
>           .data = (void *)MTK_DISP_PWM },
> -       { .compatible = "mediatek,mt8173-disp-od",
> -         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8183-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-ufoe",
> +         .data = (void *)MTK_DISP_UFOE },
> +       { .compatible = "mediatek,mt8173-disp-wdma",
> +         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt2701-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8173-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8183-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt2701-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8173-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8183-dsi",
> +         .data = (void *)MTK_DSI },
>         { }
>  };
>
> @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> -                   comp_type == MTK_DSI ||
> -                   comp_type == MTK_DPI) {
> +                   comp_type == MTK_DPI ||
> +                   comp_type == MTK_DSI) {
>                         dev_info(dev, "Adding component match for %pOF\n",
>                                  node);
>                         drm_of_component_match_add(dev, &match, compare_of,
> --
> 2.18.0
>

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Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
>
> 1. Adjust to the alphabetic order for the define, function, struct
>    and array in mediatek-drm driver
> 2. Remove the unsed define in mtk_drm_ddp_comp.c

Separate the 2nd part to another patch.

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-----------
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
>  3 files changed, 133 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..328ee19f931e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -20,50 +20,36 @@
>  #include "mtk_drm_ddp_comp.h"
>  #include "mtk_drm_crtc.h"
>
> -#define DISP_OD_EN                             0x0000
> -#define DISP_OD_INTEN                          0x0008
> -#define DISP_OD_INTSTA                         0x000c
> -#define DISP_OD_CFG                            0x0020
> -#define DISP_OD_SIZE                           0x0030
> -#define DISP_DITHER_5                          0x0114
> -#define DISP_DITHER_7                          0x011c
> -#define DISP_DITHER_15                         0x013c
> -#define DISP_DITHER_16                         0x0140
> -
> -#define DISP_REG_UFO_START                     0x0000
> -
> -#define DISP_AAL_EN                            0x0000
> -#define DISP_AAL_SIZE                          0x0030
> +#define DISP_REG_AAL_EN                                0x0000
> +#define AAL_EN                                 BIT(0)
> +#define DISP_REG_AAL_SIZE                      0x0030
>
> -#define DISP_DITHER_EN                         0x0000
> +#define DISP_REG_DITHER_EN                     0x0000

I think we should not change the register name just for alphabetic
order. We list the register in the order of its address.
If you have another reason to change register name, add another patch
to do this.

Regards,
Chun-Kuang.

>  #define DITHER_EN                              BIT(0)
> -#define DISP_DITHER_CFG                                0x0020
> +#define DISP_REG_DITHER_CFG                    0x0020
>  #define DITHER_RELAY_MODE                      BIT(0)
>  #define DITHER_ENGINE_EN                       BIT(1)
> -#define DISP_DITHER_SIZE                       0x0030
> -
> -#define LUT_10BIT_MASK                         0x03ff
> -
> -#define OD_RELAYMODE                           BIT(0)
> -
> -#define UFO_BYPASS                             BIT(2)
> -
> -#define AAL_EN                                 BIT(0)
> -
>  #define DISP_DITHERING                         BIT(2)
> +#define DISP_REG_DITHER_SIZE                   0x0030
> +#define DISP_REG_DITHER_5                      0x0114
> +#define DISP_REG_DITHER_7                      0x011c
> +#define DISP_REG_DITHER_15                     0x013c
>  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
>  #define DITHER_NEW_BIT_MODE                    BIT(0)
> +#define DISP_REG_DITHER_16                     0x0140
>  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
>  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
>  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
>  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> +
> +#define DISP_REG_OD_EN                         0x0000
> +#define DISP_REG_OD_CFG                                0x0020
> +#define OD_RELAYMODE                           BIT(0)
> +#define DISP_REG_OD_SIZE                       0x0030
> +
> +#define DISP_REG_UFO_START                     0x0000
> +#define UFO_BYPASS                             BIT(2)
>
>  struct mtk_ddp_comp_dev {
>         struct clk *clk;
> @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
>  #endif
>  }
>
> -static int mtk_ddp_clk_enable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       return clk_prepare_enable(priv->clk);
> -}
> -
> -static void mtk_ddp_clk_disable(struct device *dev)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       clk_disable_unprepare(priv->clk);
> -}
> -
>  void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                            unsigned int bpc, unsigned int cfg,
>                            unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>                 return;
>
>         if (bpc >= MTK_MIN_BPC) {
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
> +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
>                               DITHER_NEW_BIT_MODE,
> -                             cmdq_reg, regs, DISP_DITHER_15);
> +                             cmdq_reg, regs, DISP_REG_DITHER_15);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
>                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
>                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> -                             cmdq_reg, regs, DISP_DITHER_16);
> +                             cmdq_reg, regs, DISP_REG_DITHER_16);
>                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
>         }
>  }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> -                             DISP_DITHERING, cmdq_pkt);
> -}
> -
> -static void mtk_od_config(struct device *dev, unsigned int w,
> -                         unsigned int h, unsigned int vrefresh,
> -                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
> -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
> -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> -}
> -
> -static void mtk_od_start(struct device *dev)
> +static int mtk_ddp_clk_enable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(1, priv->regs + DISP_OD_EN);
> +       return clk_prepare_enable(priv->clk);
>  }
>
> -static void mtk_ufoe_start(struct device *dev)
> +static void mtk_ddp_clk_disable(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> +       clk_disable_unprepare(priv->clk);
>  }
>
>  static void mtk_aal_config(struct device *dev, unsigned int w,
> @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE);
>  }
>
>  static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_aal_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
>  }
>
>  static void mtk_dither_config(struct device *dev, unsigned int w,
> @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
> +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_SIZE);
> +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_DITHER_CFG);
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
>                               DITHER_ENGINE_EN, cmdq_pkt);
>  }
>
> @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
>  }
>
>  static void mtk_dither_stop(struct device *dev)
>  {
>         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> +}
> +
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> +                          unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> +                             DISP_DITHERING, cmdq_pkt);
> +}
> +
> +static void mtk_od_config(struct device *dev, unsigned int w,
> +                         unsigned int h, unsigned int vrefresh,
> +                         unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
> +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
> +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> +}
> +
> +static void mtk_od_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(1, priv->regs + DISP_REG_OD_EN);
> +}
> +
> +static void mtk_ufoe_start(struct device *dev)
> +{
> +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
>  }
>
>  static const struct mtk_ddp_comp_funcs ddp_aal = {
> @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>  };
>
>  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> +       [MTK_DISP_AAL] = "aal",
> +       [MTK_DISP_BLS] = "bls",
> +       [MTK_DISP_CCORR] = "ccorr",
> +       [MTK_DISP_COLOR] = "color",
> +       [MTK_DISP_DITHER] = "dither",
> +       [MTK_DISP_GAMMA] = "gamma",
> +       [MTK_DISP_MUTEX] = "mutex",
> +       [MTK_DISP_OD] = "od",
>         [MTK_DISP_OVL] = "ovl",
>         [MTK_DISP_OVL_2L] = "ovl-2l",
> +       [MTK_DISP_PWM] = "pwm",
>         [MTK_DISP_RDMA] = "rdma",
> -       [MTK_DISP_WDMA] = "wdma",
> -       [MTK_DISP_COLOR] = "color",
> -       [MTK_DISP_CCORR] = "ccorr",
> -       [MTK_DISP_AAL] = "aal",
> -       [MTK_DISP_GAMMA] = "gamma",
> -       [MTK_DISP_DITHER] = "dither",
>         [MTK_DISP_UFOE] = "ufoe",
> -       [MTK_DSI] = "dsi",
> +       [MTK_DISP_WDMA] = "wdma",
>         [MTK_DPI] = "dpi",
> -       [MTK_DISP_PWM] = "pwm",
> -       [MTK_DISP_MUTEX] = "mutex",
> -       [MTK_DISP_OD] = "od",
> -       [MTK_DISP_BLS] = "bls",
> +       [MTK_DSI] = "dsi",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> -           type == MTK_DPI ||
> -           type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
>             type == MTK_DISP_OVL_2L ||
>             type == MTK_DISP_PWM ||
> -           type == MTK_DISP_RDMA)
> +           type == MTK_DISP_RDMA ||
> +           type == MTK_DPI ||
> +           type == MTK_DSI)
>                 return 0;
>
>         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..d317b944df66 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -18,22 +18,22 @@ struct mtk_plane_state;
>  struct drm_crtc_state;
>
>  enum mtk_ddp_comp_type {
> -       MTK_DISP_OVL,
> -       MTK_DISP_OVL_2L,
> -       MTK_DISP_RDMA,
> -       MTK_DISP_WDMA,
> -       MTK_DISP_COLOR,
> +       MTK_DISP_AAL,
> +       MTK_DISP_BLS,
>         MTK_DISP_CCORR,
> +       MTK_DISP_COLOR,
>         MTK_DISP_DITHER,
> -       MTK_DISP_AAL,
>         MTK_DISP_GAMMA,
> -       MTK_DISP_UFOE,
> -       MTK_DSI,
> -       MTK_DPI,
> -       MTK_DISP_PWM,
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
> -       MTK_DISP_BLS,
> +       MTK_DISP_OVL,
> +       MTK_DISP_OVL_2L,
> +       MTK_DISP_PWM,
> +       MTK_DISP_RDMA,
> +       MTK_DISP_UFOE,
> +       MTK_DISP_WDMA,
> +       MTK_DPI,
> +       MTK_DSI,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..a95dc1006b82 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -396,50 +396,20 @@ static const struct component_master_ops mtk_drm_ops = {
>  };
>
>  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> -       { .compatible = "mediatek,mt2701-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8173-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl",
> -         .data = (void *)MTK_DISP_OVL },
> -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> -         .data = (void *)MTK_DISP_OVL_2L },
> -       { .compatible = "mediatek,mt2701-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8183-disp-rdma",
> -         .data = (void *)MTK_DISP_RDMA },
> -       { .compatible = "mediatek,mt8173-disp-wdma",
> -         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt8173-disp-aal",
> +         .data = (void *)MTK_DISP_AAL},
>         { .compatible = "mediatek,mt8183-disp-ccorr",
>           .data = (void *)MTK_DISP_CCORR },
>         { .compatible = "mediatek,mt2701-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
>         { .compatible = "mediatek,mt8173-disp-color",
>           .data = (void *)MTK_DISP_COLOR },
> -       { .compatible = "mediatek,mt8173-disp-aal",
> -         .data = (void *)MTK_DISP_AAL},
> +       { .compatible = "mediatek,mt8183-disp-dither",
> +         .data = (void *)MTK_DISP_DITHER },
>         { .compatible = "mediatek,mt8173-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-gamma",
>           .data = (void *)MTK_DISP_GAMMA, },
> -       { .compatible = "mediatek,mt8183-disp-dither",
> -         .data = (void *)MTK_DISP_DITHER },
> -       { .compatible = "mediatek,mt8173-disp-ufoe",
> -         .data = (void *)MTK_DISP_UFOE },
> -       { .compatible = "mediatek,mt2701-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8173-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt8183-dsi",
> -         .data = (void *)MTK_DSI },
> -       { .compatible = "mediatek,mt2701-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8173-dpi",
> -         .data = (void *)MTK_DPI },
> -       { .compatible = "mediatek,mt8183-dpi",
> -         .data = (void *)MTK_DPI },
>         { .compatible = "mediatek,mt2701-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -448,12 +418,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8173-disp-od",
> +         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8173-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl",
> +         .data = (void *)MTK_DISP_OVL },
> +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> +         .data = (void *)MTK_DISP_OVL_2L },
>         { .compatible = "mediatek,mt2701-disp-pwm",
>           .data = (void *)MTK_DISP_BLS },
>         { .compatible = "mediatek,mt8173-disp-pwm",
>           .data = (void *)MTK_DISP_PWM },
> -       { .compatible = "mediatek,mt8173-disp-od",
> -         .data = (void *)MTK_DISP_OD },
> +       { .compatible = "mediatek,mt2701-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8183-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8173-disp-ufoe",
> +         .data = (void *)MTK_DISP_UFOE },
> +       { .compatible = "mediatek,mt8173-disp-wdma",
> +         .data = (void *)MTK_DISP_WDMA },
> +       { .compatible = "mediatek,mt2701-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8173-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt8183-dpi",
> +         .data = (void *)MTK_DPI },
> +       { .compatible = "mediatek,mt2701-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8173-dsi",
> +         .data = (void *)MTK_DSI },
> +       { .compatible = "mediatek,mt8183-dsi",
> +         .data = (void *)MTK_DSI },
>         { }
>  };
>
> @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> -                   comp_type == MTK_DSI ||
> -                   comp_type == MTK_DPI) {
> +                   comp_type == MTK_DPI ||
> +                   comp_type == MTK_DSI) {
>                         dev_info(dev, "Adding component match for %pOF\n",
>                                  node);
>                         drm_of_component_match_add(dev, &match, compare_of,
> --
> 2.18.0
>

Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi Matthias,

On Fri, 2021-08-06 at 13:28 +0200, Matthias Brugger wrote:
> Hi Jason,
> 
> On 05/08/2021 22:52, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> 
> I'd like to see the implementation of vdosys1 as well, to better
> understand why
> we need two compatibles.

Do you mean I have to merge this patch and [1] into the same patch? or
just add [1] at the same series? or just include [1] at commit message?
[1] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-10-nancy.lin@mediatek.com/

> 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!21Mclcdx-qMIpoqPQOZd_-TuzoUfzzJ8UBC_RDzmvz5ISZQjfJIAhhJDKYBClDfOZb71$
> >  
> 
> Please add the binding description to this series.

OK, I'll add the binding patch into this series. 

> 
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 96
> > ++++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
> >  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
> >  3 files changed, 116 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..9339a786ec5d
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN					0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 <<
> > 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			
> > (0 << 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			
> > (1 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT					
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			
> > (0 << 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			
> > (1 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > +	{
> > +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > +		MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> 
> Please update the struct to the new version that includes a mask
> field.
> 

OK, I'll add [2] before my patch and also test it on mt8195 SoC
platform.
[2] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-linux@fw-web.de/


> Regards,
> Matthias
-- 
Regards,
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi Matthias,

On Fri, 2021-08-06 at 13:28 +0200, Matthias Brugger wrote:
> Hi Jason,
> 
> On 05/08/2021 22:52, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> 
> I'd like to see the implementation of vdosys1 as well, to better
> understand why
> we need two compatibles.

Do you mean I have to merge this patch and [1] into the same patch? or
just add [1] at the same series? or just include [1] at commit message?
[1] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-10-nancy.lin@mediatek.com/

> 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!21Mclcdx-qMIpoqPQOZd_-TuzoUfzzJ8UBC_RDzmvz5ISZQjfJIAhhJDKYBClDfOZb71$
> >  
> 
> Please add the binding description to this series.

OK, I'll add the binding patch into this series. 

> 
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 96
> > ++++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
> >  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
> >  3 files changed, 116 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..9339a786ec5d
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN					0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 <<
> > 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			
> > (0 << 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			
> > (1 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT					
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			
> > (0 << 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			
> > (1 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > +	{
> > +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > +		MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> 
> Please update the struct to the new version that includes a mask
> field.
> 

OK, I'll add [2] before my patch and also test it on mt8195 SoC
platform.
[2] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-linux@fw-web.de/


> Regards,
> Matthias
-- 
Regards,
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi Matthias,

On Fri, 2021-08-06 at 13:28 +0200, Matthias Brugger wrote:
> Hi Jason,
> 
> On 05/08/2021 22:52, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> 
> I'd like to see the implementation of vdosys1 as well, to better
> understand why
> we need two compatibles.

Do you mean I have to merge this patch and [1] into the same patch? or
just add [1] at the same series? or just include [1] at commit message?
[1] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-10-nancy.lin@mediatek.com/

> 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!21Mclcdx-qMIpoqPQOZd_-TuzoUfzzJ8UBC_RDzmvz5ISZQjfJIAhhJDKYBClDfOZb71$
> >  
> 
> Please add the binding description to this series.

OK, I'll add the binding patch into this series. 

> 
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 96
> > ++++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       | 11 +++
> >  include/linux/soc/mediatek/mtk-mmsys.h |  9 +++
> >  3 files changed, 116 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..9339a786ec5d
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN					0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 <<
> > 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			
> > (0 << 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			
> > (1 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT					
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1				
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			
> > (0 << 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0			
> > (1 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > +	{
> > +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > +		MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> 
> Please update the struct to the new version that includes a mask
> field.
> 

OK, I'll add [2] before my patch and also test it on mt8195 SoC
platform.
[2] 
https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-linux@fw-web.de/


> Regards,
> Matthias
-- 
Regards,
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Jason-JH Lin]

On Sat, 2021-08-07 at 01:10 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > Add MERGE engine file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!yUTG6rzENI8VUIZjGy5JTWKNX2TyyJn_wn66Wnx2J2GxzFaIhl21IuF8ZlfTqAyj6ahi$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  6 files changed, 277 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..538e0087a44c 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -3,6 +3,7 @@
> >  mediatek-drm-y := mtk_disp_ccorr.o \
> >                   mtk_disp_color.o \
> >                   mtk_disp_gamma.o \
> > +                 mtk_disp_merge.o \
> >                   mtk_disp_ovl.o \
> >                   mtk_disp_rdma.o \
> >                   mtk_drm_crtc.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..f407cd9d873e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs,
> > struct drm_crtc_state *state);
> >  void mtk_gamma_start(struct device *dev);
> >  void mtk_gamma_stop(struct device *dev);
> > 
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > +                     unsigned int height, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> >  void mtk_ovl_bgclr_in_on(struct device *dev);
> >  void mtk_ovl_bgclr_in_off(struct device *dev);
> >  void mtk_ovl_bypass_shadow(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..f3d262792054
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,263 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL            0x000
> > +#define MERGE_EN                       1
> 
> One more indent for the bitwise value.

OK, I'll fix this.
> 
> > +#define DISP_REG_MERGE_CFG_0           0x010
> > +#define DISP_REG_MERGE_CFG_4           0x020
> > +#define DISP_REG_MERGE_CFG_10          0x038
> > +/* no swap */
> > +#define SWAP_MODE                      0
> > +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_12          0x040
> > +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> > +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> > +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_24          0x070
> > +#define DISP_REG_MERGE_CFG_25          0x074
> > +#define DISP_REG_MERGE_CFG_36          0x0a0
> > +#define ULTRA_EN                       1
> > +#define PREULTRA_EN                    1
> > +#define HALT_FOR_DVFS_EN               0
> > +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> > +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> > +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> > +#define DISP_REG_MERGE_CFG_37          0x0a4
> > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> > +#define BUFFER_MODE                    3
> > +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> > +#define DISP_REG_MERGE_CFG_38          0x0a8
> > +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> > +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> > +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_39          0x0ac
> > +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> > +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> > +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_40          0x0b0
> > +/* 6 us, 600M pixel/sec */
> > +#define ULTRA_TH_LOW                   (6 * 600)
> > +/* 8 us, 600M pixel/sec */
> > +#define ULTRA_TH_HIGH                  (8 * 600)
> > +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> > +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_41          0x0b4
> > +/* 8 us, 600M pixel/sec */
> > +#define PREULTRA_TH_LOW                        (8 * 600)
> > +/* 9 us, 600M pixel/sec */
> 
> Add comment that "6 us ~ 9us is experience value and max mmsys clock
> frequency is 594MHz", and I think you should use 594 instead of 600.
> 
> Regards,
> Chun-Kuang.
> 
OK, I'll add this comment and use 594 instead of 600.

Regards,
Jason-JH.Lin

> > +#define PREULTRA_TH_HIGH               (9 * 600)
> > +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> > +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> > +
> > +struct mtk_disp_merge {
> > +       void __iomem *regs;
> > +       struct clk *clk;
> > +       struct clk *async_clk;
> > +       struct cmdq_client_reg          cmdq_reg;
> > +       bool                            fifo_en;
> > +};
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > +                                  struct cmdq_pkt *handle)
> > +{
> > +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 |
> > HALT_FOR_DVFS_EN << 8,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_36,
> > +                          FLD_ULTRA_EN | FLD_PREULTRA_EN |
> > FLD_HALT_FOR_DVFS_EN);
> > +
> > +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_37,
> > +                          FLD_BUFFER_MODE);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_38,
> > +                          FLD_VDE_BLOCK_ULTRA |
> > FLD_VALID_TH_BLOCK_ULTRA |
> > +                          FLD_ULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_39,
> > +                          FLD_NVDE_FORCE_PREULTRA |
> > FLD_NVALID_TH_FORCE_PREULTRA |
> > +                          FLD_PREULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH <<
> > 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_40,
> > +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> > +
> > +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW |
> > PREULTRA_TH_HIGH << 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_41,
> > +                          FLD_PREULTRA_TH_LOW |
> > FLD_PREULTRA_TH_HIGH);
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > +                     unsigned int h, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> > +
> > +       if (!h || !w) {
> > +               dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > +               return;
> > +       }
> > +
> > +       if (priv->fifo_en) {
> > +               mtk_merge_fifo_setting(priv, handle);
> > +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > +       }
> > +
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_0);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_4);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_24);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_25);
> > +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv-
> > >regs,
> > +                          DISP_REG_MERGE_CFG_12,
> > FLD_CFG_MERGE_MODE);
> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > +       int ret = 0;
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       ret = clk_prepare_enable(priv->clk);
> > +       if (ret)
> > +               pr_err("merge clk prepare enable failed\n");
> > +
> > +       if (priv->async_clk) {
> > +               ret = clk_prepare_enable(priv->async_clk);
> > +               if (ret)
> > +                       pr_err("async clk prepare enable
> > failed\n");
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       if (priv->async_clk)
> > +               clk_disable_unprepare(priv->async_clk);
> > +
> > +       clk_disable_unprepare(priv->clk);
> > +}
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > +                              void *data)
> > +{
> > +       return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > +                                 void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > +       .bind   = mtk_disp_merge_bind,
> > +       .unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct resource *res;
> > +       struct mtk_disp_merge *priv;
> > +       int ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       priv->regs = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(priv->regs)) {
> > +               dev_err(dev, "failed to ioremap merge\n");
> > +               return PTR_ERR(priv->regs);
> > +       }
> > +
> > +       priv->clk = devm_clk_get(dev, NULL);
> > +       if (IS_ERR(priv->clk)) {
> > +               dev_err(dev, "failed to get merge clk\n");
> > +               return PTR_ERR(priv->clk);
> > +       }
> > +
> > +       priv->async_clk = of_clk_get(dev->of_node, 1);
> > +       if (IS_ERR(priv->async_clk)) {
> > +               ret = PTR_ERR(priv->async_clk);
> > +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> > +               priv->async_clk = NULL;
> > +       }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +       if (ret)
> > +               dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > +       priv->fifo_en = of_property_read_bool(dev->of_node,
> > +                                             "mediatek,merge-fifo-
> > en");
> > +
> > +       platform_set_drvdata(pdev, priv);
> > +
> > +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> > +       if (ret != 0)
> > +               dev_err(dev, "Failed to add component: %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > +       { .compatible = "mediatek,mt8195-disp-merge", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > +       .probe = mtk_disp_merge_probe,
> > +       .remove = mtk_disp_merge_remove,
> > +       .driver = {
> > +               .name = "mediatek-disp-merge",
> > +               .owner = THIS_MODULE,
> > +               .of_match_table = mtk_disp_merge_driver_dt_match,
> > +       },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 560be6bc9d0e..b42a47c06956 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_DITHER,
> >         MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> > +       MTK_DISP_MERGE,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> >         MTK_DISP_OVL,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index a95dc1006b82..5eb9c0a04447 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> >                 private->comp_node[comp_id] = of_node_get(node);
> > 
> >                 /*
> > -                * Currently only the CCORR, COLOR, GAMMA, OVL,
> > RDMA, DSI, and DPI
> > +                * Currently only the CCORR, COLOR, GAMMA, MERGE,
> > OVL, RDMA, DSI, and DPI
> >                  * blocks have separate component platform drivers
> > and initialize their own
> >                  * DDP component structure. The others are
> > initialized here.
> >                  */
> >                 if (comp_type == MTK_DISP_CCORR ||
> >                     comp_type == MTK_DISP_COLOR ||
> >                     comp_type == MTK_DISP_GAMMA ||
> > +                   comp_type == MTK_DISP_MERGE ||
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > @@ -639,6 +640,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >         &mtk_disp_ccorr_driver,
> >         &mtk_disp_color_driver,
> >         &mtk_disp_gamma_driver,
> > +       &mtk_disp_merge_driver,
> >         &mtk_disp_ovl_driver,
> >         &mtk_disp_rdma_driver,
> >         &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..0fa417219a69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -49,6 +49,7 @@ struct mtk_drm_private {
> >  extern struct platform_driver mtk_disp_ccorr_driver;
> >  extern struct platform_driver mtk_disp_color_driver;
> >  extern struct platform_driver mtk_disp_gamma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Jason-JH Lin]

On Sat, 2021-08-07 at 01:10 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > Add MERGE engine file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!yUTG6rzENI8VUIZjGy5JTWKNX2TyyJn_wn66Wnx2J2GxzFaIhl21IuF8ZlfTqAyj6ahi$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  6 files changed, 277 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..538e0087a44c 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -3,6 +3,7 @@
> >  mediatek-drm-y := mtk_disp_ccorr.o \
> >                   mtk_disp_color.o \
> >                   mtk_disp_gamma.o \
> > +                 mtk_disp_merge.o \
> >                   mtk_disp_ovl.o \
> >                   mtk_disp_rdma.o \
> >                   mtk_drm_crtc.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..f407cd9d873e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs,
> > struct drm_crtc_state *state);
> >  void mtk_gamma_start(struct device *dev);
> >  void mtk_gamma_stop(struct device *dev);
> > 
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > +                     unsigned int height, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> >  void mtk_ovl_bgclr_in_on(struct device *dev);
> >  void mtk_ovl_bgclr_in_off(struct device *dev);
> >  void mtk_ovl_bypass_shadow(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..f3d262792054
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,263 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL            0x000
> > +#define MERGE_EN                       1
> 
> One more indent for the bitwise value.

OK, I'll fix this.
> 
> > +#define DISP_REG_MERGE_CFG_0           0x010
> > +#define DISP_REG_MERGE_CFG_4           0x020
> > +#define DISP_REG_MERGE_CFG_10          0x038
> > +/* no swap */
> > +#define SWAP_MODE                      0
> > +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_12          0x040
> > +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> > +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> > +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_24          0x070
> > +#define DISP_REG_MERGE_CFG_25          0x074
> > +#define DISP_REG_MERGE_CFG_36          0x0a0
> > +#define ULTRA_EN                       1
> > +#define PREULTRA_EN                    1
> > +#define HALT_FOR_DVFS_EN               0
> > +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> > +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> > +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> > +#define DISP_REG_MERGE_CFG_37          0x0a4
> > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> > +#define BUFFER_MODE                    3
> > +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> > +#define DISP_REG_MERGE_CFG_38          0x0a8
> > +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> > +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> > +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_39          0x0ac
> > +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> > +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> > +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_40          0x0b0
> > +/* 6 us, 600M pixel/sec */
> > +#define ULTRA_TH_LOW                   (6 * 600)
> > +/* 8 us, 600M pixel/sec */
> > +#define ULTRA_TH_HIGH                  (8 * 600)
> > +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> > +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_41          0x0b4
> > +/* 8 us, 600M pixel/sec */
> > +#define PREULTRA_TH_LOW                        (8 * 600)
> > +/* 9 us, 600M pixel/sec */
> 
> Add comment that "6 us ~ 9us is experience value and max mmsys clock
> frequency is 594MHz", and I think you should use 594 instead of 600.
> 
> Regards,
> Chun-Kuang.
> 
OK, I'll add this comment and use 594 instead of 600.

Regards,
Jason-JH.Lin

> > +#define PREULTRA_TH_HIGH               (9 * 600)
> > +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> > +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> > +
> > +struct mtk_disp_merge {
> > +       void __iomem *regs;
> > +       struct clk *clk;
> > +       struct clk *async_clk;
> > +       struct cmdq_client_reg          cmdq_reg;
> > +       bool                            fifo_en;
> > +};
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > +                                  struct cmdq_pkt *handle)
> > +{
> > +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 |
> > HALT_FOR_DVFS_EN << 8,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_36,
> > +                          FLD_ULTRA_EN | FLD_PREULTRA_EN |
> > FLD_HALT_FOR_DVFS_EN);
> > +
> > +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_37,
> > +                          FLD_BUFFER_MODE);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_38,
> > +                          FLD_VDE_BLOCK_ULTRA |
> > FLD_VALID_TH_BLOCK_ULTRA |
> > +                          FLD_ULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_39,
> > +                          FLD_NVDE_FORCE_PREULTRA |
> > FLD_NVALID_TH_FORCE_PREULTRA |
> > +                          FLD_PREULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH <<
> > 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_40,
> > +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> > +
> > +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW |
> > PREULTRA_TH_HIGH << 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_41,
> > +                          FLD_PREULTRA_TH_LOW |
> > FLD_PREULTRA_TH_HIGH);
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > +                     unsigned int h, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> > +
> > +       if (!h || !w) {
> > +               dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > +               return;
> > +       }
> > +
> > +       if (priv->fifo_en) {
> > +               mtk_merge_fifo_setting(priv, handle);
> > +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > +       }
> > +
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_0);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_4);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_24);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_25);
> > +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv-
> > >regs,
> > +                          DISP_REG_MERGE_CFG_12,
> > FLD_CFG_MERGE_MODE);
> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > +       int ret = 0;
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       ret = clk_prepare_enable(priv->clk);
> > +       if (ret)
> > +               pr_err("merge clk prepare enable failed\n");
> > +
> > +       if (priv->async_clk) {
> > +               ret = clk_prepare_enable(priv->async_clk);
> > +               if (ret)
> > +                       pr_err("async clk prepare enable
> > failed\n");
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       if (priv->async_clk)
> > +               clk_disable_unprepare(priv->async_clk);
> > +
> > +       clk_disable_unprepare(priv->clk);
> > +}
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > +                              void *data)
> > +{
> > +       return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > +                                 void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > +       .bind   = mtk_disp_merge_bind,
> > +       .unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct resource *res;
> > +       struct mtk_disp_merge *priv;
> > +       int ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       priv->regs = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(priv->regs)) {
> > +               dev_err(dev, "failed to ioremap merge\n");
> > +               return PTR_ERR(priv->regs);
> > +       }
> > +
> > +       priv->clk = devm_clk_get(dev, NULL);
> > +       if (IS_ERR(priv->clk)) {
> > +               dev_err(dev, "failed to get merge clk\n");
> > +               return PTR_ERR(priv->clk);
> > +       }
> > +
> > +       priv->async_clk = of_clk_get(dev->of_node, 1);
> > +       if (IS_ERR(priv->async_clk)) {
> > +               ret = PTR_ERR(priv->async_clk);
> > +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> > +               priv->async_clk = NULL;
> > +       }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +       if (ret)
> > +               dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > +       priv->fifo_en = of_property_read_bool(dev->of_node,
> > +                                             "mediatek,merge-fifo-
> > en");
> > +
> > +       platform_set_drvdata(pdev, priv);
> > +
> > +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> > +       if (ret != 0)
> > +               dev_err(dev, "Failed to add component: %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > +       { .compatible = "mediatek,mt8195-disp-merge", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > +       .probe = mtk_disp_merge_probe,
> > +       .remove = mtk_disp_merge_remove,
> > +       .driver = {
> > +               .name = "mediatek-disp-merge",
> > +               .owner = THIS_MODULE,
> > +               .of_match_table = mtk_disp_merge_driver_dt_match,
> > +       },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 560be6bc9d0e..b42a47c06956 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_DITHER,
> >         MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> > +       MTK_DISP_MERGE,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> >         MTK_DISP_OVL,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index a95dc1006b82..5eb9c0a04447 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> >                 private->comp_node[comp_id] = of_node_get(node);
> > 
> >                 /*
> > -                * Currently only the CCORR, COLOR, GAMMA, OVL,
> > RDMA, DSI, and DPI
> > +                * Currently only the CCORR, COLOR, GAMMA, MERGE,
> > OVL, RDMA, DSI, and DPI
> >                  * blocks have separate component platform drivers
> > and initialize their own
> >                  * DDP component structure. The others are
> > initialized here.
> >                  */
> >                 if (comp_type == MTK_DISP_CCORR ||
> >                     comp_type == MTK_DISP_COLOR ||
> >                     comp_type == MTK_DISP_GAMMA ||
> > +                   comp_type == MTK_DISP_MERGE ||
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > @@ -639,6 +640,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >         &mtk_disp_ccorr_driver,
> >         &mtk_disp_color_driver,
> >         &mtk_disp_gamma_driver,
> > +       &mtk_disp_merge_driver,
> >         &mtk_disp_ovl_driver,
> >         &mtk_disp_rdma_driver,
> >         &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..0fa417219a69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -49,6 +49,7 @@ struct mtk_drm_private {
> >  extern struct platform_driver mtk_disp_ccorr_driver;
> >  extern struct platform_driver mtk_disp_color_driver;
> >  extern struct platform_driver mtk_disp_gamma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 6/7] drm/mediatek: add MERGE support for mediatek-drm

[Jason-JH Lin]

On Sat, 2021-08-07 at 01:10 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > Add MERGE engine file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: display: add mt8195 SoC binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-5-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!yUTG6rzENI8VUIZjGy5JTWKNX2TyyJn_wn66Wnx2J2GxzFaIhl21IuF8ZlfTqAyj6ahi$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 263
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  6 files changed, 277 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..538e0087a44c 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -3,6 +3,7 @@
> >  mediatek-drm-y := mtk_disp_ccorr.o \
> >                   mtk_disp_color.o \
> >                   mtk_disp_gamma.o \
> > +                 mtk_disp_merge.o \
> >                   mtk_disp_ovl.o \
> >                   mtk_disp_rdma.o \
> >                   mtk_drm_crtc.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..f407cd9d873e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs,
> > struct drm_crtc_state *state);
> >  void mtk_gamma_start(struct device *dev);
> >  void mtk_gamma_stop(struct device *dev);
> > 
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > +                     unsigned int height, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> >  void mtk_ovl_bgclr_in_on(struct device *dev);
> >  void mtk_ovl_bgclr_in_off(struct device *dev);
> >  void mtk_ovl_bypass_shadow(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..f3d262792054
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,263 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL            0x000
> > +#define MERGE_EN                       1
> 
> One more indent for the bitwise value.

OK, I'll fix this.
> 
> > +#define DISP_REG_MERGE_CFG_0           0x010
> > +#define DISP_REG_MERGE_CFG_4           0x020
> > +#define DISP_REG_MERGE_CFG_10          0x038
> > +/* no swap */
> > +#define SWAP_MODE                      0
> > +#define FLD_SWAP_MODE                  GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_12          0x040
> > +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> > +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> > +#define FLD_CFG_MERGE_MODE             GENMASK(4, 0)
> > +#define DISP_REG_MERGE_CFG_24          0x070
> > +#define DISP_REG_MERGE_CFG_25          0x074
> > +#define DISP_REG_MERGE_CFG_36          0x0a0
> > +#define ULTRA_EN                       1
> > +#define PREULTRA_EN                    1
> > +#define HALT_FOR_DVFS_EN               0
> > +#define FLD_ULTRA_EN                   GENMASK(0, 0)
> > +#define FLD_PREULTRA_EN                        GENMASK(4, 4)
> > +#define FLD_HALT_FOR_DVFS_EN           GENMASK(8, 8)
> > +#define DISP_REG_MERGE_CFG_37          0x0a4
> > +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
> > +#define BUFFER_MODE                    3
> > +#define FLD_BUFFER_MODE                        GENMASK(1, 0)
> > +#define DISP_REG_MERGE_CFG_38          0x0a8
> > +#define FLD_VDE_BLOCK_ULTRA            GENMASK(0, 0)
> > +#define FLD_VALID_TH_BLOCK_ULTRA       GENMASK(4, 4)
> > +#define FLD_ULTRA_FIFO_VALID_TH                GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_39          0x0ac
> > +#define FLD_NVDE_FORCE_PREULTRA                GENMASK(8, 8)
> > +#define FLD_NVALID_TH_FORCE_PREULTRA   GENMASK(12, 12)
> > +#define FLD_PREULTRA_FIFO_VALID_TH     GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_40          0x0b0
> > +/* 6 us, 600M pixel/sec */
> > +#define ULTRA_TH_LOW                   (6 * 600)
> > +/* 8 us, 600M pixel/sec */
> > +#define ULTRA_TH_HIGH                  (8 * 600)
> > +#define FLD_ULTRA_TH_LOW               GENMASK(15, 0)
> > +#define FLD_ULTRA_TH_HIGH              GENMASK(31, 16)
> > +#define DISP_REG_MERGE_CFG_41          0x0b4
> > +/* 8 us, 600M pixel/sec */
> > +#define PREULTRA_TH_LOW                        (8 * 600)
> > +/* 9 us, 600M pixel/sec */
> 
> Add comment that "6 us ~ 9us is experience value and max mmsys clock
> frequency is 594MHz", and I think you should use 594 instead of 600.
> 
> Regards,
> Chun-Kuang.
> 
OK, I'll add this comment and use 594 instead of 600.

Regards,
Jason-JH.Lin

> > +#define PREULTRA_TH_HIGH               (9 * 600)
> > +#define FLD_PREULTRA_TH_LOW            GENMASK(15, 0)
> > +#define FLD_PREULTRA_TH_HIGH           GENMASK(31, 16)
> > +
> > +struct mtk_disp_merge {
> > +       void __iomem *regs;
> > +       struct clk *clk;
> > +       struct clk *async_clk;
> > +       struct cmdq_client_reg          cmdq_reg;
> > +       bool                            fifo_en;
> > +};
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > +                                  struct cmdq_pkt *handle)
> > +{
> > +       mtk_ddp_write_mask(handle, ULTRA_EN | PREULTRA_EN << 4 |
> > HALT_FOR_DVFS_EN << 8,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_36,
> > +                          FLD_ULTRA_EN | FLD_PREULTRA_EN |
> > FLD_HALT_FOR_DVFS_EN);
> > +
> > +       mtk_ddp_write_mask(handle, BUFFER_MODE,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_37,
> > +                          FLD_BUFFER_MODE);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_38,
> > +                          FLD_VDE_BLOCK_ULTRA |
> > FLD_VALID_TH_BLOCK_ULTRA |
> > +                          FLD_ULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, 0,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_39,
> > +                          FLD_NVDE_FORCE_PREULTRA |
> > FLD_NVALID_TH_FORCE_PREULTRA |
> > +                          FLD_PREULTRA_FIFO_VALID_TH);
> > +
> > +       mtk_ddp_write_mask(handle, ULTRA_TH_LOW | ULTRA_TH_HIGH <<
> > 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_40,
> > +                          FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
> > +
> > +       mtk_ddp_write_mask(handle, PREULTRA_TH_LOW |
> > PREULTRA_TH_HIGH << 16,
> > +                          &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_41,
> > +                          FLD_PREULTRA_TH_LOW |
> > FLD_PREULTRA_TH_HIGH);
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > +                     unsigned int h, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +       unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> > +
> > +       if (!h || !w) {
> > +               dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > +               return;
> > +       }
> > +
> > +       if (priv->fifo_en) {
> > +               mtk_merge_fifo_setting(priv, handle);
> > +               mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > +       }
> > +
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_0);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_4);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_24);
> > +       mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_MERGE_CFG_25);
> > +       mtk_ddp_write_mask(handle, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > +       mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv-
> > >regs,
> > +                          DISP_REG_MERGE_CFG_12,
> > FLD_CFG_MERGE_MODE);
> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > +       int ret = 0;
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       ret = clk_prepare_enable(priv->clk);
> > +       if (ret)
> > +               pr_err("merge clk prepare enable failed\n");
> > +
> > +       if (priv->async_clk) {
> > +               ret = clk_prepare_enable(priv->async_clk);
> > +               if (ret)
> > +                       pr_err("async clk prepare enable
> > failed\n");
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       if (priv->async_clk)
> > +               clk_disable_unprepare(priv->async_clk);
> > +
> > +       clk_disable_unprepare(priv->clk);
> > +}
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > +                              void *data)
> > +{
> > +       return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > +                                 void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > +       .bind   = mtk_disp_merge_bind,
> > +       .unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct resource *res;
> > +       struct mtk_disp_merge *priv;
> > +       int ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       priv->regs = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(priv->regs)) {
> > +               dev_err(dev, "failed to ioremap merge\n");
> > +               return PTR_ERR(priv->regs);
> > +       }
> > +
> > +       priv->clk = devm_clk_get(dev, NULL);
> > +       if (IS_ERR(priv->clk)) {
> > +               dev_err(dev, "failed to get merge clk\n");
> > +               return PTR_ERR(priv->clk);
> > +       }
> > +
> > +       priv->async_clk = of_clk_get(dev->of_node, 1);
> > +       if (IS_ERR(priv->async_clk)) {
> > +               ret = PTR_ERR(priv->async_clk);
> > +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> > +               priv->async_clk = NULL;
> > +       }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +       if (ret)
> > +               dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > +       priv->fifo_en = of_property_read_bool(dev->of_node,
> > +                                             "mediatek,merge-fifo-
> > en");
> > +
> > +       platform_set_drvdata(pdev, priv);
> > +
> > +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> > +       if (ret != 0)
> > +               dev_err(dev, "Failed to add component: %d\n", ret);
> > +
> > +       return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > +       { .compatible = "mediatek,mt8195-disp-merge", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > +       .probe = mtk_disp_merge_probe,
> > +       .remove = mtk_disp_merge_remove,
> > +       .driver = {
> > +               .name = "mediatek-disp-merge",
> > +               .owner = THIS_MODULE,
> > +               .of_match_table = mtk_disp_merge_driver_dt_match,
> > +       },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 560be6bc9d0e..b42a47c06956 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_DITHER,
> >         MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> > +       MTK_DISP_MERGE,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> >         MTK_DISP_OVL,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index a95dc1006b82..5eb9c0a04447 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -532,13 +532,14 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> >                 private->comp_node[comp_id] = of_node_get(node);
> > 
> >                 /*
> > -                * Currently only the CCORR, COLOR, GAMMA, OVL,
> > RDMA, DSI, and DPI
> > +                * Currently only the CCORR, COLOR, GAMMA, MERGE,
> > OVL, RDMA, DSI, and DPI
> >                  * blocks have separate component platform drivers
> > and initialize their own
> >                  * DDP component structure. The others are
> > initialized here.
> >                  */
> >                 if (comp_type == MTK_DISP_CCORR ||
> >                     comp_type == MTK_DISP_COLOR ||
> >                     comp_type == MTK_DISP_GAMMA ||
> > +                   comp_type == MTK_DISP_MERGE ||
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > @@ -639,6 +640,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >         &mtk_disp_ccorr_driver,
> >         &mtk_disp_color_driver,
> >         &mtk_disp_gamma_driver,
> > +       &mtk_disp_merge_driver,
> >         &mtk_disp_ovl_driver,
> >         &mtk_disp_rdma_driver,
> >         &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..0fa417219a69 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -49,6 +49,7 @@ struct mtk_drm_private {
> >  extern struct platform_driver mtk_disp_ccorr_driver;
> >  extern struct platform_driver mtk_disp_color_driver;
> >  extern struct platform_driver mtk_disp_gamma_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Sat, 2021-08-07 at 00:44 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms used for
> > compressing and decompressing image display streams, including
> > the specification of the syntax and semantics of the compressed
> > video bit stream.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC
> > binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!z1RWCIbQoMLarG_-uxUAQS__rpGyCB2Xk7IFVb_Vbo-RoXrWDE4cLvcERABbW11zbL1o$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62
> > +++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
> >  2 files changed, 63 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 328ee19f931e..24c7b004fe4d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -43,6 +43,12 @@
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > 
> > +#define DISP_REG_DSC_CON                       0x0000
> > +#define DSC_EN                                 BIT(0)
> > +#define DSC_DUAL_INOUT                         BIT(2)
> > +#define DSC_BYPASS                             BIT(4)
> > +#define DSC_UFOE_SEL                           BIT(16)
> > +
> >  #define DISP_REG_OD_EN                         0x0000
> >  #define DISP_REG_OD_CFG                                0x0020
> >  #define OD_RELAYMODE                           BIT(0)
> > @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev,
> > unsigned int bpc,
> >                               DISP_DITHERING, cmdq_pkt);
> >  }
> > 
> > +static void mtk_dsc_config(struct device *dev, unsigned int w,
> > +                          unsigned int h, unsigned int vrefresh,
> > +                          unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       /* dsc bypass mode */
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_BYPASS);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, 
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv-
> > >cmdq_reg, priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static void mtk_dsc_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> > +static void mtk_dsc_stop(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> >  static void mtk_od_config(struct device *dev, unsigned int w,
> >                           unsigned int h, unsigned int vrefresh,
> >                           unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi
> > = {
> >         .stop = mtk_dpi_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +       .clk_enable = mtk_ddp_clk_enable,
> > +       .clk_disable = mtk_ddp_clk_disable,
> > +       .config = mtk_dsc_config,
> > +       .start = mtk_dsc_start,
> > +       .stop = mtk_dsc_stop,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_dsi = {
> >         .start = mtk_dsi_ddp_start,
> >         .stop = mtk_dsi_ddp_stop,
> > @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_gamma = {
> >         .stop = mtk_gamma_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +       .clk_enable = mtk_merge_clk_enable,
> > +       .clk_disable = mtk_merge_clk_disable,
> > +       .start = mtk_merge_start,
> > +       .stop = mtk_merge_stop,
> > +       .config = mtk_merge_config,
> > +};
> 
> Move the merge modification to the patch of merge.
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_od = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -333,7 +384,9 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_CCORR] = "ccorr",
> >         [MTK_DISP_COLOR] = "color",
> >         [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_DSC] = "dsc",
> >         [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MERGE] = "merge",
> 
> Ditto.
> 
> >         [MTK_DISP_MUTEX] = "mutex",
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> > @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0,
> > &ddp_dither },
> >         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi
> > },
> >         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi
> > },
> > +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi
> > },
> >         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0,
> > &ddp_gamma },
> > +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5,
> > &ddp_merge },
> 
> Ditto.
> 
> >         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od
> > },
> >         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od
> > },
> >         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl
> > },
> > @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > +           type == MTK_DISP_MERGE ||
> 
> Ditto.
> 
> Regards,
> Chun-Kuang.
> 

OK, I'll move them into MERGE patch.

Regards,
Jason-JH.Lin
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index d317b944df66..560be6bc9d0e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_CCORR,
> >         MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > +       MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
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Linux-mediatek@lists.infradead.org
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Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Sat, 2021-08-07 at 00:44 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms used for
> > compressing and decompressing image display streams, including
> > the specification of the syntax and semantics of the compressed
> > video bit stream.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC
> > binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!z1RWCIbQoMLarG_-uxUAQS__rpGyCB2Xk7IFVb_Vbo-RoXrWDE4cLvcERABbW11zbL1o$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62
> > +++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
> >  2 files changed, 63 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 328ee19f931e..24c7b004fe4d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -43,6 +43,12 @@
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > 
> > +#define DISP_REG_DSC_CON                       0x0000
> > +#define DSC_EN                                 BIT(0)
> > +#define DSC_DUAL_INOUT                         BIT(2)
> > +#define DSC_BYPASS                             BIT(4)
> > +#define DSC_UFOE_SEL                           BIT(16)
> > +
> >  #define DISP_REG_OD_EN                         0x0000
> >  #define DISP_REG_OD_CFG                                0x0020
> >  #define OD_RELAYMODE                           BIT(0)
> > @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev,
> > unsigned int bpc,
> >                               DISP_DITHERING, cmdq_pkt);
> >  }
> > 
> > +static void mtk_dsc_config(struct device *dev, unsigned int w,
> > +                          unsigned int h, unsigned int vrefresh,
> > +                          unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       /* dsc bypass mode */
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_BYPASS);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, 
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv-
> > >cmdq_reg, priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static void mtk_dsc_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> > +static void mtk_dsc_stop(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> >  static void mtk_od_config(struct device *dev, unsigned int w,
> >                           unsigned int h, unsigned int vrefresh,
> >                           unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi
> > = {
> >         .stop = mtk_dpi_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +       .clk_enable = mtk_ddp_clk_enable,
> > +       .clk_disable = mtk_ddp_clk_disable,
> > +       .config = mtk_dsc_config,
> > +       .start = mtk_dsc_start,
> > +       .stop = mtk_dsc_stop,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_dsi = {
> >         .start = mtk_dsi_ddp_start,
> >         .stop = mtk_dsi_ddp_stop,
> > @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_gamma = {
> >         .stop = mtk_gamma_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +       .clk_enable = mtk_merge_clk_enable,
> > +       .clk_disable = mtk_merge_clk_disable,
> > +       .start = mtk_merge_start,
> > +       .stop = mtk_merge_stop,
> > +       .config = mtk_merge_config,
> > +};
> 
> Move the merge modification to the patch of merge.
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_od = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -333,7 +384,9 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_CCORR] = "ccorr",
> >         [MTK_DISP_COLOR] = "color",
> >         [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_DSC] = "dsc",
> >         [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MERGE] = "merge",
> 
> Ditto.
> 
> >         [MTK_DISP_MUTEX] = "mutex",
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> > @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0,
> > &ddp_dither },
> >         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi
> > },
> >         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi
> > },
> > +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi
> > },
> >         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0,
> > &ddp_gamma },
> > +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5,
> > &ddp_merge },
> 
> Ditto.
> 
> >         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od
> > },
> >         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od
> > },
> >         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl
> > },
> > @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > +           type == MTK_DISP_MERGE ||
> 
> Ditto.
> 
> Regards,
> Chun-Kuang.
> 

OK, I'll move them into MERGE patch.

Regards,
Jason-JH.Lin
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index d317b944df66..560be6bc9d0e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_CCORR,
> >         MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > +       MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v6 5/7] drm/mediatek: add DSC support for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Sat, 2021-08-07 at 00:44 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms used for
> > compressing and decompressing image display streams, including
> > the specification of the syntax and semantics of the compressed
> > video bit stream.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > This patch is base on [1]
> > 
> > [1] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC
> > binding
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-4-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!z1RWCIbQoMLarG_-uxUAQS__rpGyCB2Xk7IFVb_Vbo-RoXrWDE4cLvcERABbW11zbL1o$
> >  
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62
> > +++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
> >  2 files changed, 63 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 328ee19f931e..24c7b004fe4d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -43,6 +43,12 @@
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > 
> > +#define DISP_REG_DSC_CON                       0x0000
> > +#define DSC_EN                                 BIT(0)
> > +#define DSC_DUAL_INOUT                         BIT(2)
> > +#define DSC_BYPASS                             BIT(4)
> > +#define DSC_UFOE_SEL                           BIT(16)
> > +
> >  #define DISP_REG_OD_EN                         0x0000
> >  #define DISP_REG_OD_CFG                                0x0020
> >  #define OD_RELAYMODE                           BIT(0)
> > @@ -209,6 +215,35 @@ static void mtk_dither_set(struct device *dev,
> > unsigned int bpc,
> >                               DISP_DITHERING, cmdq_pkt);
> >  }
> > 
> > +static void mtk_dsc_config(struct device *dev, unsigned int w,
> > +                          unsigned int h, unsigned int vrefresh,
> > +                          unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       /* dsc bypass mode */
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg,
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_BYPASS);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, 
> > priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +       mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv-
> > >cmdq_reg, priv->regs,
> > +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static void mtk_dsc_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> > +static void mtk_dsc_stop(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
> > +}
> > +
> >  static void mtk_od_config(struct device *dev, unsigned int w,
> >                           unsigned int h, unsigned int vrefresh,
> >                           unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -272,6 +307,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi
> > = {
> >         .stop = mtk_dpi_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +       .clk_enable = mtk_ddp_clk_enable,
> > +       .clk_disable = mtk_ddp_clk_disable,
> > +       .config = mtk_dsc_config,
> > +       .start = mtk_dsc_start,
> > +       .stop = mtk_dsc_stop,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_dsi = {
> >         .start = mtk_dsi_ddp_start,
> >         .stop = mtk_dsi_ddp_stop,
> > @@ -286,6 +329,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_gamma = {
> >         .stop = mtk_gamma_stop,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +       .clk_enable = mtk_merge_clk_enable,
> > +       .clk_disable = mtk_merge_clk_disable,
> > +       .start = mtk_merge_start,
> > +       .stop = mtk_merge_stop,
> > +       .config = mtk_merge_config,
> > +};
> 
> Move the merge modification to the patch of merge.
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_od = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -333,7 +384,9 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_CCORR] = "ccorr",
> >         [MTK_DISP_COLOR] = "color",
> >         [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_DSC] = "dsc",
> >         [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MERGE] = "merge",
> 
> Ditto.
> 
> >         [MTK_DISP_MUTEX] = "mutex",
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> > @@ -362,11 +415,19 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0,
> > &ddp_dither },
> >         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, &ddp_dpi
> > },
> >         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, &ddp_dpi
> > },
> > +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, &ddp_dsi
> > },
> >         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, &ddp_dsi
> > },
> >         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0,
> > &ddp_gamma },
> > +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5,
> > &ddp_merge },
> 
> Ditto.
> 
> >         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od
> > },
> >         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od
> > },
> >         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, &ddp_ovl
> > },
> > @@ -497,6 +558,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > +           type == MTK_DISP_MERGE ||
> 
> Ditto.
> 
> Regards,
> Chun-Kuang.
> 

OK, I'll move them into MERGE patch.

Regards,
Jason-JH.Lin
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index d317b944df66..560be6bc9d0e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_CCORR,
> >         MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > +       MTK_DISP_DSC,
> >         MTK_DISP_GAMMA,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Mon, 2021-08-09 at 22:34 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > 1. Adjust to the alphabetic order for the define, function, struct
> >    and array in mediatek-drm driver
> > 2. Remove the unsed define in mtk_drm_ddp_comp.c
> 
> Separate the 2nd part to another patch.

OK, I'll separate them.

> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-------
> > ----
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
> >  3 files changed, 133 insertions(+), 145 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..328ee19f931e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,50 +20,36 @@
> >  #include "mtk_drm_ddp_comp.h"
> >  #include "mtk_drm_crtc.h"
> > 
> > -#define DISP_OD_EN                             0x0000
> > -#define DISP_OD_INTEN                          0x0008
> > -#define DISP_OD_INTSTA                         0x000c
> > -#define DISP_OD_CFG                            0x0020
> > -#define DISP_OD_SIZE                           0x0030
> > -#define DISP_DITHER_5                          0x0114
> > -#define DISP_DITHER_7                          0x011c
> > -#define DISP_DITHER_15                         0x013c
> > -#define DISP_DITHER_16                         0x0140
> > -
> > -#define DISP_REG_UFO_START                     0x0000
> > -
> > -#define DISP_AAL_EN                            0x0000
> > -#define DISP_AAL_SIZE                          0x0030
> > +#define DISP_REG_AAL_EN                                0x0000
> > +#define AAL_EN                                 BIT(0)
> > +#define DISP_REG_AAL_SIZE                      0x0030
> > 
> > -#define DISP_DITHER_EN                         0x0000
> > +#define DISP_REG_DITHER_EN                     0x0000
> 
> I think we should not change the register name just for alphabetic
> order. We list the register in the order of its address.
> If you have another reason to change register name, add another patch
> to do this.
> 
> Regards,
> Chun-Kuang.

I think using DISP_REG prifix can identify the macro of register offset
and register value.

So I'll revert the changing of register name in this alphabetic order
patch and send this into another patch.

Regards,
Jason-JH.Lin
> 
> >  #define DITHER_EN                              BIT(0)
> > -#define DISP_DITHER_CFG                                0x0020
> > +#define DISP_REG_DITHER_CFG                    0x0020
> >  #define DITHER_RELAY_MODE                      BIT(0)
> >  #define DITHER_ENGINE_EN                       BIT(1)
> > -#define DISP_DITHER_SIZE                       0x0030
> > -
> > -#define LUT_10BIT_MASK                         0x03ff
> > -
> > -#define OD_RELAYMODE                           BIT(0)
> > -
> > -#define UFO_BYPASS                             BIT(2)
> > -
> > -#define AAL_EN                                 BIT(0)
> > -
> >  #define DISP_DITHERING                         BIT(2)
> > +#define DISP_REG_DITHER_SIZE                   0x0030
> > +#define DISP_REG_DITHER_5                      0x0114
> > +#define DISP_REG_DITHER_7                      0x011c
> > +#define DISP_REG_DITHER_15                     0x013c
> >  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_NEW_BIT_MODE                    BIT(0)
> > +#define DISP_REG_DITHER_16                     0x0140
> >  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> > -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> > +
> > +#define DISP_REG_OD_EN                         0x0000
> > +#define DISP_REG_OD_CFG                                0x0020
> > +#define OD_RELAYMODE                           BIT(0)
> > +#define DISP_REG_OD_SIZE                       0x0030
> > +
> > +#define DISP_REG_UFO_START                     0x0000
> > +#define UFO_BYPASS                             BIT(2)
> > 
> >  struct mtk_ddp_comp_dev {
> >         struct clk *clk;
> > @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> >  #endif
> >  }
> > 
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       clk_disable_unprepare(priv->clk);
> > -}
> > -
> >  void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> >                            unsigned int bpc, unsigned int cfg,
> >                            unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> >                 return;
> > 
> >         if (bpc >= MTK_MIN_BPC) {
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_5);
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_7);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_5);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_7);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_NEW_BIT_MODE,
> > -                             cmdq_reg, regs, DISP_DITHER_15);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_15);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC -
> > bpc),
> > -                             cmdq_reg, regs, DISP_DITHER_16);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_16);
> >                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs,
> > cfg);
> >         }
> >  }
> > 
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > -                             DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > -                         unsigned int h, unsigned int vrefresh,
> > -                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_OD_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_OD_CFG);
> > -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(1, priv->regs + DISP_OD_EN);
> > +       return clk_prepare_enable(priv->clk);
> >  }
> > 
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > +       clk_disable_unprepare(priv->clk);
> >  }
> > 
> >  static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev,
> > unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_AAL_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_AAL_SIZE);
> >  }
> > 
> >  static void mtk_aal_gamma_set(struct device *dev, struct
> > drm_crtc_state *state)
> > @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> > +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_aal_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_dither_config(struct device *dev, unsigned int w,
> > @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device
> > *dev, unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs, DISP_DITHER_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs, DISP_DITHER_CFG);
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_DITHER_CFG,
> > +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_DITHER_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs,
> > +                     DISP_REG_DITHER_CFG);
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_REG_DITHER_CFG,
> >                               DITHER_ENGINE_EN, cmdq_pkt);
> >  }
> > 
> > @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device
> > *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> > +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> >  }
> > 
> >  static void mtk_dither_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > +}
> > +
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > +                          unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > +                             DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > +                         unsigned int h, unsigned int vrefresh,
> > +                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> >  }
> > 
> >  static const struct mtk_ddp_comp_funcs ddp_aal = {
> > @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> >  };
> > 
> >  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > +       [MTK_DISP_AAL] = "aal",
> > +       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DISP_CCORR] = "ccorr",
> > +       [MTK_DISP_COLOR] = "color",
> > +       [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MUTEX] = "mutex",
> > +       [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> >         [MTK_DISP_OVL_2L] = "ovl-2l",
> > +       [MTK_DISP_PWM] = "pwm",
> >         [MTK_DISP_RDMA] = "rdma",
> > -       [MTK_DISP_WDMA] = "wdma",
> > -       [MTK_DISP_COLOR] = "color",
> > -       [MTK_DISP_CCORR] = "ccorr",
> > -       [MTK_DISP_AAL] = "aal",
> > -       [MTK_DISP_GAMMA] = "gamma",
> > -       [MTK_DISP_DITHER] = "dither",
> >         [MTK_DISP_UFOE] = "ufoe",
> > -       [MTK_DSI] = "dsi",
> > +       [MTK_DISP_WDMA] = "wdma",
> >         [MTK_DPI] = "dpi",
> > -       [MTK_DISP_PWM] = "pwm",
> > -       [MTK_DISP_MUTEX] = "mutex",
> > -       [MTK_DISP_OD] = "od",
> > -       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DSI] = "dsi",
> >  };
> > 
> >  struct mtk_ddp_comp_match {
> > @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > -           type == MTK_DPI ||
> > -           type == MTK_DSI ||
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > -           type == MTK_DISP_RDMA)
> > +           type == MTK_DISP_RDMA ||
> > +           type == MTK_DPI ||
> > +           type == MTK_DSI)
> >                 return 0;
> > 
> >         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> >  struct drm_crtc_state;
> > 
> >  enum mtk_ddp_comp_type {
> > -       MTK_DISP_OVL,
> > -       MTK_DISP_OVL_2L,
> > -       MTK_DISP_RDMA,
> > -       MTK_DISP_WDMA,
> > -       MTK_DISP_COLOR,
> > +       MTK_DISP_AAL,
> > +       MTK_DISP_BLS,
> >         MTK_DISP_CCORR,
> > +       MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > -       MTK_DISP_AAL,
> >         MTK_DISP_GAMMA,
> > -       MTK_DISP_UFOE,
> > -       MTK_DSI,
> > -       MTK_DPI,
> > -       MTK_DISP_PWM,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > -       MTK_DISP_BLS,
> > +       MTK_DISP_OVL,
> > +       MTK_DISP_OVL_2L,
> > +       MTK_DISP_PWM,
> > +       MTK_DISP_RDMA,
> > +       MTK_DISP_UFOE,
> > +       MTK_DISP_WDMA,
> > +       MTK_DPI,
> > +       MTK_DSI,
> >         MTK_DDP_COMP_TYPE_MAX,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> >  };
> > 
> >  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > -       { .compatible = "mediatek,mt2701-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8173-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > -         .data = (void *)MTK_DISP_OVL_2L },
> > -       { .compatible = "mediatek,mt2701-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8183-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-wdma",
> > -         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt8173-disp-aal",
> > +         .data = (void *)MTK_DISP_AAL},
> >         { .compatible = "mediatek,mt8183-disp-ccorr",
> >           .data = (void *)MTK_DISP_CCORR },
> >         { .compatible = "mediatek,mt2701-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> >         { .compatible = "mediatek,mt8173-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> > -       { .compatible = "mediatek,mt8173-disp-aal",
> > -         .data = (void *)MTK_DISP_AAL},
> > +       { .compatible = "mediatek,mt8183-disp-dither",
> > +         .data = (void *)MTK_DISP_DITHER },
> >         { .compatible = "mediatek,mt8173-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> >         { .compatible = "mediatek,mt8183-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> > -       { .compatible = "mediatek,mt8183-disp-dither",
> > -         .data = (void *)MTK_DISP_DITHER },
> > -       { .compatible = "mediatek,mt8173-disp-ufoe",
> > -         .data = (void *)MTK_DISP_UFOE },
> > -       { .compatible = "mediatek,mt2701-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8173-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8183-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt2701-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8173-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8183-dpi",
> > -         .data = (void *)MTK_DPI },
> >         { .compatible = "mediatek,mt2701-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt8183-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> > +       { .compatible = "mediatek,mt8173-disp-od",
> > +         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8173-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > +         .data = (void *)MTK_DISP_OVL_2L },
> >         { .compatible = "mediatek,mt2701-disp-pwm",
> >           .data = (void *)MTK_DISP_BLS },
> >         { .compatible = "mediatek,mt8173-disp-pwm",
> >           .data = (void *)MTK_DISP_PWM },
> > -       { .compatible = "mediatek,mt8173-disp-od",
> > -         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8183-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-ufoe",
> > +         .data = (void *)MTK_DISP_UFOE },
> > +       { .compatible = "mediatek,mt8173-disp-wdma",
> > +         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt2701-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8173-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8183-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt2701-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8173-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8183-dsi",
> > +         .data = (void *)MTK_DSI },
> >         { }
> >  };
> > 
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > -                   comp_type == MTK_DSI ||
> > -                   comp_type == MTK_DPI) {
> > +                   comp_type == MTK_DPI ||
> > +                   comp_type == MTK_DSI) {
> >                         dev_info(dev, "Adding component match for
> > %pOF\n",
> >                                  node);
> >                         drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Mon, 2021-08-09 at 22:34 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > 1. Adjust to the alphabetic order for the define, function, struct
> >    and array in mediatek-drm driver
> > 2. Remove the unsed define in mtk_drm_ddp_comp.c
> 
> Separate the 2nd part to another patch.

OK, I'll separate them.

> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-------
> > ----
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
> >  3 files changed, 133 insertions(+), 145 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..328ee19f931e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,50 +20,36 @@
> >  #include "mtk_drm_ddp_comp.h"
> >  #include "mtk_drm_crtc.h"
> > 
> > -#define DISP_OD_EN                             0x0000
> > -#define DISP_OD_INTEN                          0x0008
> > -#define DISP_OD_INTSTA                         0x000c
> > -#define DISP_OD_CFG                            0x0020
> > -#define DISP_OD_SIZE                           0x0030
> > -#define DISP_DITHER_5                          0x0114
> > -#define DISP_DITHER_7                          0x011c
> > -#define DISP_DITHER_15                         0x013c
> > -#define DISP_DITHER_16                         0x0140
> > -
> > -#define DISP_REG_UFO_START                     0x0000
> > -
> > -#define DISP_AAL_EN                            0x0000
> > -#define DISP_AAL_SIZE                          0x0030
> > +#define DISP_REG_AAL_EN                                0x0000
> > +#define AAL_EN                                 BIT(0)
> > +#define DISP_REG_AAL_SIZE                      0x0030
> > 
> > -#define DISP_DITHER_EN                         0x0000
> > +#define DISP_REG_DITHER_EN                     0x0000
> 
> I think we should not change the register name just for alphabetic
> order. We list the register in the order of its address.
> If you have another reason to change register name, add another patch
> to do this.
> 
> Regards,
> Chun-Kuang.

I think using DISP_REG prifix can identify the macro of register offset
and register value.

So I'll revert the changing of register name in this alphabetic order
patch and send this into another patch.

Regards,
Jason-JH.Lin
> 
> >  #define DITHER_EN                              BIT(0)
> > -#define DISP_DITHER_CFG                                0x0020
> > +#define DISP_REG_DITHER_CFG                    0x0020
> >  #define DITHER_RELAY_MODE                      BIT(0)
> >  #define DITHER_ENGINE_EN                       BIT(1)
> > -#define DISP_DITHER_SIZE                       0x0030
> > -
> > -#define LUT_10BIT_MASK                         0x03ff
> > -
> > -#define OD_RELAYMODE                           BIT(0)
> > -
> > -#define UFO_BYPASS                             BIT(2)
> > -
> > -#define AAL_EN                                 BIT(0)
> > -
> >  #define DISP_DITHERING                         BIT(2)
> > +#define DISP_REG_DITHER_SIZE                   0x0030
> > +#define DISP_REG_DITHER_5                      0x0114
> > +#define DISP_REG_DITHER_7                      0x011c
> > +#define DISP_REG_DITHER_15                     0x013c
> >  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_NEW_BIT_MODE                    BIT(0)
> > +#define DISP_REG_DITHER_16                     0x0140
> >  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> > -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> > +
> > +#define DISP_REG_OD_EN                         0x0000
> > +#define DISP_REG_OD_CFG                                0x0020
> > +#define OD_RELAYMODE                           BIT(0)
> > +#define DISP_REG_OD_SIZE                       0x0030
> > +
> > +#define DISP_REG_UFO_START                     0x0000
> > +#define UFO_BYPASS                             BIT(2)
> > 
> >  struct mtk_ddp_comp_dev {
> >         struct clk *clk;
> > @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> >  #endif
> >  }
> > 
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       clk_disable_unprepare(priv->clk);
> > -}
> > -
> >  void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> >                            unsigned int bpc, unsigned int cfg,
> >                            unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> >                 return;
> > 
> >         if (bpc >= MTK_MIN_BPC) {
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_5);
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_7);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_5);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_7);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_NEW_BIT_MODE,
> > -                             cmdq_reg, regs, DISP_DITHER_15);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_15);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC -
> > bpc),
> > -                             cmdq_reg, regs, DISP_DITHER_16);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_16);
> >                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs,
> > cfg);
> >         }
> >  }
> > 
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > -                             DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > -                         unsigned int h, unsigned int vrefresh,
> > -                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_OD_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_OD_CFG);
> > -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(1, priv->regs + DISP_OD_EN);
> > +       return clk_prepare_enable(priv->clk);
> >  }
> > 
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > +       clk_disable_unprepare(priv->clk);
> >  }
> > 
> >  static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev,
> > unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_AAL_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_AAL_SIZE);
> >  }
> > 
> >  static void mtk_aal_gamma_set(struct device *dev, struct
> > drm_crtc_state *state)
> > @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> > +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_aal_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_dither_config(struct device *dev, unsigned int w,
> > @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device
> > *dev, unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs, DISP_DITHER_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs, DISP_DITHER_CFG);
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_DITHER_CFG,
> > +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_DITHER_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs,
> > +                     DISP_REG_DITHER_CFG);
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_REG_DITHER_CFG,
> >                               DITHER_ENGINE_EN, cmdq_pkt);
> >  }
> > 
> > @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device
> > *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> > +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> >  }
> > 
> >  static void mtk_dither_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > +}
> > +
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > +                          unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > +                             DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > +                         unsigned int h, unsigned int vrefresh,
> > +                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> >  }
> > 
> >  static const struct mtk_ddp_comp_funcs ddp_aal = {
> > @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> >  };
> > 
> >  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > +       [MTK_DISP_AAL] = "aal",
> > +       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DISP_CCORR] = "ccorr",
> > +       [MTK_DISP_COLOR] = "color",
> > +       [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MUTEX] = "mutex",
> > +       [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> >         [MTK_DISP_OVL_2L] = "ovl-2l",
> > +       [MTK_DISP_PWM] = "pwm",
> >         [MTK_DISP_RDMA] = "rdma",
> > -       [MTK_DISP_WDMA] = "wdma",
> > -       [MTK_DISP_COLOR] = "color",
> > -       [MTK_DISP_CCORR] = "ccorr",
> > -       [MTK_DISP_AAL] = "aal",
> > -       [MTK_DISP_GAMMA] = "gamma",
> > -       [MTK_DISP_DITHER] = "dither",
> >         [MTK_DISP_UFOE] = "ufoe",
> > -       [MTK_DSI] = "dsi",
> > +       [MTK_DISP_WDMA] = "wdma",
> >         [MTK_DPI] = "dpi",
> > -       [MTK_DISP_PWM] = "pwm",
> > -       [MTK_DISP_MUTEX] = "mutex",
> > -       [MTK_DISP_OD] = "od",
> > -       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DSI] = "dsi",
> >  };
> > 
> >  struct mtk_ddp_comp_match {
> > @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > -           type == MTK_DPI ||
> > -           type == MTK_DSI ||
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > -           type == MTK_DISP_RDMA)
> > +           type == MTK_DISP_RDMA ||
> > +           type == MTK_DPI ||
> > +           type == MTK_DSI)
> >                 return 0;
> > 
> >         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> >  struct drm_crtc_state;
> > 
> >  enum mtk_ddp_comp_type {
> > -       MTK_DISP_OVL,
> > -       MTK_DISP_OVL_2L,
> > -       MTK_DISP_RDMA,
> > -       MTK_DISP_WDMA,
> > -       MTK_DISP_COLOR,
> > +       MTK_DISP_AAL,
> > +       MTK_DISP_BLS,
> >         MTK_DISP_CCORR,
> > +       MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > -       MTK_DISP_AAL,
> >         MTK_DISP_GAMMA,
> > -       MTK_DISP_UFOE,
> > -       MTK_DSI,
> > -       MTK_DPI,
> > -       MTK_DISP_PWM,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > -       MTK_DISP_BLS,
> > +       MTK_DISP_OVL,
> > +       MTK_DISP_OVL_2L,
> > +       MTK_DISP_PWM,
> > +       MTK_DISP_RDMA,
> > +       MTK_DISP_UFOE,
> > +       MTK_DISP_WDMA,
> > +       MTK_DPI,
> > +       MTK_DSI,
> >         MTK_DDP_COMP_TYPE_MAX,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> >  };
> > 
> >  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > -       { .compatible = "mediatek,mt2701-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8173-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > -         .data = (void *)MTK_DISP_OVL_2L },
> > -       { .compatible = "mediatek,mt2701-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8183-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-wdma",
> > -         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt8173-disp-aal",
> > +         .data = (void *)MTK_DISP_AAL},
> >         { .compatible = "mediatek,mt8183-disp-ccorr",
> >           .data = (void *)MTK_DISP_CCORR },
> >         { .compatible = "mediatek,mt2701-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> >         { .compatible = "mediatek,mt8173-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> > -       { .compatible = "mediatek,mt8173-disp-aal",
> > -         .data = (void *)MTK_DISP_AAL},
> > +       { .compatible = "mediatek,mt8183-disp-dither",
> > +         .data = (void *)MTK_DISP_DITHER },
> >         { .compatible = "mediatek,mt8173-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> >         { .compatible = "mediatek,mt8183-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> > -       { .compatible = "mediatek,mt8183-disp-dither",
> > -         .data = (void *)MTK_DISP_DITHER },
> > -       { .compatible = "mediatek,mt8173-disp-ufoe",
> > -         .data = (void *)MTK_DISP_UFOE },
> > -       { .compatible = "mediatek,mt2701-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8173-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8183-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt2701-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8173-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8183-dpi",
> > -         .data = (void *)MTK_DPI },
> >         { .compatible = "mediatek,mt2701-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt8183-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> > +       { .compatible = "mediatek,mt8173-disp-od",
> > +         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8173-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > +         .data = (void *)MTK_DISP_OVL_2L },
> >         { .compatible = "mediatek,mt2701-disp-pwm",
> >           .data = (void *)MTK_DISP_BLS },
> >         { .compatible = "mediatek,mt8173-disp-pwm",
> >           .data = (void *)MTK_DISP_PWM },
> > -       { .compatible = "mediatek,mt8173-disp-od",
> > -         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8183-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-ufoe",
> > +         .data = (void *)MTK_DISP_UFOE },
> > +       { .compatible = "mediatek,mt8173-disp-wdma",
> > +         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt2701-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8173-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8183-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt2701-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8173-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8183-dsi",
> > +         .data = (void *)MTK_DSI },
> >         { }
> >  };
> > 
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > -                   comp_type == MTK_DSI ||
> > -                   comp_type == MTK_DPI) {
> > +                   comp_type == MTK_DPI ||
> > +                   comp_type == MTK_DSI) {
> >                         dev_info(dev, "Adding component match for
> > %pOF\n",
> >                                  node);
> >                         drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Re: [PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm

[Jason-JH Lin]

Hi CK,

On Mon, 2021-08-09 at 22:34 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> > 
> > 1. Adjust to the alphabetic order for the define, function, struct
> >    and array in mediatek-drm driver
> > 2. Remove the unsed define in mtk_drm_ddp_comp.c
> 
> Separate the 2nd part to another patch.

OK, I'll separate them.

> 
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-------
> > ----
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  22 +--
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |  76 ++++-----
> >  3 files changed, 133 insertions(+), 145 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..328ee19f931e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,50 +20,36 @@
> >  #include "mtk_drm_ddp_comp.h"
> >  #include "mtk_drm_crtc.h"
> > 
> > -#define DISP_OD_EN                             0x0000
> > -#define DISP_OD_INTEN                          0x0008
> > -#define DISP_OD_INTSTA                         0x000c
> > -#define DISP_OD_CFG                            0x0020
> > -#define DISP_OD_SIZE                           0x0030
> > -#define DISP_DITHER_5                          0x0114
> > -#define DISP_DITHER_7                          0x011c
> > -#define DISP_DITHER_15                         0x013c
> > -#define DISP_DITHER_16                         0x0140
> > -
> > -#define DISP_REG_UFO_START                     0x0000
> > -
> > -#define DISP_AAL_EN                            0x0000
> > -#define DISP_AAL_SIZE                          0x0030
> > +#define DISP_REG_AAL_EN                                0x0000
> > +#define AAL_EN                                 BIT(0)
> > +#define DISP_REG_AAL_SIZE                      0x0030
> > 
> > -#define DISP_DITHER_EN                         0x0000
> > +#define DISP_REG_DITHER_EN                     0x0000
> 
> I think we should not change the register name just for alphabetic
> order. We list the register in the order of its address.
> If you have another reason to change register name, add another patch
> to do this.
> 
> Regards,
> Chun-Kuang.

I think using DISP_REG prifix can identify the macro of register offset
and register value.

So I'll revert the changing of register name in this alphabetic order
patch and send this into another patch.

Regards,
Jason-JH.Lin
> 
> >  #define DITHER_EN                              BIT(0)
> > -#define DISP_DITHER_CFG                                0x0020
> > +#define DISP_REG_DITHER_CFG                    0x0020
> >  #define DITHER_RELAY_MODE                      BIT(0)
> >  #define DITHER_ENGINE_EN                       BIT(1)
> > -#define DISP_DITHER_SIZE                       0x0030
> > -
> > -#define LUT_10BIT_MASK                         0x03ff
> > -
> > -#define OD_RELAYMODE                           BIT(0)
> > -
> > -#define UFO_BYPASS                             BIT(2)
> > -
> > -#define AAL_EN                                 BIT(0)
> > -
> >  #define DISP_DITHERING                         BIT(2)
> > +#define DISP_REG_DITHER_SIZE                   0x0030
> > +#define DISP_REG_DITHER_5                      0x0114
> > +#define DISP_REG_DITHER_7                      0x011c
> > +#define DISP_REG_DITHER_15                     0x013c
> >  #define DITHER_LSB_ERR_SHIFT_R(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_R(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_R(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_R(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_NEW_BIT_MODE                    BIT(0)
> > +#define DISP_REG_DITHER_16                     0x0140
> >  #define DITHER_LSB_ERR_SHIFT_B(x)              (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_B(x)                  (((x) & 0x7) << 24)
> >  #define DITHER_ADD_LSHIFT_B(x)                 (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_B(x)                 (((x) & 0x7) << 16)
> >  #define DITHER_LSB_ERR_SHIFT_G(x)              (((x) & 0x7) << 12)
> > -#define DITHER_OVFLW_BIT_G(x)                  (((x) & 0x7) << 8)
> >  #define DITHER_ADD_LSHIFT_G(x)                 (((x) & 0x7) << 4)
> > -#define DITHER_ADD_RSHIFT_G(x)                 (((x) & 0x7) << 0)
> > +
> > +#define DISP_REG_OD_EN                         0x0000
> > +#define DISP_REG_OD_CFG                                0x0020
> > +#define OD_RELAYMODE                           BIT(0)
> > +#define DISP_REG_OD_SIZE                       0x0030
> > +
> > +#define DISP_REG_UFO_START                     0x0000
> > +#define UFO_BYPASS                             BIT(2)
> > 
> >  struct mtk_ddp_comp_dev {
> >         struct clk *clk;
> > @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> >  #endif
> >  }
> > 
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       clk_disable_unprepare(priv->clk);
> > -}
> > -
> >  void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> >                            unsigned int bpc, unsigned int cfg,
> >                            unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> >                 return;
> > 
> >         if (bpc >= MTK_MIN_BPC) {
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_5);
> > -               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_7);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_5);
> > +               mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_7);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_NEW_BIT_MODE,
> > -                             cmdq_reg, regs, DISP_DITHER_15);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_15);
> >                 mtk_ddp_write(cmdq_pkt,
> >                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC -
> > bpc) |
> >                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC -
> > bpc),
> > -                             cmdq_reg, regs, DISP_DITHER_16);
> > +                             cmdq_reg, regs, DISP_REG_DITHER_16);
> >                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs,
> > cfg);
> >         }
> >  }
> > 
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > -                   unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > -                             DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > -                         unsigned int h, unsigned int vrefresh,
> > -                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > -       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_OD_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_OD_CFG);
> > -       mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(1, priv->regs + DISP_OD_EN);
> > +       return clk_prepare_enable(priv->clk);
> >  }
> > 
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > +       clk_disable_unprepare(priv->clk);
> >  }
> > 
> >  static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev,
> > unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_AAL_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_AAL_SIZE);
> >  }
> > 
> >  static void mtk_aal_gamma_set(struct device *dev, struct
> > drm_crtc_state *state)
> > @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(AAL_EN, priv->regs + DISP_AAL_EN);
> > +       writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_aal_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
> >  }
> > 
> >  static void mtk_dither_config(struct device *dev, unsigned int w,
> > @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device
> > *dev, unsigned int w,
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs, DISP_DITHER_SIZE);
> > -       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs, DISP_DITHER_CFG);
> > -       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_DITHER_CFG,
> > +       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > +                     DISP_REG_DITHER_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > priv->regs,
> > +                     DISP_REG_DITHER_CFG);
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_REG_DITHER_CFG,
> >                               DITHER_ENGINE_EN, cmdq_pkt);
> >  }
> > 
> > @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device
> > *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> > +       writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> >  }
> > 
> >  static void mtk_dither_stop(struct device *dev)
> >  {
> >         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > 
> > -       writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> > +       writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > +}
> > +
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > +                          unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > +                             DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > +                         unsigned int h, unsigned int vrefresh,
> > +                         unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > +       mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > +       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > +       writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> >  }
> > 
> >  static const struct mtk_ddp_comp_funcs ddp_aal = {
> > @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> >  };
> > 
> >  static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > +       [MTK_DISP_AAL] = "aal",
> > +       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DISP_CCORR] = "ccorr",
> > +       [MTK_DISP_COLOR] = "color",
> > +       [MTK_DISP_DITHER] = "dither",
> > +       [MTK_DISP_GAMMA] = "gamma",
> > +       [MTK_DISP_MUTEX] = "mutex",
> > +       [MTK_DISP_OD] = "od",
> >         [MTK_DISP_OVL] = "ovl",
> >         [MTK_DISP_OVL_2L] = "ovl-2l",
> > +       [MTK_DISP_PWM] = "pwm",
> >         [MTK_DISP_RDMA] = "rdma",
> > -       [MTK_DISP_WDMA] = "wdma",
> > -       [MTK_DISP_COLOR] = "color",
> > -       [MTK_DISP_CCORR] = "ccorr",
> > -       [MTK_DISP_AAL] = "aal",
> > -       [MTK_DISP_GAMMA] = "gamma",
> > -       [MTK_DISP_DITHER] = "dither",
> >         [MTK_DISP_UFOE] = "ufoe",
> > -       [MTK_DSI] = "dsi",
> > +       [MTK_DISP_WDMA] = "wdma",
> >         [MTK_DPI] = "dpi",
> > -       [MTK_DISP_PWM] = "pwm",
> > -       [MTK_DISP_MUTEX] = "mutex",
> > -       [MTK_DISP_OD] = "od",
> > -       [MTK_DISP_BLS] = "bls",
> > +       [MTK_DSI] = "dsi",
> >  };
> > 
> >  struct mtk_ddp_comp_match {
> > @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > -           type == MTK_DPI ||
> > -           type == MTK_DSI ||
> >             type == MTK_DISP_OVL ||
> >             type == MTK_DISP_OVL_2L ||
> >             type == MTK_DISP_PWM ||
> > -           type == MTK_DISP_RDMA)
> > +           type == MTK_DISP_RDMA ||
> > +           type == MTK_DPI ||
> > +           type == MTK_DSI)
> >                 return 0;
> > 
> >         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> >  struct drm_crtc_state;
> > 
> >  enum mtk_ddp_comp_type {
> > -       MTK_DISP_OVL,
> > -       MTK_DISP_OVL_2L,
> > -       MTK_DISP_RDMA,
> > -       MTK_DISP_WDMA,
> > -       MTK_DISP_COLOR,
> > +       MTK_DISP_AAL,
> > +       MTK_DISP_BLS,
> >         MTK_DISP_CCORR,
> > +       MTK_DISP_COLOR,
> >         MTK_DISP_DITHER,
> > -       MTK_DISP_AAL,
> >         MTK_DISP_GAMMA,
> > -       MTK_DISP_UFOE,
> > -       MTK_DSI,
> > -       MTK_DPI,
> > -       MTK_DISP_PWM,
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> > -       MTK_DISP_BLS,
> > +       MTK_DISP_OVL,
> > +       MTK_DISP_OVL_2L,
> > +       MTK_DISP_PWM,
> > +       MTK_DISP_RDMA,
> > +       MTK_DISP_UFOE,
> > +       MTK_DISP_WDMA,
> > +       MTK_DPI,
> > +       MTK_DSI,
> >         MTK_DDP_COMP_TYPE_MAX,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> >  };
> > 
> >  static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > -       { .compatible = "mediatek,mt2701-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8173-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl",
> > -         .data = (void *)MTK_DISP_OVL },
> > -       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > -         .data = (void *)MTK_DISP_OVL_2L },
> > -       { .compatible = "mediatek,mt2701-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8183-disp-rdma",
> > -         .data = (void *)MTK_DISP_RDMA },
> > -       { .compatible = "mediatek,mt8173-disp-wdma",
> > -         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt8173-disp-aal",
> > +         .data = (void *)MTK_DISP_AAL},
> >         { .compatible = "mediatek,mt8183-disp-ccorr",
> >           .data = (void *)MTK_DISP_CCORR },
> >         { .compatible = "mediatek,mt2701-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> >         { .compatible = "mediatek,mt8173-disp-color",
> >           .data = (void *)MTK_DISP_COLOR },
> > -       { .compatible = "mediatek,mt8173-disp-aal",
> > -         .data = (void *)MTK_DISP_AAL},
> > +       { .compatible = "mediatek,mt8183-disp-dither",
> > +         .data = (void *)MTK_DISP_DITHER },
> >         { .compatible = "mediatek,mt8173-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> >         { .compatible = "mediatek,mt8183-disp-gamma",
> >           .data = (void *)MTK_DISP_GAMMA, },
> > -       { .compatible = "mediatek,mt8183-disp-dither",
> > -         .data = (void *)MTK_DISP_DITHER },
> > -       { .compatible = "mediatek,mt8173-disp-ufoe",
> > -         .data = (void *)MTK_DISP_UFOE },
> > -       { .compatible = "mediatek,mt2701-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8173-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt8183-dsi",
> > -         .data = (void *)MTK_DSI },
> > -       { .compatible = "mediatek,mt2701-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8173-dpi",
> > -         .data = (void *)MTK_DPI },
> > -       { .compatible = "mediatek,mt8183-dpi",
> > -         .data = (void *)MTK_DPI },
> >         { .compatible = "mediatek,mt2701-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt8183-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> > +       { .compatible = "mediatek,mt8173-disp-od",
> > +         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8173-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl",
> > +         .data = (void *)MTK_DISP_OVL },
> > +       { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > +         .data = (void *)MTK_DISP_OVL_2L },
> >         { .compatible = "mediatek,mt2701-disp-pwm",
> >           .data = (void *)MTK_DISP_BLS },
> >         { .compatible = "mediatek,mt8173-disp-pwm",
> >           .data = (void *)MTK_DISP_PWM },
> > -       { .compatible = "mediatek,mt8173-disp-od",
> > -         .data = (void *)MTK_DISP_OD },
> > +       { .compatible = "mediatek,mt2701-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8183-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8173-disp-ufoe",
> > +         .data = (void *)MTK_DISP_UFOE },
> > +       { .compatible = "mediatek,mt8173-disp-wdma",
> > +         .data = (void *)MTK_DISP_WDMA },
> > +       { .compatible = "mediatek,mt2701-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8173-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt8183-dpi",
> > +         .data = (void *)MTK_DPI },
> > +       { .compatible = "mediatek,mt2701-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8173-dsi",
> > +         .data = (void *)MTK_DSI },
> > +       { .compatible = "mediatek,mt8183-dsi",
> > +         .data = (void *)MTK_DSI },
> >         { }
> >  };
> > 
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > -                   comp_type == MTK_DSI ||
> > -                   comp_type == MTK_DPI) {
> > +                   comp_type == MTK_DPI ||
> > +                   comp_type == MTK_DSI) {
> >                         dev_info(dev, "Adding component match for
> > %pOF\n",
> >                                  node);
> >                         drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>