From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08037C636CA for ; Sun, 18 Jul 2021 23:22:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D945A60FDA for ; Sun, 18 Jul 2021 23:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233646AbhGRXZ4 (ORCPT ); Sun, 18 Jul 2021 19:25:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:32890 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231846AbhGRXZz (ORCPT ); Sun, 18 Jul 2021 19:25:55 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A7A7061166; Sun, 18 Jul 2021 23:22:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626650576; bh=+cIz9IsxTWX0flU1vqzo73L/SPqQutS6FLX3yWrvH3A=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=byKOgNCkjolptKZ8o4CD5FZBcRQ66Zn6YY6qX6/BlieuaheftSXku3KUimj07pzTB SLqyZ4X/+BGySRyq/eQfKJ4SqH5zlC23/VZQJQ3fVM7Jwv9imG53OIhZeTn0ubpFNc 1utIgSgZ2Xf+yaSC5uCFz2t2K96DR5cvDP/nBWkp6cx8zVEm/00vl47M7j5d4wnDR3 vOExrMrFKqfnKtqOStC9N/6uQ9dYPIBLOLssRuX+YJaYXH2yXlLnpj+773iajx0gNd dlYIqv2R8RXkiVtzueGVwC7MJZS2G+iX4Jt0b5KZcimPGnV/CsxFUeFa3XvWVaVLdb Jtt5mFre8vCmg== Received: by mail-ed1-f52.google.com with SMTP id v1so21243941edt.6; Sun, 18 Jul 2021 16:22:56 -0700 (PDT) X-Gm-Message-State: AOAM532X6lIBOVR7MNbP2LFUhWcSkG5q3TihJ85cbmulF2YoDcb7Ip8N fUyCS8KUYplvsRspm+pIHPc/1IrhF+jSUID3UA== X-Google-Smtp-Source: ABdhPJyLbPQ/bSD5SySNlFUyRdfpkbfYqeHvj8he8EYh2p/ltsGUUyHfnDaoFoD6KhiI5AJDHucNK93+SxE1G7YueM4= X-Received: by 2002:aa7:d353:: with SMTP id m19mr31865120edr.162.1626650575251; Sun, 18 Jul 2021 16:22:55 -0700 (PDT) MIME-Version: 1.0 References: <20210717090408.28283-1-nancy.lin@mediatek.com> <20210717090408.28283-2-nancy.lin@mediatek.com> In-Reply-To: <20210717090408.28283-2-nancy.lin@mediatek.com> From: Chun-Kuang Hu Date: Mon, 19 Jul 2021 07:22:43 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195 To: "Nancy.Lin" Cc: CK Hu , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , Yongqiang Niu , DRI Development , "moderated list:ARM/Mediatek SoC support" , DTML , linux-kernel , Linux ARM , singo.chang@mediatek.com, srv_heupstream Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Nancy: Nancy.Lin =E6=96=BC 2021=E5=B9=B47=E6=9C=8817=E6= =97=A5 =E9=80=B1=E5=85=AD =E4=B8=8B=E5=8D=885:04=E5=AF=AB=E9=81=93=EF=BC=9A > > 1. Add pseudo-ovl definition file for mt8195 display. > 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details. > > Signed-off-by: Nancy.Lin > --- > .../display/mediatek/mediatek,disp.yaml | 5 + > .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++ > 2 files changed, 110 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/me= diatek,pseudo-ovl.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dis= p.yaml > index aac1796e3f6b..bb6d28572b48 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.ya= ml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.ya= ml > @@ -230,6 +230,11 @@ properties: > - items: > - const: mediatek,mt8173-disp-od > > + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediat= ek/mediatek,pseudo-ovl.yaml > + # for details. > + - items: > + - const: mediatek,mt8195-disp-pseudo-ovl > + > reg: > description: Physical base address and length of the function block = register space. > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediat= ek,pseudo-ovl.yaml > new file mode 100644 > index 000000000000..9059d96ce70e > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-= ovl.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.= yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: mediatek pseudo ovl Device Tree Bindings > + > +maintainers: > + - CK Hu > + - Nancy.Lin > + > +description: | > + The Mediatek pseudo ovl function block is composed of eight RDMA and > + four MERGE devices. It's encapsulated as an overlay device, which supp= orts > + 4 layers. > + > +properties: > + compatible: > + oneOf: > + # pseudo ovl controller > + - items: > + - const: mediatek,mt8195-disp-pseudo-ovl > + # RDMA: read DMA > + - items: > + - const: mediatek,mt8195-vdo1-rdma > + # MERGE: merge streams from two RDMA sources > + - items: > + - const: mediatek,mt8195-vdo1-merge > + reg: > + maxItems: 1 > + interrupts: > + maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as arg= ument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml fo= r > + details. > + maxItems: 1 > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce= . > + There are 4 arguments in this property, gce node, subsys id, offse= t and > + register size. The subsys id is defined in the gce header of each = chips > + include/include/dt-bindings/gce/-gce.h, mapping to the regis= ter of > + display function block. > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: > + - mediatek,mt8195-vdo1-merge > + > + then: > + properties: > + clocks: > + items: > + - description: merge clock > + - description: merge async clock > + clock-names: > + items: > + - const: merge > + - const: merge_async > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + > + vdo1_rdma@1c104000 { > + compatible =3D "mediatek,mt8195-vdo1-rdma", > + "mediatek,mt8195-disp-pseudo-ovl"; Do not create pseudo or virtual device, so just leave the "mediatek,mt8195-vdo1-rdma". Regards, Chun-Kuang. > + reg =3D <0 0x1c104000 0 0x1000>; > + interrupts =3D ; > + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; > + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; > + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1c10XXXX 0x4000 0x= 1000>; > + }; > + > + disp_vpp_merge@1c10c000 { > + compatible =3D "mediatek,mt8195-vdo1-merge"; > + reg =3D <0 0x1c10c000 0 0x1000>; > + interrupts =3D ; > + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE0>, > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; > + clock-names =3D "merge","merge_async"; > + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1c10XXXX 0xc000 0x= 1000>; > + }; > + > +... > -- > 2.18.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, 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smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=y31XWIyHpcsTUEdX1uYPQVeZE2xKfuO5e0ovQX/Cx9U=; b=yokfj0K3ZSwesm 5/PPs9/wfVGj10sy+ZUBL8XMVnUZDs6J0lz7YJfKRuDNCF+ZwiFSxewDRSKW1Pb5razzEN31uSGTd CsoDmSI7qL7dqsoK4jRYubP00w9T3TZE43mB65AocTvO/YKK3KtOBSWdGbAoGDi74C/xvwSVwcbbI WrOX6z9nyN/fTZkmQYmcLvqRR4E027cdmEXPsGzf/O0S3GKbjK1207XkL9kQhVeZf/hb4wl8qXeaU TC53qOs8i4pSRp6dQm1xdRu8zDFGueKLLEt1F/ZR8iZyZQzVcgXAb1cc1S+uEyC4CSqBOjC6OMujM OGKzNl2D5R9L9yEPnPtA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by 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ec55so21290005edb.1; Sun, 18 Jul 2021 16:22:56 -0700 (PDT) X-Gm-Message-State: AOAM53280wKB0FVsunPSpcd1S+fcGP6qwmiJqna105nNnyscj5vAV9a5 xIZ4XqGM5vYXMEsavVoSfIsLCgHtFJXnvjcACQ== X-Google-Smtp-Source: ABdhPJyLbPQ/bSD5SySNlFUyRdfpkbfYqeHvj8he8EYh2p/ltsGUUyHfnDaoFoD6KhiI5AJDHucNK93+SxE1G7YueM4= X-Received: by 2002:aa7:d353:: with SMTP id m19mr31865120edr.162.1626650575251; Sun, 18 Jul 2021 16:22:55 -0700 (PDT) MIME-Version: 1.0 References: <20210717090408.28283-1-nancy.lin@mediatek.com> <20210717090408.28283-2-nancy.lin@mediatek.com> In-Reply-To: <20210717090408.28283-2-nancy.lin@mediatek.com> From: Chun-Kuang Hu Date: Mon, 19 Jul 2021 07:22:43 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195 To: "Nancy.Lin" Cc: CK Hu , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , "jason-jh . lin" , Yongqiang Niu , DRI Development , "moderated list:ARM/Mediatek SoC support" , DTML , linux-kernel , Linux ARM , singo.chang@mediatek.com, srv_heupstream X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210718_162257_684733_28EA90DF X-CRM114-Status: GOOD ( 20.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGksIE5hbmN5OgoKTmFuY3kuTGluIDxuYW5jeS5saW5AbWVkaWF0ZWsuY29tPiDmlrwgMjAyMeW5 tDfmnIgxN+aXpSDpgLHlha0g5LiL5Y2INTowNOWvq+mBk++8mgo+Cj4gMS4gQWRkIHBzZXVkby1v dmwgZGVmaW5pdGlvbiBmaWxlIGZvciBtdDgxOTUgZGlzcGxheS4KPiAyLiBBZGQgbWVkaWF0ZWss cHNldWRvLW92bC55YW1sIHRvIGRlY3JpYmUgcHNldWRvLW92bCBtb2R1bGUgaW4gZGV0YWlscy4K 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dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E40989F19; Sun, 18 Jul 2021 23:22:58 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id EED6289F19 for ; Sun, 18 Jul 2021 23:22:56 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 9AF2061073 for ; Sun, 18 Jul 2021 23:22:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626650576; bh=+cIz9IsxTWX0flU1vqzo73L/SPqQutS6FLX3yWrvH3A=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=byKOgNCkjolptKZ8o4CD5FZBcRQ66Zn6YY6qX6/BlieuaheftSXku3KUimj07pzTB SLqyZ4X/+BGySRyq/eQfKJ4SqH5zlC23/VZQJQ3fVM7Jwv9imG53OIhZeTn0ubpFNc 1utIgSgZ2Xf+yaSC5uCFz2t2K96DR5cvDP/nBWkp6cx8zVEm/00vl47M7j5d4wnDR3 vOExrMrFKqfnKtqOStC9N/6uQ9dYPIBLOLssRuX+YJaYXH2yXlLnpj+773iajx0gNd dlYIqv2R8RXkiVtzueGVwC7MJZS2G+iX4Jt0b5KZcimPGnV/CsxFUeFa3XvWVaVLdb Jtt5mFre8vCmg== Received: by mail-ed1-f44.google.com with SMTP id x17so21219636edd.12 for ; Sun, 18 Jul 2021 16:22:56 -0700 (PDT) X-Gm-Message-State: AOAM531IMxNdTUmJSUh/sSHZyl3uVjMTcimujC9tcgTvL5qhUhaH8/Ja F0Tlsf0093GZF30FBt/YwEFsu76lOb7na8s0/w== X-Google-Smtp-Source: ABdhPJyLbPQ/bSD5SySNlFUyRdfpkbfYqeHvj8he8EYh2p/ltsGUUyHfnDaoFoD6KhiI5AJDHucNK93+SxE1G7YueM4= X-Received: by 2002:aa7:d353:: with SMTP id m19mr31865120edr.162.1626650575251; Sun, 18 Jul 2021 16:22:55 -0700 (PDT) MIME-Version: 1.0 References: <20210717090408.28283-1-nancy.lin@mediatek.com> <20210717090408.28283-2-nancy.lin@mediatek.com> In-Reply-To: <20210717090408.28283-2-nancy.lin@mediatek.com> From: Chun-Kuang Hu Date: Mon, 19 Jul 2021 07:22:43 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195 To: "Nancy.Lin" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chun-Kuang Hu , srv_heupstream , DTML , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, linux-kernel , DRI Development , Yongqiang Niu , Matthias Brugger , Rob Herring , "moderated list:ARM/Mediatek SoC support" , Linux ARM Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Nancy: Nancy.Lin =E6=96=BC 2021=E5=B9=B47=E6=9C=8817=E6= =97=A5 =E9=80=B1=E5=85=AD =E4=B8=8B=E5=8D=885:04=E5=AF=AB=E9=81=93=EF=BC=9A > > 1. Add pseudo-ovl definition file for mt8195 display. > 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details. > > Signed-off-by: Nancy.Lin > --- > .../display/mediatek/mediatek,disp.yaml | 5 + > .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++ > 2 files changed, 110 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/me= diatek,pseudo-ovl.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dis= p.yaml > index aac1796e3f6b..bb6d28572b48 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.ya= ml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.ya= ml > @@ -230,6 +230,11 @@ properties: > - items: > - const: mediatek,mt8173-disp-od > > + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediat= ek/mediatek,pseudo-ovl.yaml > + # for details. > + - items: > + - const: mediatek,mt8195-disp-pseudo-ovl > + > reg: > description: Physical base address and length of the function block = register space. > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediat= ek,pseudo-ovl.yaml > new file mode 100644 > index 000000000000..9059d96ce70e > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-= ovl.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.= yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: mediatek pseudo ovl Device Tree Bindings > + > +maintainers: > + - CK Hu > + - Nancy.Lin > + > +description: | > + The Mediatek pseudo ovl function block is composed of eight RDMA and > + four MERGE devices. It's encapsulated as an overlay device, which supp= orts > + 4 layers. > + > +properties: > + compatible: > + oneOf: > + # pseudo ovl controller > + - items: > + - const: mediatek,mt8195-disp-pseudo-ovl > + # RDMA: read DMA > + - items: > + - const: mediatek,mt8195-vdo1-rdma > + # MERGE: merge streams from two RDMA sources > + - items: > + - const: mediatek,mt8195-vdo1-merge > + reg: > + maxItems: 1 > + interrupts: > + maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as arg= ument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml fo= r > + details. > + maxItems: 1 > + clocks: > + maxItems: 2 > + clock-names: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce= . > + There are 4 arguments in this property, gce node, subsys id, offse= t and > + register size. The subsys id is defined in the gce header of each = chips > + include/include/dt-bindings/gce/-gce.h, mapping to the regis= ter of > + display function block. > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: > + - mediatek,mt8195-vdo1-merge > + > + then: > + properties: > + clocks: > + items: > + - description: merge clock > + - description: merge async clock > + clock-names: > + items: > + - const: merge > + - const: merge_async > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + > + vdo1_rdma@1c104000 { > + compatible =3D "mediatek,mt8195-vdo1-rdma", > + "mediatek,mt8195-disp-pseudo-ovl"; Do not create pseudo or virtual device, so just leave the "mediatek,mt8195-vdo1-rdma". Regards, Chun-Kuang. > + reg =3D <0 0x1c104000 0 0x1000>; > + interrupts =3D ; > + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; > + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus =3D <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; > + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1c10XXXX 0x4000 0x= 1000>; > + }; > + > + disp_vpp_merge@1c10c000 { > + compatible =3D "mediatek,mt8195-vdo1-merge"; > + reg =3D <0 0x1c10c000 0 0x1000>; > + interrupts =3D ; > + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE0>, > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; > + clock-names =3D "merge","merge_async"; > + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1c10XXXX 0xc000 0x= 1000>; > + }; > + > +... > -- > 2.18.0 >