* [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v6:
- rebase on kernel-5.15-rc1.
- change mbox label to gce0 for dts node of vdosys1.
- modify mmsys reset num for mt8195.
- rebase on vdosys0 series v10. (ref [5])
- use drm to bring up ovl_adaptor driver.
- move drm iommu/mutex check from kms init to drm bind.
- modify rdma binding doc location. (Documentation/devicetree/bindings/arm/)
- modify for reviewer's comment in v5.
Changes in v5:
- add mmsys reset controller reference.
Changes in v4:
- use merge common driver for merge1~4.
- refine ovl_adaptor rdma driver.
- use ovl_adaptor ddp_comp function instead of ethdr.
- modify for reviewer's comment in v3.
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Changes in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=537069
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=543493
[6] [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210806023606.16867-2-Christine.Zhu@mediatek.com/
[7] [v3,2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid/
[8] [v3,6/7] soc: mediatek: mmsys: Add reset controller support
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid/
Nancy.Lin (16):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195
vdosys1
soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add display MDP RDMA support for MT8195
drm/mediatek: add display merge api support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add ovl_adaptor support for MT8195
drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++
.../display/mediatek/mediatek,ethdr.yaml | 145 +++++
.../display/mediatek/mediatek,merge.yaml | 4 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 ++++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 29 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 90 +++-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 36 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 339 +++++++++---
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 10 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 +++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 +
drivers/soc/mediatek/mt8195-mmsys.h | 199 +++++++
drivers/soc/mediatek/mtk-mmsys.c | 80 ++-
drivers/soc/mediatek/mtk-mmsys.h | 12 +
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++-----
include/dt-bindings/reset/mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 22 +
24 files changed, 2621 insertions(+), 241 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
--
2.18.0
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v6:
- rebase on kernel-5.15-rc1.
- change mbox label to gce0 for dts node of vdosys1.
- modify mmsys reset num for mt8195.
- rebase on vdosys0 series v10. (ref [5])
- use drm to bring up ovl_adaptor driver.
- move drm iommu/mutex check from kms init to drm bind.
- modify rdma binding doc location. (Documentation/devicetree/bindings/arm/)
- modify for reviewer's comment in v5.
Changes in v5:
- add mmsys reset controller reference.
Changes in v4:
- use merge common driver for merge1~4.
- refine ovl_adaptor rdma driver.
- use ovl_adaptor ddp_comp function instead of ethdr.
- modify for reviewer's comment in v3.
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Changes in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=537069
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=543493
[6] [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210806023606.16867-2-Christine.Zhu@mediatek.com/
[7] [v3,2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid/
[8] [v3,6/7] soc: mediatek: mmsys: Add reset controller support
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid/
Nancy.Lin (16):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195
vdosys1
soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add display MDP RDMA support for MT8195
drm/mediatek: add display merge api support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add ovl_adaptor support for MT8195
drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++
.../display/mediatek/mediatek,ethdr.yaml | 145 +++++
.../display/mediatek/mediatek,merge.yaml | 4 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 ++++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 29 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 90 +++-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 36 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 339 +++++++++---
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 10 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 +++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 +
drivers/soc/mediatek/mt8195-mmsys.h | 199 +++++++
drivers/soc/mediatek/mtk-mmsys.c | 80 ++-
drivers/soc/mediatek/mtk-mmsys.h | 12 +
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++-----
include/dt-bindings/reset/mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 22 +
24 files changed, 2621 insertions(+), 241 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through by several modules, such as, OVL_ADAPTOR and MERGE.
Add DRM and these modules support by the patches below:
Changes in v6:
- rebase on kernel-5.15-rc1.
- change mbox label to gce0 for dts node of vdosys1.
- modify mmsys reset num for mt8195.
- rebase on vdosys0 series v10. (ref [5])
- use drm to bring up ovl_adaptor driver.
- move drm iommu/mutex check from kms init to drm bind.
- modify rdma binding doc location. (Documentation/devicetree/bindings/arm/)
- modify for reviewer's comment in v5.
Changes in v5:
- add mmsys reset controller reference.
Changes in v4:
- use merge common driver for merge1~4.
- refine ovl_adaptor rdma driver.
- use ovl_adaptor ddp_comp function instead of ethdr.
- modify for reviewer's comment in v3.
Changes in v3:
- modify for reviewer's comment in v2.
- add vdosys1 2 pixels align limit.
- add mixer odd offset support.
Changes in v2:
- Merge PSEUDO_OVL and ETHDR into one DRM component.
- Add mmsys config API for vdosys1 hardware setting.
- Add mmsys reset control using linux reset framework.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=537069
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=543493
[6] [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file
https://patchwork.kernel.org/project/linux-mediatek/patch/20210806023606.16867-2-Christine.Zhu@mediatek.com/
[7] [v3,2/7] dt-bindings: mediatek: Add #reset-cells to mmsys system controller
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid/
[8] [v3,6/7] soc: mediatek: mmsys: Add reset controller support
https://patchwork.kernel.org/project/linux-mediatek/patch/20210825122613.v3.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid/
Nancy.Lin (16):
dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
dt-bindings: mediatek: add ethdr definition for mt8195
dt-bindings: reset: mt8195: add vdosys1 reset control bit
arm64: dts: mt8195: add display node for vdosys1
soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195
vdosys1
soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
soc: mediatek: add mtk-mutex support for mt8195 vdosys1
drm/mediatek: add display MDP RDMA support for MT8195
drm/mediatek: add display merge api support for MT8195
drm/mediatek: add ETHDR support for MT8195
drm/mediatek: add ovl_adaptor support for MT8195
drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++
.../display/mediatek/mediatek,ethdr.yaml | 145 +++++
.../display/mediatek/mediatek,merge.yaml | 4 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 ++++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 29 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 90 +++-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 36 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 339 +++++++++---
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 10 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 +++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 +
drivers/soc/mediatek/mt8195-mmsys.h | 199 +++++++
drivers/soc/mediatek/mtk-mmsys.c | 80 ++-
drivers/soc/mediatek/mtk-mmsys.h | 12 +
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++-----
include/dt-bindings/reset/mt8195-resets.h | 12 +
include/linux/soc/mediatek/mtk-mmsys.h | 22 +
24 files changed, 2621 insertions(+), 241 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..fd8fe2071c21
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MDP RDMA
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ The mediatek MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..fd8fe2071c21
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MDP RDMA
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ The mediatek MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 RDMA definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../arm/mediatek/mediatek,mdp-rdma.yaml | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
new file mode 100644
index 000000000000..fd8fe2071c21
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mdp-rdma.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MDP RDMA
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ The mediatek MDP RDMA stands for Read Direct Memory Access.
+ It provides real time data to the back-end panel driver, such as DSI,
+ DPI and DP_INTF.
+ It contains one line buffer to store the sufficient pixel data.
+ RDMA device node must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ clocks:
+ items:
+ - description: RDMA Clock
+
+ iommus:
+ description:
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 merge1 to merge4 have HW mute function.
Add MERGE additional mute property description.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 6007e00679a8..d7d0eda813d1 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -54,6 +54,10 @@ properties:
command to SMI to speed up the data rate.
type: boolean
+ mediatek,merge-mute:
+ description: Support mute function. Mute the content of merge output.
+ type: boolean
+
mediatek,gce-client-reg:
description:
The register of client driver can be configured by gce with 4 arguments
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 merge1 to merge4 have HW mute function.
Add MERGE additional mute property description.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 6007e00679a8..d7d0eda813d1 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -54,6 +54,10 @@ properties:
command to SMI to speed up the data rate.
type: boolean
+ mediatek,merge-mute:
+ description: Support mute function. Mute the content of merge output.
+ type: boolean
+
mediatek,gce-client-reg:
description:
The register of client driver can be configured by gce with 4 arguments
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 merge1 to merge4 have HW mute function.
Add MERGE additional mute property description.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 6007e00679a8..d7d0eda813d1 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -54,6 +54,10 @@ properties:
command to SMI to speed up the data rate.
type: boolean
+ mediatek,merge-mute:
+ description: Support mute function. Mute the content of merge output.
+ type: boolean
+
mediatek,gce-client-reg:
description:
The register of client driver can be configured by gce with 4 arguments
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..e127f0b392d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Ethdr Device Tree Bindings
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..e127f0b392d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Ethdr Device Tree Bindings
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 ETHDR definition.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..e127f0b392d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Ethdr Device Tree Bindings
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ resets:
+ maxItems: 5
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..aab8d74496a6 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..aab8d74496a6 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index a26bccc8b957..aab8d74496a6 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -26,4 +26,16 @@
#define MT8195_TOPRGU_SW_RST_NUM 16
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 +++++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e136761345db..9c44829b2727 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,22 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ ethdr0 = ðdr0;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1235,7 +1252,212 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ ethdr0: disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 +++++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e136761345db..9c44829b2727 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,22 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ ethdr0 = ðdr0;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1235,7 +1252,212 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ ethdr0: disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 222 +++++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e136761345db..9c44829b2727 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
+#include <dt-bindings/reset/mt8195-resets.h>
/ {
compatible = "mediatek,mt8195";
@@ -20,6 +21,22 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ ethdr0 = ðdr0;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1235,7 +1252,212 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ mediatek,merge-mute = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
+ };
+
+ merge5: disp_vpp_merge@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
+
+ ethdr0: disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
};
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0c97a5f016c1..f19ec72c1243 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 56b9342256da..4da11b2911a5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -69,6 +69,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -258,6 +264,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 64c77c4a6c56..eaf7f7345519 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -39,6 +40,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0c97a5f016c1..f19ec72c1243 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 56b9342256da..4da11b2911a5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -69,6 +69,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -258,6 +264,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 64c77c4a6c56..eaf7f7345519 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -39,6 +40,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 10 ++
include/linux/soc/mediatek/mtk-mmsys.h | 2 +
3 files changed, 148 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0c97a5f016c1..f19ec72c1243 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -59,6 +59,70 @@
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define MT8195_SOUT_TO_MIXER_IN1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define MT8195_SOUT_TO_MIXER_IN2_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define MT8195_SOUT_TO_MIXER_IN3_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define MT8195_SOUT_TO_MIXER_IN4_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -108,6 +172,78 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
+ MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN1_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN2_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN3_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
+ MT8195_SOUT_TO_MIXER_IN4_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
+ MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
+ MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
+ MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ }, {
+ DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
+ MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DPI1_SEL
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
+ MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
+ MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 56b9342256da..4da11b2911a5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -69,6 +69,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -258,6 +264,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 64c77c4a6c56..eaf7f7345519 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -18,6 +18,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
DDP_COMPONENT_DSC0,
@@ -39,6 +40,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_OVL_ADAPTOR,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 34 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 122 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index f19ec72c1243..648baaec112b 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4da11b2911a5..f9f18ee81efb 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -73,6 +73,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -178,6 +180,38 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
.reset = mtk_mmsys_reset,
};
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+ u32 tmp;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..2694021435d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -88,10 +88,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index eaf7f7345519..b2d2310d7e7a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -56,6 +56,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -64,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 34 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 122 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index f19ec72c1243..648baaec112b 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4da11b2911a5..f9f18ee81efb 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -73,6 +73,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -178,6 +180,38 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
.reset = mtk_mmsys_reset,
};
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+ u32 tmp;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..2694021435d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -88,10 +88,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index eaf7f7345519..b2d2310d7e7a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -56,6 +56,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -64,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mmsys config API. The config API is used for config mmsys reg.
Some mmsys regs need to be setting according to the HW engine binding
to the mmsys simultaneously.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 62 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 34 ++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 10 +++++
include/linux/soc/mediatek/mtk-mmsys.h | 16 +++++++
4 files changed, 122 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index f19ec72c1243..648baaec112b 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,21 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
+#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
+#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
+#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD 0xe60
+#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
+#define MT8195_VDO1_HDR_TOP_CFG 0xd00
+#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
+#define MT8195_VDO1_MIXER_IN2_ALPHA 0xd34
+#define MT8195_VDO1_MIXER_IN3_ALPHA 0xd38
+#define MT8195_VDO1_MIXER_IN4_ALPHA 0xd3c
+#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
+#define MT8195_VDO1_MIXER_IN2_PAD 0xd44
+#define MT8195_VDO1_MIXER_IN3_PAD 0xd48
+#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c
+
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
{
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
@@ -247,4 +262,51 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/*
+ * mtk_mmsys_config table is used for config mmsys reg in runtime.
+ * MMSYS_CONFIG_MERGE_ASYNC_WIDTH: config merge async width
+ * MMSYS_CONFIG_MERGE_ASYNC_HEIGHT: config merge async height
+ * MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH: config hdr_be async width
+ * MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT: config hdr_be async height
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_ODD: config mixer odd channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN: config mixer even channel 9bit alpha value
+ * MMSYS_CONFIG_MIXER_IN_CH_SWAP: config mixer input RGB channel swap
+ * MMSYS_CONFIG_HDR_ALPHA_SEL: config alpha source
+ * MMSYS_CONFIG_MIXER_IN_MODE: config mixer pad mode(bypass/even extend mode)
+ * MMSYS_CONFIG_MIXER_IN_BIWIDTH: config mixer pad width. formula: width / 2 - 1
+ */
+static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
+ { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
+ { MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_MODE, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(1, 0), 0},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 1, MT8195_VDO1_MIXER_IN1_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 2, MT8195_VDO1_MIXER_IN2_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 3, MT8195_VDO1_MIXER_IN3_PAD, GENMASK(31, 16), 16},
+ { MMSYS_CONFIG_MIXER_IN_BIWIDTH, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(31, 16), 16},
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4da11b2911a5..f9f18ee81efb 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -73,6 +73,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
.routes = mmsys_mt8195_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+ .config = mmsys_mt8195_config_table,
+ .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -178,6 +180,38 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
.reset = mtk_mmsys_reset,
};
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
+ u32 reg_val;
+ u32 mask;
+ u32 offset;
+ int i;
+ u32 tmp;
+
+ if (!mmsys->data->num_configs)
+ return;
+
+ for (i = 0; i < mmsys->data->num_configs; i++)
+ if (config == mmsys_config[i].config && id == mmsys_config[i].id)
+ break;
+
+ if (i == mmsys->data->num_configs)
+ return;
+
+ offset = mmsys_config[i].addr;
+ mask = mmsys_config[i].mask;
+ reg_val = val << mmsys_config[i].shift;
+
+ tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 8b0ed05117ea..2694021435d2 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -88,10 +88,20 @@ struct mtk_mmsys_routes {
u32 val;
};
+struct mtk_mmsys_config {
+ enum mtk_mmsys_config_type config;
+ u32 id;
+ u32 addr;
+ u32 mask;
+ u32 shift;
+};
+
struct mtk_mmsys_driver_data {
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
+ const struct mtk_mmsys_config *config;
+ const unsigned int num_configs;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index eaf7f7345519..b2d2310d7e7a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -56,6 +56,19 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mmsys_config_type {
+ MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
+ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
+ MMSYS_CONFIG_HDR_ALPHA_SEL,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
+ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
+ MMSYS_CONFIG_MIXER_IN_CH_SWAP,
+ MMSYS_CONFIG_MIXER_IN_MODE,
+ MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -64,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
+ u32 id, u32 val);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 08/16] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 29 ++++++++++++++++++++------
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f9f18ee81efb..7802c2239874 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -88,6 +88,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -181,7 +182,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
};
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -189,7 +190,6 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
u32 mask;
u32 offset;
int i;
- u32 tmp;
if (!mmsys->data->num_configs)
return;
@@ -205,10 +205,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -244,6 +254,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index b2d2310d7e7a..3e998bfb795a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 08/16] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 29 ++++++++++++++++++++------
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f9f18ee81efb..7802c2239874 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -88,6 +88,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -181,7 +182,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
};
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -189,7 +190,6 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
u32 mask;
u32 offset;
int i;
- u32 tmp;
if (!mmsys->data->num_configs)
return;
@@ -205,10 +205,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -244,6 +254,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index b2d2310d7e7a..3e998bfb795a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 08/16] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add cmdq support for mtk-mmsys config API.
The mmsys config register settings need to take effect with the other
HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the
settings can be written in the same vblanking time.
Cmdq is used for this purpose. We prepare all the related HW settings
in one cmdq packet. The first command in the packet is "wait stream done",
and then following with all the HW settings. After the cmdq packet is
flush to GCE HW. The GCE waits for the "stream done event" to coming
and then starts flushing all the HW settings. This can guarantee all
the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 29 ++++++++++++++++++++------
include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index f9f18ee81efb..7802c2239874 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -88,6 +88,7 @@ struct mtk_mmsys {
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ struct cmdq_client_reg cmdq_base;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -181,7 +182,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
};
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val)
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
@@ -189,7 +190,6 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
u32 mask;
u32 offset;
int i;
- u32 tmp;
if (!mmsys->data->num_configs)
return;
@@ -205,10 +205,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
mask = mmsys_config[i].mask;
reg_val = val << mmsys_config[i].shift;
- tmp = readl(mmsys->regs + offset);
-
- tmp = (tmp & ~mask) | reg_val;
- writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_pkt && mmsys->cmdq_base.size) {
+ cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
+ mmsys->cmdq_base.offset + offset, reg_val,
+ mask);
+ } else {
+#endif
+ u32 tmp = readl(mmsys->regs + offset);
+
+ tmp = (tmp & ~mask) | reg_val;
+ writel(tmp, mmsys->regs + offset);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ }
+#endif
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -244,6 +254,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
}
mmsys->data = of_device_get_match_data(&pdev->dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
+ if (ret)
+ dev_dbg(dev, "No mediatek,gce-client-reg!\n");
+#endif
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index b2d2310d7e7a..3e998bfb795a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -6,6 +6,10 @@
#ifndef __MTK_MMSYS_H
#define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
enum mtk_ddp_comp_id;
struct device;
@@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
- u32 id, u32 val);
+ u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
drivers/soc/mediatek/mtk-mmsys.h | 2 ++
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 648baaec112b..f67801c42fd9 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7802c2239874..8a6556892e60 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -19,6 +19,8 @@
#include "mt8192-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -49,12 +51,16 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -75,6 +81,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
+ .num_resets = 64,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -133,19 +141,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
+ u32 offset;
u32 reg;
int i;
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
spin_lock_irqsave(&mmsys->lock, flags);
- reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
if (assert)
reg &= ~BIT(id);
else
reg |= BIT(id);
- writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
spin_unlock_irqrestore(&mmsys->lock, flags);
@@ -241,10 +253,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ mmsys->data = of_device_get_match_data(&pdev->dev);
spin_lock_init(&mmsys->lock);
mmsys->rcdev.owner = THIS_MODULE;
- mmsys->rcdev.nr_resets = 32;
+ mmsys->rcdev.nr_resets = mmsys->data->num_resets;
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
mmsys->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
@@ -253,8 +266,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
-
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 2694021435d2..4842102cd451 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,8 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
+ u32 num_resets;
};
/*
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
drivers/soc/mediatek/mtk-mmsys.h | 2 ++
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 648baaec112b..f67801c42fd9 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7802c2239874..8a6556892e60 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -19,6 +19,8 @@
#include "mt8192-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -49,12 +51,16 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -75,6 +81,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
+ .num_resets = 64,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -133,19 +141,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
+ u32 offset;
u32 reg;
int i;
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
spin_lock_irqsave(&mmsys->lock, flags);
- reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
if (assert)
reg &= ~BIT(id);
else
reg |= BIT(id);
- writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
spin_unlock_irqrestore(&mmsys->lock, flags);
@@ -241,10 +253,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ mmsys->data = of_device_get_match_data(&pdev->dev);
spin_lock_init(&mmsys->lock);
mmsys->rcdev.owner = THIS_MODULE;
- mmsys->rcdev.nr_resets = 32;
+ mmsys->rcdev.nr_resets = mmsys->data->num_resets;
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
mmsys->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
@@ -253,8 +266,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
-
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 2694021435d2..4842102cd451 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,8 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
+ u32 num_resets;
};
/*
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 vdosys1 has more than 32 reset bits and a different reset base
than other chips. Modify mmsys for support 64 bit and different reset
base.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 1 +
drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
drivers/soc/mediatek/mtk-mmsys.h | 2 ++
3 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 648baaec112b..f67801c42fd9 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -123,6 +123,7 @@
#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MT8195_VDO1_SW0_RST_B 0x1d0
#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 7802c2239874..8a6556892e60 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -19,6 +19,8 @@
#include "mt8192-mmsys.h"
#include "mt8195-mmsys.h"
+#define MMSYS_SW_RESET_PER_REG 32
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
.routes = mmsys_default_routing_table,
@@ -49,12 +51,16 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .sw_reset_start = MMSYS_SW0_RST_B,
+ .num_resets = 32,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -75,6 +81,8 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
.config = mmsys_mt8195_config_table,
.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
+ .sw_reset_start = MT8195_VDO1_SW0_RST_B,
+ .num_resets = 64,
};
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
@@ -133,19 +141,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
{
struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
unsigned long flags;
+ u32 offset;
u32 reg;
int i;
+ offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
+ id = id % MMSYS_SW_RESET_PER_REG;
+
spin_lock_irqsave(&mmsys->lock, flags);
- reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
+ reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
if (assert)
reg &= ~BIT(id);
else
reg |= BIT(id);
- writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
+ writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
spin_unlock_irqrestore(&mmsys->lock, flags);
@@ -241,10 +253,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ mmsys->data = of_device_get_match_data(&pdev->dev);
spin_lock_init(&mmsys->lock);
mmsys->rcdev.owner = THIS_MODULE;
- mmsys->rcdev.nr_resets = 32;
+ mmsys->rcdev.nr_resets = mmsys->data->num_resets;
mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
mmsys->rcdev.of_node = pdev->dev.of_node;
ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
@@ -253,8 +266,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
-
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
if (ret)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 2694021435d2..4842102cd451 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -102,6 +102,8 @@ struct mtk_mmsys_driver_data {
const unsigned int num_routes;
const struct mtk_mmsys_config *config;
const unsigned int num_configs;
+ u32 sw_reset_start;
+ u32 num_resets;
};
/*
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
1 file changed, 175 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..7767fedbd14f 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,142 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +212,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +227,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +236,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +256,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +271,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +289,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +303,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +317,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -302,6 +331,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -466,17 +516,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -506,22 +559,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
1 file changed, 175 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..7767fedbd14f 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,142 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +212,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +227,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +236,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +256,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +271,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +289,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +303,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +317,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -302,6 +331,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -466,17 +516,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -506,22 +559,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
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^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains ovl_adaptor, merge5,
and dp_intf1. Ovl_adaptor is composed of several sub-elements,
so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
1 file changed, 175 insertions(+), 121 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 36502b27fe20..7767fedbd14f 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,113 +29,142 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8192_MUTEX_MOD_DISP_OVL0 0
-#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
-#define MT8192_MUTEX_MOD_DISP_RDMA0 2
-#define MT8192_MUTEX_MOD_DISP_COLOR0 4
-#define MT8192_MUTEX_MOD_DISP_CCORR0 5
-#define MT8192_MUTEX_MOD_DISP_AAL0 6
-#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
-#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
-#define MT8192_MUTEX_MOD_DISP_DITHER0 9
-#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
-#define MT8192_MUTEX_MOD_DISP_RDMA4 17
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8192_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L BIT(1)
+#define MT8192_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8192_MUTEX_MOD_DISP_COLOR0 BIT(4)
+#define MT8192_MUTEX_MOD_DISP_CCORR0 BIT(5)
+#define MT8192_MUTEX_MOD_DISP_AAL0 BIT(6)
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 BIT(7)
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 BIT(8)
+#define MT8192_MUTEX_MOD_DISP_DITHER0 BIT(9)
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L BIT(16)
+#define MT8192_MUTEX_MOD_DISP_RDMA4 BIT(17)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -183,7 +212,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -198,7 +227,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -207,7 +236,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -227,7 +256,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -242,7 +271,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -260,7 +289,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -274,7 +303,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
@@ -288,7 +317,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -302,6 +331,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+ [DDP_COMPONENT_OVL_ADAPTOR] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -466,17 +516,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DP_INTF0:
sof_id = MUTEX_SOF_DP_INTF0;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -506,22 +559,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
case DDP_COMPONENT_DP_INTF0:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
4 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a38e88e82d12..6e604a933ed0 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index a33b13fe2b6e..b3a372cab0bd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
int mtk_aal_clk_enable(struct device *dev);
void mtk_aal_clk_disable(struct device *dev);
@@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_mdp_rdma_clk_enable(struct device *dev);
+void mtk_mdp_rdma_clk_disable(struct device *dev);
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt);
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..d05b1ef976bc
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE BIT(0)
+#define MDP_RDMA_RESET 0x008
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B BIT(5)
+#define FLD_SIMPLE_MODE BIT(4)
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_COMMAND_DIV BIT(0)
+#define FLD_EXT_PREULTRA_EN BIT(3)
+#define FLD_RD_REQ_TYPE GENMASK(7, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_ULTRA_EN GENMASK(13, 12)
+#define VAL_ULTRA_EN_ENABLE 1
+#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
+#define VAL_PRE_ULTRA_EN_ENABLE 1
+#define FLD_EXT_ULTRA_EN BIT(18)
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB BIT(25)
+#define FLD_BIT_NUMBER GENMASK(19, 18)
+#define FLD_SWAP BIT(14)
+#define FLD_UNIFORM_CONFIG BIT(17)
+#define RDMA_INPUT_10BIT BIT(18)
+#define FLD_SRC_FORMAT GENMASK(3, 0)
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN BIT(22)
+#define FLD_AFBC_YUV_TRANSFORM BIT(21)
+#define FLD_UFBDC_EN BIT(12)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB GENMASK(22, 0)
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H GENMASK(30, 16)
+#define FLD_MF_SRC_W GENMASK(14, 0)
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H GENMASK(30, 16)
+#define FLD_MF_CLIP_W GENMASK(14, 0)
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
+#define FLD_TRANS_EN BIT(16)
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 GENMASK(31, 0)
+
+#define RDMA_CSC_FULL709_TO_RGB 5
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+struct mtk_mdp_rdma {
+ void __iomem *regs;
+ struct clk *clk;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
+ VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
+ FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
+}
+
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+}
+
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ bool csc_enable = fmt_info->is_yuv ? true : false;
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
+
+ if (!csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+ else
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
+ FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_OUTPUT_10B);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_SIMPLE_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
+}
+
+int mtk_mdp_rdma_clk_enable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ clk_prepare_enable(rdma->clk);
+ return 0;
+}
+
+void mtk_mdp_rdma_clk_disable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rdma->clk);
+ pm_runtime_put(dev);
+}
+
+static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_mdp_rdma_component_ops = {
+ .bind = mtk_mdp_rdma_bind,
+ .unbind = mtk_mdp_rdma_unbind,
+};
+
+static int mtk_mdp_rdma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_mdp_rdma *priv;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap rdma\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get rdma clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_mdp_rdma_component_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+ return ret;
+}
+
+static int mtk_mdp_rdma_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-vdo1-rdma", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
+
+struct platform_driver mtk_mdp_rdma_driver = {
+ .probe = mtk_mdp_rdma_probe,
+ .remove = mtk_mdp_rdma_remove,
+ .driver = {
+ .name = "mediatek-mdp-rdma",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_mdp_rdma_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_mdp_rdma_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..868e8ca40de3
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+struct mtk_mdp_rdma_cfg {
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
4 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a38e88e82d12..6e604a933ed0 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index a33b13fe2b6e..b3a372cab0bd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
int mtk_aal_clk_enable(struct device *dev);
void mtk_aal_clk_disable(struct device *dev);
@@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_mdp_rdma_clk_enable(struct device *dev);
+void mtk_mdp_rdma_clk_disable(struct device *dev);
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt);
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..d05b1ef976bc
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE BIT(0)
+#define MDP_RDMA_RESET 0x008
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B BIT(5)
+#define FLD_SIMPLE_MODE BIT(4)
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_COMMAND_DIV BIT(0)
+#define FLD_EXT_PREULTRA_EN BIT(3)
+#define FLD_RD_REQ_TYPE GENMASK(7, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_ULTRA_EN GENMASK(13, 12)
+#define VAL_ULTRA_EN_ENABLE 1
+#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
+#define VAL_PRE_ULTRA_EN_ENABLE 1
+#define FLD_EXT_ULTRA_EN BIT(18)
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB BIT(25)
+#define FLD_BIT_NUMBER GENMASK(19, 18)
+#define FLD_SWAP BIT(14)
+#define FLD_UNIFORM_CONFIG BIT(17)
+#define RDMA_INPUT_10BIT BIT(18)
+#define FLD_SRC_FORMAT GENMASK(3, 0)
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN BIT(22)
+#define FLD_AFBC_YUV_TRANSFORM BIT(21)
+#define FLD_UFBDC_EN BIT(12)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB GENMASK(22, 0)
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H GENMASK(30, 16)
+#define FLD_MF_SRC_W GENMASK(14, 0)
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H GENMASK(30, 16)
+#define FLD_MF_CLIP_W GENMASK(14, 0)
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
+#define FLD_TRANS_EN BIT(16)
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 GENMASK(31, 0)
+
+#define RDMA_CSC_FULL709_TO_RGB 5
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+struct mtk_mdp_rdma {
+ void __iomem *regs;
+ struct clk *clk;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
+ VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
+ FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
+}
+
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+}
+
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ bool csc_enable = fmt_info->is_yuv ? true : false;
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
+
+ if (!csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+ else
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
+ FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_OUTPUT_10B);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_SIMPLE_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
+}
+
+int mtk_mdp_rdma_clk_enable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ clk_prepare_enable(rdma->clk);
+ return 0;
+}
+
+void mtk_mdp_rdma_clk_disable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rdma->clk);
+ pm_runtime_put(dev);
+}
+
+static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_mdp_rdma_component_ops = {
+ .bind = mtk_mdp_rdma_bind,
+ .unbind = mtk_mdp_rdma_unbind,
+};
+
+static int mtk_mdp_rdma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_mdp_rdma *priv;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap rdma\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get rdma clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_mdp_rdma_component_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+ return ret;
+}
+
+static int mtk_mdp_rdma_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-vdo1-rdma", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
+
+struct platform_driver mtk_mdp_rdma_driver = {
+ .probe = mtk_mdp_rdma_probe,
+ .remove = mtk_mdp_rdma_remove,
+ .driver = {
+ .name = "mediatek-mdp-rdma",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_mdp_rdma_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_mdp_rdma_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..868e8ca40de3
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+struct mtk_mdp_rdma_cfg {
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
the ovl_adaptor component.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
4 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a38e88e82d12..6e604a933ed0 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index a33b13fe2b6e..b3a372cab0bd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -8,6 +8,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_plane.h"
+#include "mtk_mdp_rdma.h"
int mtk_aal_clk_enable(struct device *dev);
void mtk_aal_clk_disable(struct device *dev);
@@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_mdp_rdma_clk_enable(struct device *dev);
+void mtk_mdp_rdma_clk_disable(struct device *dev);
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt);
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..d05b1ef976bc
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+#include "mtk_mdp_rdma.h"
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE BIT(0)
+#define MDP_RDMA_RESET 0x008
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B BIT(5)
+#define FLD_SIMPLE_MODE BIT(4)
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_COMMAND_DIV BIT(0)
+#define FLD_EXT_PREULTRA_EN BIT(3)
+#define FLD_RD_REQ_TYPE GENMASK(7, 4)
+#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
+#define FLD_ULTRA_EN GENMASK(13, 12)
+#define VAL_ULTRA_EN_ENABLE 1
+#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
+#define VAL_PRE_ULTRA_EN_ENABLE 1
+#define FLD_EXT_ULTRA_EN BIT(18)
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB BIT(25)
+#define FLD_BIT_NUMBER GENMASK(19, 18)
+#define FLD_SWAP BIT(14)
+#define FLD_UNIFORM_CONFIG BIT(17)
+#define RDMA_INPUT_10BIT BIT(18)
+#define FLD_SRC_FORMAT GENMASK(3, 0)
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN BIT(22)
+#define FLD_AFBC_YUV_TRANSFORM BIT(21)
+#define FLD_UFBDC_EN BIT(12)
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB GENMASK(22, 0)
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H GENMASK(30, 16)
+#define FLD_MF_SRC_W GENMASK(14, 0)
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H GENMASK(30, 16)
+#define FLD_MF_CLIP_W GENMASK(14, 0)
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
+#define FLD_TRANS_EN BIT(16)
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 GENMASK(31, 0)
+
+#define RDMA_CSC_FULL709_TO_RGB 5
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+struct mtk_mdp_rdma {
+ void __iomem *regs;
+ struct clk *clk;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
+ VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
+ FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
+ FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
+}
+
+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+}
+
+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
+}
+
+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
+ const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
+ bool csc_enable = fmt_info->is_yuv ? true : false;
+ unsigned int src_pitch_y = cfg->pitch;
+ unsigned int bpp_y = fmt_info->cpp[0] * 8;
+ unsigned int offset_y = 0;
+
+ mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
+
+ mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
+
+ if (!csc_enable && fmt_info->has_alpha)
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
+ priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+ else
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
+ FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_OUTPUT_10B);
+ mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_CON, FLD_SIMPLE_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
+
+ mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
+ mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
+ MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
+}
+
+int mtk_mdp_rdma_clk_enable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ clk_prepare_enable(rdma->clk);
+ return 0;
+}
+
+void mtk_mdp_rdma_clk_disable(struct device *dev)
+{
+ struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(rdma->clk);
+ pm_runtime_put(dev);
+}
+
+static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_mdp_rdma_component_ops = {
+ .bind = mtk_mdp_rdma_bind,
+ .unbind = mtk_mdp_rdma_unbind,
+};
+
+static int mtk_mdp_rdma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_mdp_rdma *priv;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap rdma\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get rdma clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_mdp_rdma_component_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+ return ret;
+}
+
+static int mtk_mdp_rdma_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-vdo1-rdma", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
+
+struct platform_driver mtk_mdp_rdma_driver = {
+ .probe = mtk_mdp_rdma_probe,
+ .remove = mtk_mdp_rdma_remove,
+ .driver = {
+ .name = "mediatek-mdp-rdma",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_mdp_rdma_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_mdp_rdma_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..868e8ca40de3
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+struct mtk_mdp_rdma_cfg {
+ unsigned int pitch;
+ unsigned int addr0;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ int fmt;
+};
+
+#endif // __MTK_MDP_RDMA_H__
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
2 files changed, 82 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index b3a372cab0bd..2446ad0a4977 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index b05e1df79c3d..696bb948352b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -17,6 +17,7 @@
#define DISP_REG_MERGE_CTRL 0x000
#define MERGE_EN 1
#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_1 0x014
#define DISP_REG_MERGE_CFG_4 0x020
#define DISP_REG_MERGE_CFG_10 0x038
/* no swap */
@@ -25,9 +26,12 @@
#define DISP_REG_MERGE_CFG_12 0x040
#define CFG_10_10_1PI_2PO_BUF_MODE 6
#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define CFG_11_10_1PI_2PO_MERGE 18
#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
#define DISP_REG_MERGE_CFG_24 0x070
#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_26 0x078
+#define DISP_REG_MERGE_CFG_27 0x07c
#define DISP_REG_MERGE_CFG_36 0x0a0
#define ULTRA_EN BIT(0)
#define PREULTRA_EN BIT(4)
@@ -54,26 +58,52 @@
#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_MUTE_0 0xf00
+
struct mtk_disp_merge {
void __iomem *regs;
struct clk *clk;
struct clk *async_clk;
struct cmdq_client_reg cmdq_reg;
bool fifo_en;
+ bool mute_support;
};
void mtk_merge_start(struct device *dev)
+{
+ mtk_merge_enable(dev, NULL);
+}
+
+void mtk_merge_stop(struct device *dev)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_merge_disable(dev, NULL);
}
-void mtk_merge_stop(struct device *dev)
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->mute_support)
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_MUTE_0);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
@@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
void mtk_merge_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
- if (!h || !w) {
- dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ if (!h || !l_w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
return;
}
@@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
mode = CFG_10_10_2PI_2PO_BUF_MODE;
}
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ if (r_w)
+ mode = CFG_11_10_1PI_2PO_MERGE;
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_0);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_4);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ /*
+ * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
+ * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
+ * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
+ * the input0 goes to SRAM0, and input1 goes to SRAM1.
+ * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
+ * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_24);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
- DISP_REG_MERGE_CFG_25);
+ if (r_w)
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ else
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+
+ /*
+ * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
+ * Only take effect when the merge is setting to merge mode.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_27);
+
mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
@@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->mute_support = of_property_read_bool(dev->of_node,
+ "mediatek,merge-mute");
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
2 files changed, 82 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index b3a372cab0bd..2446ad0a4977 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index b05e1df79c3d..696bb948352b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -17,6 +17,7 @@
#define DISP_REG_MERGE_CTRL 0x000
#define MERGE_EN 1
#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_1 0x014
#define DISP_REG_MERGE_CFG_4 0x020
#define DISP_REG_MERGE_CFG_10 0x038
/* no swap */
@@ -25,9 +26,12 @@
#define DISP_REG_MERGE_CFG_12 0x040
#define CFG_10_10_1PI_2PO_BUF_MODE 6
#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define CFG_11_10_1PI_2PO_MERGE 18
#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
#define DISP_REG_MERGE_CFG_24 0x070
#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_26 0x078
+#define DISP_REG_MERGE_CFG_27 0x07c
#define DISP_REG_MERGE_CFG_36 0x0a0
#define ULTRA_EN BIT(0)
#define PREULTRA_EN BIT(4)
@@ -54,26 +58,52 @@
#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_MUTE_0 0xf00
+
struct mtk_disp_merge {
void __iomem *regs;
struct clk *clk;
struct clk *async_clk;
struct cmdq_client_reg cmdq_reg;
bool fifo_en;
+ bool mute_support;
};
void mtk_merge_start(struct device *dev)
+{
+ mtk_merge_enable(dev, NULL);
+}
+
+void mtk_merge_stop(struct device *dev)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_merge_disable(dev, NULL);
}
-void mtk_merge_stop(struct device *dev)
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->mute_support)
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_MUTE_0);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
@@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
void mtk_merge_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
- if (!h || !w) {
- dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ if (!h || !l_w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
return;
}
@@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
mode = CFG_10_10_2PI_2PO_BUF_MODE;
}
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ if (r_w)
+ mode = CFG_11_10_1PI_2PO_MERGE;
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_0);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_4);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ /*
+ * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
+ * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
+ * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
+ * the input0 goes to SRAM0, and input1 goes to SRAM1.
+ * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
+ * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_24);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
- DISP_REG_MERGE_CFG_25);
+ if (r_w)
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ else
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+
+ /*
+ * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
+ * Only take effect when the merge is setting to merge mode.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_27);
+
mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
@@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->mute_support = of_property_read_bool(dev->of_node,
+ "mediatek,merge-mute");
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add merge new API.
1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is
mtk_ddp_comp_funcs function prototype. The API interface parameters
cannot be modified, so add a new config API for extension.
3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
are configured with each drm plane update. Need to enable/disable
merge with cmdq making sure all the settings taken effect in the
same vblank.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
2 files changed, 82 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index b3a372cab0bd..2446ad0a4977 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index b05e1df79c3d..696bb948352b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -17,6 +17,7 @@
#define DISP_REG_MERGE_CTRL 0x000
#define MERGE_EN 1
#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_1 0x014
#define DISP_REG_MERGE_CFG_4 0x020
#define DISP_REG_MERGE_CFG_10 0x038
/* no swap */
@@ -25,9 +26,12 @@
#define DISP_REG_MERGE_CFG_12 0x040
#define CFG_10_10_1PI_2PO_BUF_MODE 6
#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define CFG_11_10_1PI_2PO_MERGE 18
#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
#define DISP_REG_MERGE_CFG_24 0x070
#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_26 0x078
+#define DISP_REG_MERGE_CFG_27 0x07c
#define DISP_REG_MERGE_CFG_36 0x0a0
#define ULTRA_EN BIT(0)
#define PREULTRA_EN BIT(4)
@@ -54,26 +58,52 @@
#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_MUTE_0 0xf00
+
struct mtk_disp_merge {
void __iomem *regs;
struct clk *clk;
struct clk *async_clk;
struct cmdq_client_reg cmdq_reg;
bool fifo_en;
+ bool mute_support;
};
void mtk_merge_start(struct device *dev)
+{
+ mtk_merge_enable(dev, NULL);
+}
+
+void mtk_merge_stop(struct device *dev)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_merge_disable(dev, NULL);
}
-void mtk_merge_stop(struct device *dev)
+void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
- writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+ mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->mute_support)
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_MUTE_0);
}
static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
@@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
void mtk_merge_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
+ unsigned int h, unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
- if (!h || !w) {
- dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ if (!h || !l_w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
return;
}
@@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
mode = CFG_10_10_2PI_2PO_BUF_MODE;
}
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ if (r_w)
+ mode = CFG_11_10_1PI_2PO_MERGE;
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_0);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_4);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ /*
+ * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
+ * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
+ * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
+ * the input0 goes to SRAM0, and input1 goes to SRAM1.
+ * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
+ * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_24);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
- DISP_REG_MERGE_CFG_25);
+ if (r_w)
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ else
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+
+ /*
+ * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
+ * Only take effect when the merge is setting to merge mode.
+ */
+ mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_26);
+ mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_27);
+
mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
@@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->mute_support = of_property_read_bool(dev->of_node,
+ "mediatek,merge-mute");
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
3 files changed, 429 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 6e604a933ed0..fb158a1e7f06 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
+ mtk_ethdr.o \
mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..99e5a95aebed
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2)
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->mmsys_dev = data;
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_ethdr_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..84eb9bf2ede0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_ETHDR_H__
+#define __MTK_ETHDR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+#endif
+
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
3 files changed, 429 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 6e604a933ed0..fb158a1e7f06 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
+ mtk_ethdr.o \
mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..99e5a95aebed
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2)
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->mmsys_dev = data;
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_ethdr_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..84eb9bf2ede0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_ETHDR_H__
+#define __MTK_ETHDR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+#endif
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
ETHDR is a part of ovl_adaptor.
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combine
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
3 files changed, 429 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 6e604a933ed0..fb158a1e7f06 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
+ mtk_ethdr.o \
mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..99e5a95aebed
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_INTEN 0x4
+ #define MIX_FME_CPL_INTEN BIT(1)
+#define MIX_INTSTA 0x8
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+ #define OUTPUT_NO_RND BIT(3)
+ #define SOURCE_RGB_SEL BIT(7)
+ #define BACKGROUND_RELAY (4 << 9)
+#define MIX_ROI_BGCLR 0x20
+ #define BGCLR_BLACK 0xff000000
+#define MIX_SRC_CON 0x24
+ #define MIX_SRC_L0_EN BIT(0)
+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
+ #define NON_PREMULTI_SOURCE (2 << 12)
+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
+#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+ #define MIX_FUNC_DCM_ENABLE 0xffffffff
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+ #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+ #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+ #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
+
+#define MIXER_INx_MODE_BYPASS 0
+#define MIXER_INx_MODE_EVEN_EXTEND 1
+#define MIXER_INx_MODE_ODD_EXTEND 2
+#define DEFAULT_9BIT_ALPHA 0x100
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+ struct device *mmsys_dev;
+ spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+void mtk_ethdr_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+void mtk_ethdr_disable_vblank(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
+}
+
+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_ethdr *priv = dev_id;
+ unsigned long flags;
+
+ writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if (!priv->vblank_cb) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return IRQ_NONE;
+ }
+
+ priv->vblank_cb(priv->vblank_cb_data);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
+ unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx >= 4)
+ return;
+
+ if (!pending->enable) {
+ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, 0, cmdq_pkt);
+ return;
+ }
+
+ if (pending->x % 2)
+ mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
+ idx + 1, mixer_pad_mode, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
+ idx + 1, pending->width / 2 - 1, cmdq_pkt);
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 0, cmdq_pkt);
+ } else {
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
+ idx + 1, 1, cmdq_pkt);
+ }
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
+ DEFAULT_9BIT_ALPHA, cmdq_pkt);
+
+ mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
+ mixer->regs, MIX_L_SRC_SIZE(idx));
+ mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
+ 0x1ff);
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
+ BIT(idx));
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
+ vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
+ vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
+ gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
+ gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
+
+ mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
+ vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
+
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
+ mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
+ mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(0));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(1));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(2));
+ mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
+ MIX_L_SRC_CON(3));
+ mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
+ mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
+ &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
+ mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, MIX_SRC_L0_EN);
+
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0,
+ w / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0,
+ h, cmdq_pkt);
+ mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, 0, cmdq_pkt);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(1, mixer->regs + MIX_EN);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ writel(0, mixer->regs + MIX_EN);
+ writel(1, mixer->regs + MIX_RST);
+ reset_control_reset(devm_reset_control_array_get(dev, true, true));
+ writel(0, mixer->regs + MIX_RST);
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ priv->mmsys_dev = data;
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
+ spin_lock_init(&priv->lock);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
+module_platform_driver(mtk_ethdr_driver);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..84eb9bf2ede0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_ETHDR_H__
+#define __MTK_ETHDR_H__
+
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ethdr_disable_vblank(struct device *dev);
+#endif
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
4 files changed, 516 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fb158a1e7f06..3abd27d7c91d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_gamma.o \
mtk_disp_merge.o \
mtk_disp_ovl.o \
+ mtk_disp_ovl_adaptor.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2446ad0a4977..6a4f4c42aedb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ovl_adaptor_disable_vblank(struct device *dev);
+void mtk_ovl_adaptor_start(struct device *dev);
+void mtk_ovl_adaptor_stop(struct device *dev);
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
+
int mtk_mdp_rdma_clk_enable(struct device *dev);
void mtk_mdp_rdma_clk_disable(struct device *dev);
void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..bfb5a9d29c26
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_ethdr.h"
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_ETHDR,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ETHDR0,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ETHDR",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+};
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ struct device *ethdr;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+ unsigned int l_w = 0;
+ unsigned int r_w = 0;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+ ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
+
+ if (!pending->enable) {
+ mtk_merge_disable(merge, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+ return;
+ }
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ if (use_dual_pipe) {
+ l_w = (pending->width / 2) + ((pending->width / 2) % 2);
+ r_w = pending->width - l_w;
+ } else {
+ l_w = pending->width;
+ }
+ mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.width = l_w;
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
+
+ if (use_dual_pipe) {
+ rdma_config.x_left = l_w;
+ rdma_config.width = r_w;
+ mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+ }
+
+ mtk_merge_enable(merge, cmdq_pkt);
+ mtk_merge_unmute(merge, cmdq_pkt);
+
+ mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
+ else
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
+ vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_start(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l, NULL);
+ mtk_mdp_rdma_stop(rdma_r, NULL);
+ mtk_merge_stop(merge);
+ }
+
+ mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int ret;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ ret = mtk_mdp_rdma_clk_enable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ ret = mtk_merge_clk_enable(comp);
+ else
+ ret = mtk_ethdr_clk_enable(comp);
+ if (ret) {
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ goto clk_err;
+ }
+ }
+
+ return ret;
+
+clk_err:
+ while (--i >= 0) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+}
+
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
+{
+ return MTK_OVL_ADAPTOR_LAYER_NUM;
+}
+
+void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
+ vblank_cb, vblank_cb_data);
+}
+
+void mtk_ovl_adaptor_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ }, {
+ .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
+ },
+ {},
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ struct platform_device *comp_pdev;
+ int i, ret;
+
+ parent = dev->parent->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
+
+ drm_of_component_match_add(dev, match, compare_of, node);
+ dev_info(dev, "Adding component match for %pOF\n", node);
+ }
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
+ .bind = mtk_disp_ovl_adaptor_comp_bind,
+ .unbind = mtk_disp_ovl_adaptor_comp_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s-%d", __func__, __LINE__);
+
+ component_bind_all(dev, priv->mmsys_dev);
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
+{
+}
+
+static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
+ .bind = mtk_disp_ovl_adaptor_master_bind,
+ .unbind = mtk_disp_ovl_adaptor_master_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
+{
+ struct device_node *node;
+
+ for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
+ const struct of_device_id *of_id;
+ struct platform_device *comp_pdev;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node))
+ continue;
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0)
+ continue;
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev)
+ return -EPROBE_DEFER;
+
+ if (!platform_get_drvdata(comp_pdev))
+ return -EPROBE_DEFER;
+ }
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct component_match *match = NULL;
+ int ret;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ ret = mtk_disp_ovl_adaptor_check_comp(dev);
+ if (ret < 0)
+ return ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev, &match);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+ component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..1ad9f7edfcc7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_merge_driver;
+extern struct platform_driver mtk_disp_ovl_adaptor_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
4 files changed, 516 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fb158a1e7f06..3abd27d7c91d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_gamma.o \
mtk_disp_merge.o \
mtk_disp_ovl.o \
+ mtk_disp_ovl_adaptor.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2446ad0a4977..6a4f4c42aedb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ovl_adaptor_disable_vblank(struct device *dev);
+void mtk_ovl_adaptor_start(struct device *dev);
+void mtk_ovl_adaptor_stop(struct device *dev);
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
+
int mtk_mdp_rdma_clk_enable(struct device *dev);
void mtk_mdp_rdma_clk_disable(struct device *dev);
void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..bfb5a9d29c26
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_ethdr.h"
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_ETHDR,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ETHDR0,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ETHDR",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+};
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ struct device *ethdr;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+ unsigned int l_w = 0;
+ unsigned int r_w = 0;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+ ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
+
+ if (!pending->enable) {
+ mtk_merge_disable(merge, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+ return;
+ }
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ if (use_dual_pipe) {
+ l_w = (pending->width / 2) + ((pending->width / 2) % 2);
+ r_w = pending->width - l_w;
+ } else {
+ l_w = pending->width;
+ }
+ mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.width = l_w;
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
+
+ if (use_dual_pipe) {
+ rdma_config.x_left = l_w;
+ rdma_config.width = r_w;
+ mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+ }
+
+ mtk_merge_enable(merge, cmdq_pkt);
+ mtk_merge_unmute(merge, cmdq_pkt);
+
+ mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
+ else
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
+ vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_start(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l, NULL);
+ mtk_mdp_rdma_stop(rdma_r, NULL);
+ mtk_merge_stop(merge);
+ }
+
+ mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int ret;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ ret = mtk_mdp_rdma_clk_enable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ ret = mtk_merge_clk_enable(comp);
+ else
+ ret = mtk_ethdr_clk_enable(comp);
+ if (ret) {
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ goto clk_err;
+ }
+ }
+
+ return ret;
+
+clk_err:
+ while (--i >= 0) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+}
+
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
+{
+ return MTK_OVL_ADAPTOR_LAYER_NUM;
+}
+
+void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
+ vblank_cb, vblank_cb_data);
+}
+
+void mtk_ovl_adaptor_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ }, {
+ .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
+ },
+ {},
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ struct platform_device *comp_pdev;
+ int i, ret;
+
+ parent = dev->parent->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
+
+ drm_of_component_match_add(dev, match, compare_of, node);
+ dev_info(dev, "Adding component match for %pOF\n", node);
+ }
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
+ .bind = mtk_disp_ovl_adaptor_comp_bind,
+ .unbind = mtk_disp_ovl_adaptor_comp_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s-%d", __func__, __LINE__);
+
+ component_bind_all(dev, priv->mmsys_dev);
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
+{
+}
+
+static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
+ .bind = mtk_disp_ovl_adaptor_master_bind,
+ .unbind = mtk_disp_ovl_adaptor_master_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
+{
+ struct device_node *node;
+
+ for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
+ const struct of_device_id *of_id;
+ struct platform_device *comp_pdev;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node))
+ continue;
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0)
+ continue;
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev)
+ return -EPROBE_DEFER;
+
+ if (!platform_get_drvdata(comp_pdev))
+ return -EPROBE_DEFER;
+ }
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct component_match *match = NULL;
+ int ret;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ ret = mtk_disp_ovl_adaptor_check_comp(dev);
+ if (ret < 0)
+ return ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev, &match);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+ component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..1ad9f7edfcc7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_merge_driver;
+extern struct platform_driver mtk_disp_ovl_adaptor_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ovl_adaptor driver for MT8195.
Ovl_adaptor is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
an ETHDR. Two RDMAs merge into one layer, so this module support 4
layers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
4 files changed, 516 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fb158a1e7f06..3abd27d7c91d 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_gamma.o \
mtk_disp_merge.o \
mtk_disp_ovl.o \
+ mtk_disp_ovl_adaptor.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 2446ad0a4977..6a4f4c42aedb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ovl_adaptor_clk_enable(struct device *dev);
+void mtk_ovl_adaptor_clk_disable(struct device *dev);
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ovl_adaptor_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_ovl_adaptor_disable_vblank(struct device *dev);
+void mtk_ovl_adaptor_start(struct device *dev);
+void mtk_ovl_adaptor_stop(struct device *dev);
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
+
int mtk_mdp_rdma_clk_enable(struct device *dev);
void mtk_mdp_rdma_clk_disable(struct device *dev);
void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
new file mode 100644
index 000000000000..bfb5a9d29c26
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_ethdr.h"
+
+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
+#define MTK_OVL_ADAPTOR_LAYER_NUM 4
+
+enum mtk_ovl_adaptor_comp_type {
+ OVL_ADAPTOR_TYPE_RDMA = 0,
+ OVL_ADAPTOR_TYPE_MERGE,
+ OVL_ADAPTOR_TYPE_ETHDR,
+ OVL_ADAPTOR_TYPE_NUM,
+};
+
+enum mtk_ovl_adaptor_comp_id {
+ OVL_ADAPTOR_MDP_RDMA0,
+ OVL_ADAPTOR_MDP_RDMA1,
+ OVL_ADAPTOR_MDP_RDMA2,
+ OVL_ADAPTOR_MDP_RDMA3,
+ OVL_ADAPTOR_MDP_RDMA4,
+ OVL_ADAPTOR_MDP_RDMA5,
+ OVL_ADAPTOR_MDP_RDMA6,
+ OVL_ADAPTOR_MDP_RDMA7,
+ OVL_ADAPTOR_MERGE0,
+ OVL_ADAPTOR_MERGE1,
+ OVL_ADAPTOR_MERGE2,
+ OVL_ADAPTOR_MERGE3,
+ OVL_ADAPTOR_ETHDR0,
+ OVL_ADAPTOR_ID_MAX
+};
+
+struct ovl_adaptor_comp_match {
+ enum mtk_ovl_adaptor_comp_type type;
+ int alias_id;
+};
+
+struct mtk_disp_ovl_adaptor {
+ struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
+ struct device *mmsys_dev;
+};
+
+static const char * const ovl_adaptor_comp_str[] = {
+ "OVL_ADAPTOR_MDP_RDMA0",
+ "OVL_ADAPTOR_MDP_RDMA1",
+ "OVL_ADAPTOR_MDP_RDMA2",
+ "OVL_ADAPTOR_MDP_RDMA3",
+ "OVL_ADAPTOR_MDP_RDMA4",
+ "OVL_ADAPTOR_MDP_RDMA5",
+ "OVL_ADAPTOR_MDP_RDMA6",
+ "OVL_ADAPTOR_MDP_RDMA7",
+ "OVL_ADAPTOR_MERGE0",
+ "OVL_ADAPTOR_MERGE1",
+ "OVL_ADAPTOR_MERGE2",
+ "OVL_ADAPTOR_MERGE3",
+ "OVL_ADAPTOR_ETHDR",
+ "OVL_ADAPTOR_ID_MAX"
+};
+
+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
+ [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
+ [OVL_ADAPTOR_TYPE_MERGE] = "merge",
+ [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
+};
+
+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
+};
+
+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ struct device *ethdr;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+ unsigned int l_w = 0;
+ unsigned int r_w = 0;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
+ ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
+
+ if (!pending->enable) {
+ mtk_merge_disable(merge, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+ return;
+ }
+
+ /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
+ pending->width = ALIGN_DOWN(pending->width, 2);
+
+ if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ if (use_dual_pipe) {
+ l_w = (pending->width / 2) + ((pending->width / 2) % 2);
+ r_w = pending->width - l_w;
+ } else {
+ l_w = pending->width;
+ }
+ mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
+ idx, pending->width / 2, cmdq_pkt);
+ mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
+ idx, pending->height, cmdq_pkt);
+
+ rdma_config.width = l_w;
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.pitch = pending->pitch;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
+
+ if (use_dual_pipe) {
+ rdma_config.x_left = l_w;
+ rdma_config.width = r_w;
+ mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
+ }
+
+ mtk_merge_enable(merge, cmdq_pkt);
+ mtk_merge_unmute(merge, cmdq_pkt);
+
+ mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
+ else
+ mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
+
+ mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
+ vrefresh, bpc, cmdq_pkt);
+}
+
+void mtk_ovl_adaptor_start(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *rdma_l;
+ struct device *rdma_r;
+ struct device *merge;
+ u32 i;
+
+ for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
+ rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
+ rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
+ merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
+
+ mtk_mdp_rdma_stop(rdma_l, NULL);
+ mtk_mdp_rdma_stop(rdma_r, NULL);
+ mtk_merge_stop(merge);
+ }
+
+ mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+int mtk_ovl_adaptor_clk_enable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int ret;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ ret = mtk_mdp_rdma_clk_enable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ ret = mtk_merge_clk_enable(comp);
+ else
+ ret = mtk_ethdr_clk_enable(comp);
+ if (ret) {
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, ovl_adaptor_comp_str[i]);
+ goto clk_err;
+ }
+ }
+
+ return ret;
+
+clk_err:
+ while (--i >= 0) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+ return ret;
+}
+
+void mtk_ovl_adaptor_clk_disable(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+ struct device *comp;
+ int i;
+
+ for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
+ comp = ovl_adaptor->ovl_adaptor_comp[i];
+
+ if (i < OVL_ADAPTOR_MERGE0)
+ mtk_mdp_rdma_clk_disable(comp);
+ else if (i < OVL_ADAPTOR_ETHDR0)
+ mtk_merge_clk_disable(comp);
+ else
+ mtk_ethdr_clk_disable(comp);
+ }
+}
+
+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
+{
+ return MTK_OVL_ADAPTOR_LAYER_NUM;
+}
+
+void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
+ vblank_cb, vblank_cb_data);
+}
+
+void mtk_ovl_adaptor_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_ovl_adaptor_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
+ }, {
+ .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
+ },
+ {},
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ struct platform_device *comp_pdev;
+ int i, ret;
+
+ parent = dev->parent->parent->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
+
+ drm_of_component_match_add(dev, match, compare_of, node);
+ dev_info(dev, "Adding component match for %pOF\n", node);
+ }
+
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
+ .bind = mtk_disp_ovl_adaptor_comp_bind,
+ .unbind = mtk_disp_ovl_adaptor_comp_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s-%d", __func__, __LINE__);
+
+ component_bind_all(dev, priv->mmsys_dev);
+ return 0;
+}
+
+static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
+{
+}
+
+static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
+ .bind = mtk_disp_ovl_adaptor_master_bind,
+ .unbind = mtk_disp_ovl_adaptor_master_unbind,
+};
+
+static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
+{
+ struct device_node *node;
+
+ for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
+ const struct of_device_id *of_id;
+ struct platform_device *comp_pdev;
+ enum mtk_ovl_adaptor_comp_type type;
+ int id;
+
+ of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node))
+ continue;
+
+ type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
+
+ id = ovl_adaptor_comp_get_id(dev, node, type);
+ if (id < 0)
+ continue;
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev)
+ return -EPROBE_DEFER;
+
+ if (!platform_get_drvdata(comp_pdev))
+ return -EPROBE_DEFER;
+ }
+ return 0;
+}
+
+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_ovl_adaptor *priv;
+ struct device *dev = &pdev->dev;
+ struct component_match *match = NULL;
+ int ret;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ ret = mtk_disp_ovl_adaptor_check_comp(dev);
+ if (ret < 0)
+ return ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->mmsys_dev = pdev->dev.platform_data;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = ovl_adaptor_comp_init(dev, &match);
+ if (ret) {
+ dev_notice(dev, "ovl_adaptor comp init fail\n");
+ return ret;
+ }
+ component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
+ if (ret != 0) {
+ pm_runtime_disable(dev);
+ dev_err(dev, "Failed to add component: %d\n", ret);
+ }
+
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
+ pm_runtime_disable(&pdev->dev);
+ return 0;
+}
+
+struct platform_driver mtk_disp_ovl_adaptor_driver = {
+ .probe = mtk_disp_ovl_adaptor_probe,
+ .remove = mtk_disp_ovl_adaptor_remove,
+ .driver = {
+ .name = "mediatek-disp-ovl-adaptor",
+ .owner = THIS_MODULE,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..1ad9f7edfcc7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_merge_driver;
+extern struct platform_driver mtk_disp_ovl_adaptor_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
only one drm driver register as the drm device.
Each drm driver binds its own component. The last bind drm driver
allocates and registers the drm device to drm core.
Each crtc path is created with the corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 301 ++++++++++++++++++------
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
4 files changed, 249 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 5f81489fc60c..ece407c6d44a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -829,21 +829,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -855,7 +862,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
@@ -908,19 +915,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
@@ -928,9 +934,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->cmdq_cl.tx_block = false;
mtk_crtc->cmdq_cl.knows_txdone = true;
mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
- mtk_crtc->cmdq_chan =
- mbox_request_channel(&mtk_crtc->cmdq_cl,
- drm_crtc_index(&mtk_crtc->base));
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+ mtk_crtc->cmdq_chan = mbox_request_channel(&mtk_crtc->cmdq_cl, i);
if (IS_ERR(mtk_crtc->cmdq_chan)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -940,7 +945,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_chan) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 274a5bb10851..eedf10ed30c8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -196,6 +196,8 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -204,6 +206,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -213,11 +217,15 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -225,6 +233,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -232,6 +242,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -239,32 +251,121 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
.ext_path = mt8192_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
};
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = &mt8167_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { }
+};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static bool mtk_drm_get_all_drm_priv(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ struct device *drm_dev;
+ int cnt = 0;
+ int i, j;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt] = dev_get_drvdata(drm_dev);
+ if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound)
+ cnt++;
+ }
+
+ if (drm_priv->data->mmsys_dev_num == cnt) {
+ for (i = 0; i < cnt; i++)
+ for (j = 0; j < cnt; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path)
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ return true;
+
+ if (drv_data->ext_path)
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ return true;
+
+ if (drv_data->third_path)
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ return true;
+
+ return false;
+}
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
- int ret;
-
- if (!iommu_present(&platform_bus_type))
- return -EPROBE_DEFER;
-
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ int ret, i, j;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -283,33 +384,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
- if (ret)
- goto put_mutex_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
+ if (ret)
+ goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -318,7 +443,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
@@ -340,9 +466,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -395,15 +524,36 @@ static int compare_of(struct device *dev, void *data)
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
+ struct platform_device *pdev;
struct drm_device *drm;
- int ret;
+ int ret, i;
+
+ if (!iommu_present(&platform_bus_type))
+ return -EPROBE_DEFER;
+
+ pdev = of_find_device_by_node(private->mutex_node);
+ if (!pdev) {
+ dev_err(dev, "Waiting for disp-mutex device %pOF\n",
+ private->mutex_node);
+ of_node_put(private->mutex_node);
+ return -EPROBE_DEFER;
+ }
+
+ private->mutex_dev = &pdev->dev;
+ private->mtk_drm_bound = true;
+ private->dev = dev;
+
+ if (!mtk_drm_get_all_drm_priv(dev))
+ return 0;
drm = drm_dev_alloc(&mtk_drm_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
- drm->dev_private = private;
- private->drm = drm;
+ private->drm_master = true;
+ drm->dev_private = private;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->drm = drm;
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -428,10 +578,14 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
+ private->drm_master = false;
private->drm = NULL;
}
@@ -546,54 +700,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- { .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -613,7 +753,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -624,6 +770,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -701,9 +850,10 @@ static int mtk_drm_sys_suspend(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_suspend(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_suspend(drm);
return ret;
}
@@ -712,9 +862,10 @@ static int mtk_drm_sys_resume(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_resume(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_resume(drm);
return ret;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 1ad9f7edfcc7..589d6fd7fcc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,16 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ bool drm_master;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +46,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_aal_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
only one drm driver register as the drm device.
Each drm driver binds its own component. The last bind drm driver
allocates and registers the drm device to drm core.
Each crtc path is created with the corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 301 ++++++++++++++++++------
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
4 files changed, 249 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 5f81489fc60c..ece407c6d44a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -829,21 +829,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -855,7 +862,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
@@ -908,19 +915,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
@@ -928,9 +934,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->cmdq_cl.tx_block = false;
mtk_crtc->cmdq_cl.knows_txdone = true;
mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
- mtk_crtc->cmdq_chan =
- mbox_request_channel(&mtk_crtc->cmdq_cl,
- drm_crtc_index(&mtk_crtc->base));
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+ mtk_crtc->cmdq_chan = mbox_request_channel(&mtk_crtc->cmdq_cl, i);
if (IS_ERR(mtk_crtc->cmdq_chan)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -940,7 +945,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_chan) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 274a5bb10851..eedf10ed30c8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -196,6 +196,8 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -204,6 +206,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -213,11 +217,15 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -225,6 +233,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -232,6 +242,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -239,32 +251,121 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
.ext_path = mt8192_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
};
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = &mt8167_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { }
+};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static bool mtk_drm_get_all_drm_priv(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ struct device *drm_dev;
+ int cnt = 0;
+ int i, j;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt] = dev_get_drvdata(drm_dev);
+ if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound)
+ cnt++;
+ }
+
+ if (drm_priv->data->mmsys_dev_num == cnt) {
+ for (i = 0; i < cnt; i++)
+ for (j = 0; j < cnt; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path)
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ return true;
+
+ if (drv_data->ext_path)
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ return true;
+
+ if (drv_data->third_path)
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ return true;
+
+ return false;
+}
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
- int ret;
-
- if (!iommu_present(&platform_bus_type))
- return -EPROBE_DEFER;
-
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ int ret, i, j;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -283,33 +384,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
- if (ret)
- goto put_mutex_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
+ if (ret)
+ goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -318,7 +443,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
@@ -340,9 +466,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -395,15 +524,36 @@ static int compare_of(struct device *dev, void *data)
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
+ struct platform_device *pdev;
struct drm_device *drm;
- int ret;
+ int ret, i;
+
+ if (!iommu_present(&platform_bus_type))
+ return -EPROBE_DEFER;
+
+ pdev = of_find_device_by_node(private->mutex_node);
+ if (!pdev) {
+ dev_err(dev, "Waiting for disp-mutex device %pOF\n",
+ private->mutex_node);
+ of_node_put(private->mutex_node);
+ return -EPROBE_DEFER;
+ }
+
+ private->mutex_dev = &pdev->dev;
+ private->mtk_drm_bound = true;
+ private->dev = dev;
+
+ if (!mtk_drm_get_all_drm_priv(dev))
+ return 0;
drm = drm_dev_alloc(&mtk_drm_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
- drm->dev_private = private;
- private->drm = drm;
+ private->drm_master = true;
+ drm->dev_private = private;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->drm = drm;
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -428,10 +578,14 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
+ private->drm_master = false;
private->drm = NULL;
}
@@ -546,54 +700,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- { .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -613,7 +753,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -624,6 +770,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -701,9 +850,10 @@ static int mtk_drm_sys_suspend(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_suspend(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_suspend(drm);
return ret;
}
@@ -712,9 +862,10 @@ static int mtk_drm_sys_resume(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_resume(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_resume(drm);
return ret;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 1ad9f7edfcc7..589d6fd7fcc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,16 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ bool drm_master;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +46,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_aal_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 have two mmsys. Modify drm for MT8195 multi-mmsys support.
The two mmsys (vdosys0 and vdosys1) will bring up two drm drivers,
only one drm driver register as the drm device.
Each drm driver binds its own component. The last bind drm driver
allocates and registers the drm device to drm core.
Each crtc path is created with the corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 301 ++++++++++++++++++------
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
4 files changed, 249 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 5f81489fc60c..ece407c6d44a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -829,21 +829,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -855,7 +862,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
@@ -908,19 +915,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
@@ -928,9 +934,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mtk_crtc->cmdq_cl.tx_block = false;
mtk_crtc->cmdq_cl.knows_txdone = true;
mtk_crtc->cmdq_cl.rx_callback = ddp_cmdq_cb;
- mtk_crtc->cmdq_chan =
- mbox_request_channel(&mtk_crtc->cmdq_cl,
- drm_crtc_index(&mtk_crtc->base));
+ i = (priv->data->mmsys_dev_num > 1) ? 0 : drm_crtc_index(&mtk_crtc->base);
+ mtk_crtc->cmdq_chan = mbox_request_channel(&mtk_crtc->cmdq_cl, i);
if (IS_ERR(mtk_crtc->cmdq_chan)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
drm_crtc_index(&mtk_crtc->base));
@@ -940,7 +945,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (mtk_crtc->cmdq_chan) {
ret = of_property_read_u32_index(priv->mutex_node,
"mediatek,gce-events",
- drm_crtc_index(&mtk_crtc->base),
+ i,
&mtk_crtc->cmdq_event);
if (ret) {
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..a57eb12d7c05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -17,7 +17,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 274a5bb10851..eedf10ed30c8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -196,6 +196,8 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -204,6 +206,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -213,11 +217,15 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -225,6 +233,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -232,6 +242,8 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -239,32 +251,121 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
.ext_path = mt8192_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
};
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = &mt8167_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { }
+};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_match(struct device *dev, void *data)
+{
+ if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
+ return true;
+ return false;
+}
+
+static bool mtk_drm_get_all_drm_priv(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ struct device *drm_dev;
+ int cnt = 0;
+ int i, j;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
+ if (!drm_dev || !dev_get_drvdata(drm_dev))
+ continue;
+
+ all_drm_priv[cnt] = dev_get_drvdata(drm_dev);
+ if (all_drm_priv[cnt] && all_drm_priv[cnt]->mtk_drm_bound)
+ cnt++;
+ }
+
+ if (drm_priv->data->mmsys_dev_num == cnt) {
+ for (i = 0; i < cnt; i++)
+ for (j = 0; j < cnt; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return true;
+ }
+
+ return false;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path)
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ return true;
+
+ if (drv_data->ext_path)
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ return true;
+
+ if (drv_data->third_path)
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ return true;
+
+ return false;
+}
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
- int ret;
-
- if (!iommu_present(&platform_bus_type))
- return -EPROBE_DEFER;
-
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ int ret, i, j;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -283,33 +384,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
- if (ret)
- goto put_mutex_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
+ if (ret)
+ goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -318,7 +443,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
@@ -340,9 +466,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -395,15 +524,36 @@ static int compare_of(struct device *dev, void *data)
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
+ struct platform_device *pdev;
struct drm_device *drm;
- int ret;
+ int ret, i;
+
+ if (!iommu_present(&platform_bus_type))
+ return -EPROBE_DEFER;
+
+ pdev = of_find_device_by_node(private->mutex_node);
+ if (!pdev) {
+ dev_err(dev, "Waiting for disp-mutex device %pOF\n",
+ private->mutex_node);
+ of_node_put(private->mutex_node);
+ return -EPROBE_DEFER;
+ }
+
+ private->mutex_dev = &pdev->dev;
+ private->mtk_drm_bound = true;
+ private->dev = dev;
+
+ if (!mtk_drm_get_all_drm_priv(dev))
+ return 0;
drm = drm_dev_alloc(&mtk_drm_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
- drm->dev_private = private;
- private->drm = drm;
+ private->drm_master = true;
+ drm->dev_private = private;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->drm = drm;
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -428,10 +578,14 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
+ private->drm_master = false;
private->drm = NULL;
}
@@ -546,54 +700,40 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- { .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
-
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -613,7 +753,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -624,6 +770,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
@@ -701,9 +850,10 @@ static int mtk_drm_sys_suspend(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_suspend(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_suspend(drm);
return ret;
}
@@ -712,9 +862,10 @@ static int mtk_drm_sys_resume(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
struct drm_device *drm = private->drm;
- int ret;
+ int ret = 0;
- ret = drm_mode_config_helper_resume(drm);
+ if (private->drm_master)
+ ret = drm_mode_config_helper_resume(drm);
return ret;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 1ad9f7edfcc7..589d6fd7fcc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,16 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ bool drm_master;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +46,7 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
};
extern struct platform_driver mtk_disp_aal_driver;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-04 6:21 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 13 ++---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 56 ++++++++++++++++-----
5 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 696bb948352b..d62c5e0632a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -8,6 +8,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_ddp_comp.h"
@@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_merge_disable(dev, NULL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ece407c6d44a..ecec1440eb07 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -859,15 +859,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
node = priv->comp_node[comp_id];
comp = &priv->ddp_comp[comp_id];
- if (!node) {
- dev_info(dev,
- "Not creating crtc %d because component %d is disabled or missing\n",
- crtc_i, comp_id);
- return 0;
- }
-
- if (!comp->dev) {
- dev_err(dev, "Component %pOF not initialized\n", node);
+ if (!node && !comp->dev) {
+ dev_err(dev,
+ "Not creating crtc %d because component %d is disabled, missing or not initialized\n",
+ crtc_i, comp_id);
return -ENODEV;
}
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index eb9835102d79..279087ae889b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -385,6 +385,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ovl_adaptor_clk_enable,
+ .clk_disable = mtk_ovl_adaptor_clk_disable,
+ .config = mtk_ovl_adaptor_config,
+ .start = mtk_ovl_adaptor_start,
+ .stop = mtk_ovl_adaptor_stop,
+ .layer_nr = mtk_ovl_adaptor_layer_nr,
+ .layer_config = mtk_ovl_adaptor_layer_config,
+ .enable_vblank = mtk_ovl_adaptor_enable_vblank,
+ .disable_vblank = mtk_ovl_adaptor_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -398,6 +410,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_POSTMASK] = "postmask",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
@@ -443,6 +456,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
@@ -548,12 +562,17 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
comp->id = comp_id;
comp->funcs = mtk_ddp_matches[comp_id].funcs;
- comp_pdev = of_find_device_by_node(node);
- if (!comp_pdev) {
- DRM_INFO("Waiting for device %s\n", node->full_name);
- return -EPROBE_DEFER;
+ /* Not all drm components have a DTS device node, such as ovl_adaptor,
+ * which is the drm bring up sub driver
+ */
+ if (node) {
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ DRM_INFO("Waiting for device %s\n", node->full_name);
+ return -EPROBE_DEFER;
+ }
+ comp->dev = &comp_pdev->dev;
}
- comp->dev = &comp_pdev->dev;
/* Only DMA capable components need the LARB property */
if (type == MTK_DISP_OVL ||
@@ -573,6 +592,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 221e2e3a3c8d..5e1404dc20c4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index eedf10ed30c8..778aec81a0de 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -190,6 +190,12 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -262,6 +268,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.mmsys_dev_num = 2,
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
@@ -279,6 +292,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
@@ -362,9 +377,7 @@ static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
struct mtk_drm_private *priv_n;
- struct platform_device *pdev;
- struct device_node *np = NULL;
- struct device *dma_dev;
+ struct device *dma_dev = NULL;
int ret, i, j;
ret = drmm_mode_config_init(drm);
@@ -406,8 +419,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->main_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->main_path[0]].dev;
continue;
} else if (i == 1 && priv_n->data->ext_len) {
@@ -416,8 +429,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->ext_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->ext_path[0]].dev;
continue;
} else if (i == 2 && priv_n->data->third_len) {
@@ -426,8 +439,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->third_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->third_path[0]].dev;
continue;
}
@@ -435,14 +448,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
/* Use OVL device for all DMA memory allocations */
- pdev = of_find_device_by_node(np);
- if (!pdev) {
+ if (!dma_dev) {
ret = -ENODEV;
dev_err(drm->dev, "Need at least one OVL device\n");
goto err_component_unbind;
}
- dma_dev = &pdev->dev;
for (i = 0; i < private->data->mmsys_dev_num; i++)
private->all_drm_private[i]->dma_dev = dma_dev;
@@ -521,6 +532,11 @@ static int compare_of(struct device *dev, void *data)
return dev->of_node == data;
}
+static int compare_dev(struct device *dev, void *data)
+{
+ return dev == (struct device *)data;
+}
+
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
@@ -709,6 +725,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct platform_device *ovl_adaptor;
int ret;
int i;
@@ -734,6 +751,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
return -ENODEV;
}
+ /* Bringup ovl_adaptor */
+ if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_OVL_ADAPTOR)) {
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO,
+ (void *)private->mmsys_dev,
+ sizeof(*private->mmsys_dev));
+ private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
+ private->comp_node[DDP_COMPONENT_OVL_ADAPTOR] = ovl_adaptor->dev.of_node;
+ mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR],
+ DDP_COMPONENT_OVL_ADAPTOR);
+ component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
+ }
+
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -787,6 +817,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -889,6 +920,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_merge_driver,
+ &mtk_disp_ovl_adaptor_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
--
2.18.0
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 13 ++---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 56 ++++++++++++++++-----
5 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 696bb948352b..d62c5e0632a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -8,6 +8,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_ddp_comp.h"
@@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_merge_disable(dev, NULL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ece407c6d44a..ecec1440eb07 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -859,15 +859,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
node = priv->comp_node[comp_id];
comp = &priv->ddp_comp[comp_id];
- if (!node) {
- dev_info(dev,
- "Not creating crtc %d because component %d is disabled or missing\n",
- crtc_i, comp_id);
- return 0;
- }
-
- if (!comp->dev) {
- dev_err(dev, "Component %pOF not initialized\n", node);
+ if (!node && !comp->dev) {
+ dev_err(dev,
+ "Not creating crtc %d because component %d is disabled, missing or not initialized\n",
+ crtc_i, comp_id);
return -ENODEV;
}
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index eb9835102d79..279087ae889b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -385,6 +385,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ovl_adaptor_clk_enable,
+ .clk_disable = mtk_ovl_adaptor_clk_disable,
+ .config = mtk_ovl_adaptor_config,
+ .start = mtk_ovl_adaptor_start,
+ .stop = mtk_ovl_adaptor_stop,
+ .layer_nr = mtk_ovl_adaptor_layer_nr,
+ .layer_config = mtk_ovl_adaptor_layer_config,
+ .enable_vblank = mtk_ovl_adaptor_enable_vblank,
+ .disable_vblank = mtk_ovl_adaptor_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -398,6 +410,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_POSTMASK] = "postmask",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
@@ -443,6 +456,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
@@ -548,12 +562,17 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
comp->id = comp_id;
comp->funcs = mtk_ddp_matches[comp_id].funcs;
- comp_pdev = of_find_device_by_node(node);
- if (!comp_pdev) {
- DRM_INFO("Waiting for device %s\n", node->full_name);
- return -EPROBE_DEFER;
+ /* Not all drm components have a DTS device node, such as ovl_adaptor,
+ * which is the drm bring up sub driver
+ */
+ if (node) {
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ DRM_INFO("Waiting for device %s\n", node->full_name);
+ return -EPROBE_DEFER;
+ }
+ comp->dev = &comp_pdev->dev;
}
- comp->dev = &comp_pdev->dev;
/* Only DMA capable components need the LARB property */
if (type == MTK_DISP_OVL ||
@@ -573,6 +592,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 221e2e3a3c8d..5e1404dc20c4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index eedf10ed30c8..778aec81a0de 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -190,6 +190,12 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -262,6 +268,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.mmsys_dev_num = 2,
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
@@ -279,6 +292,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
@@ -362,9 +377,7 @@ static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
struct mtk_drm_private *priv_n;
- struct platform_device *pdev;
- struct device_node *np = NULL;
- struct device *dma_dev;
+ struct device *dma_dev = NULL;
int ret, i, j;
ret = drmm_mode_config_init(drm);
@@ -406,8 +419,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->main_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->main_path[0]].dev;
continue;
} else if (i == 1 && priv_n->data->ext_len) {
@@ -416,8 +429,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->ext_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->ext_path[0]].dev;
continue;
} else if (i == 2 && priv_n->data->third_len) {
@@ -426,8 +439,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->third_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->third_path[0]].dev;
continue;
}
@@ -435,14 +448,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
/* Use OVL device for all DMA memory allocations */
- pdev = of_find_device_by_node(np);
- if (!pdev) {
+ if (!dma_dev) {
ret = -ENODEV;
dev_err(drm->dev, "Need at least one OVL device\n");
goto err_component_unbind;
}
- dma_dev = &pdev->dev;
for (i = 0; i < private->data->mmsys_dev_num; i++)
private->all_drm_private[i]->dma_dev = dma_dev;
@@ -521,6 +532,11 @@ static int compare_of(struct device *dev, void *data)
return dev->of_node == data;
}
+static int compare_dev(struct device *dev, void *data)
+{
+ return dev == (struct device *)data;
+}
+
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
@@ -709,6 +725,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct platform_device *ovl_adaptor;
int ret;
int i;
@@ -734,6 +751,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
return -ENODEV;
}
+ /* Bringup ovl_adaptor */
+ if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_OVL_ADAPTOR)) {
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO,
+ (void *)private->mmsys_dev,
+ sizeof(*private->mmsys_dev));
+ private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
+ private->comp_node[DDP_COMPONENT_OVL_ADAPTOR] = ovl_adaptor->dev.of_node;
+ mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR],
+ DDP_COMPONENT_OVL_ADAPTOR);
+ component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
+ }
+
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -787,6 +817,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -889,6 +920,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_merge_driver,
+ &mtk_disp_ovl_adaptor_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 111+ messages in thread
* [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-10-04 6:21 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-04 6:21 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and the sub driver.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 13 ++---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 56 ++++++++++++++++-----
5 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 696bb948352b..d62c5e0632a2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -8,6 +8,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_ddp_comp.h"
@@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev)
struct mtk_disp_merge *priv = dev_get_drvdata(dev);
mtk_merge_disable(dev, NULL);
+
+ if (priv->async_clk)
+ device_reset_optional(dev);
}
void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index ece407c6d44a..ecec1440eb07 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -859,15 +859,10 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
node = priv->comp_node[comp_id];
comp = &priv->ddp_comp[comp_id];
- if (!node) {
- dev_info(dev,
- "Not creating crtc %d because component %d is disabled or missing\n",
- crtc_i, comp_id);
- return 0;
- }
-
- if (!comp->dev) {
- dev_err(dev, "Component %pOF not initialized\n", node);
+ if (!node && !comp->dev) {
+ dev_err(dev,
+ "Not creating crtc %d because component %d is disabled, missing or not initialized\n",
+ crtc_i, comp_id);
return -ENODEV;
}
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index eb9835102d79..279087ae889b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -385,6 +385,18 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
+ .clk_enable = mtk_ovl_adaptor_clk_enable,
+ .clk_disable = mtk_ovl_adaptor_clk_disable,
+ .config = mtk_ovl_adaptor_config,
+ .start = mtk_ovl_adaptor_start,
+ .stop = mtk_ovl_adaptor_stop,
+ .layer_nr = mtk_ovl_adaptor_layer_nr,
+ .layer_config = mtk_ovl_adaptor_layer_config,
+ .enable_vblank = mtk_ovl_adaptor_enable_vblank,
+ .disable_vblank = mtk_ovl_adaptor_disable_vblank,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_AAL] = "aal",
[MTK_DISP_BLS] = "bls",
@@ -398,6 +410,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
+ [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
[MTK_DISP_POSTMASK] = "postmask",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
@@ -443,6 +456,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
+ [DDP_COMPONENT_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
@@ -548,12 +562,17 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
comp->id = comp_id;
comp->funcs = mtk_ddp_matches[comp_id].funcs;
- comp_pdev = of_find_device_by_node(node);
- if (!comp_pdev) {
- DRM_INFO("Waiting for device %s\n", node->full_name);
- return -EPROBE_DEFER;
+ /* Not all drm components have a DTS device node, such as ovl_adaptor,
+ * which is the drm bring up sub driver
+ */
+ if (node) {
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ DRM_INFO("Waiting for device %s\n", node->full_name);
+ return -EPROBE_DEFER;
+ }
+ comp->dev = &comp_pdev->dev;
}
- comp->dev = &comp_pdev->dev;
/* Only DMA capable components need the LARB property */
if (type == MTK_DISP_OVL ||
@@ -573,6 +592,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_OVL_ADAPTOR ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 221e2e3a3c8d..5e1404dc20c4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_OVL,
MTK_DISP_OVL_2L,
+ MTK_DISP_OVL_ADAPTOR,
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index eedf10ed30c8..778aec81a0de 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -190,6 +190,12 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_ADAPTOR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -262,6 +268,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.mmsys_dev_num = 2,
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
@@ -279,6 +292,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8192_mmsys_driver_data},
{ .compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
@@ -362,9 +377,7 @@ static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
struct mtk_drm_private *priv_n;
- struct platform_device *pdev;
- struct device_node *np = NULL;
- struct device *dma_dev;
+ struct device *dma_dev = NULL;
int ret, i, j;
ret = drmm_mode_config_init(drm);
@@ -406,8 +419,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->main_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->main_path[0]].dev;
continue;
} else if (i == 1 && priv_n->data->ext_len) {
@@ -416,8 +429,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->ext_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->ext_path[0]].dev;
continue;
} else if (i == 2 && priv_n->data->third_len) {
@@ -426,8 +439,8 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret)
goto err_component_unbind;
- if (!np)
- np = priv_n->comp_node[priv_n->data->third_path[0]];
+ if (!dma_dev)
+ dma_dev = priv_n->ddp_comp[priv_n->data->third_path[0]].dev;
continue;
}
@@ -435,14 +448,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
/* Use OVL device for all DMA memory allocations */
- pdev = of_find_device_by_node(np);
- if (!pdev) {
+ if (!dma_dev) {
ret = -ENODEV;
dev_err(drm->dev, "Need at least one OVL device\n");
goto err_component_unbind;
}
- dma_dev = &pdev->dev;
for (i = 0; i < private->data->mmsys_dev_num; i++)
private->all_drm_private[i]->dma_dev = dma_dev;
@@ -521,6 +532,11 @@ static int compare_of(struct device *dev, void *data)
return dev->of_node == data;
}
+static int compare_dev(struct device *dev, void *data)
+{
+ return dev == (struct device *)data;
+}
+
static int mtk_drm_bind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
@@ -709,6 +725,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct platform_device *ovl_adaptor;
int ret;
int i;
@@ -734,6 +751,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
return -ENODEV;
}
+ /* Bringup ovl_adaptor */
+ if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_OVL_ADAPTOR)) {
+ ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
+ PLATFORM_DEVID_AUTO,
+ (void *)private->mmsys_dev,
+ sizeof(*private->mmsys_dev));
+ private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
+ private->comp_node[DDP_COMPONENT_OVL_ADAPTOR] = ovl_adaptor->dev.of_node;
+ mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_OVL_ADAPTOR],
+ DDP_COMPONENT_OVL_ADAPTOR);
+ component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
+ }
+
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
const struct of_device_id *of_id;
@@ -787,6 +817,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -889,6 +920,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_merge_driver,
+ &mtk_disp_ovl_adaptor_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 111+ messages in thread
* Re: [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-14 14:52 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:52 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 148 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 0c97a5f016c1..f19ec72c1243 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -59,6 +59,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
There is no bitshifting action here: this is simply 1.
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
Same here.
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
And this is 0.
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
This is simply 0x2...
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
...and this is 0x3.
There are other occurrences of the same logic, so please fix them all.
Regards,
- Angelo
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-10-14 14:52 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:52 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 148 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 0c97a5f016c1..f19ec72c1243 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -59,6 +59,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
There is no bitshifting action here: this is simply 1.
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
Same here.
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
And this is 0.
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
This is simply 0x2...
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
...and this is 0x3.
There are other occurrences of the same logic, so please fix them all.
Regards,
- Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-10-14 14:52 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:52 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mt8195 vdosys1 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 136 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 10 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 2 +
> 3 files changed, 148 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 0c97a5f016c1..f19ec72c1243 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -59,6 +59,70 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
There is no bitshifting action here: this is simply 1.
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
Same here.
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
And this is 0.
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
> +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
This is simply 0x2...
> +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
...and this is 0x3.
There are other occurrences of the same logic, so please fix them all.
Regards,
- Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-14 14:56 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:56 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Il 04/10/21 08:21, Nancy.Lin ha scritto:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> 3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 648baaec112b..f67801c42fd9 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -123,6 +123,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
All other definitions are indented with tabulations, but these are spaces here.
Please, do not mix formatting.
Regards,
- Angelo
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-14 14:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:56 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Il 04/10/21 08:21, Nancy.Lin ha scritto:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> 3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 648baaec112b..f67801c42fd9 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -123,6 +123,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
All other definitions are indented with tabulations, but these are spaces here.
Please, do not mix formatting.
Regards,
- Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-14 14:56 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 14:56 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Il 04/10/21 08:21, Nancy.Lin ha scritto:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> 3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 648baaec112b..f67801c42fd9 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -123,6 +123,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
All other definitions are indented with tabulations, but these are spaces here.
Please, do not mix formatting.
Regards,
- Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-14 15:01 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 15:01 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mtk-mutex support for mt8195 vdosys1.
> The vdosys1 path component contains ovl_adaptor, merge5,
> and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> so change it to support multi-bit control.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
> 1 file changed, 175 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 36502b27fe20..7767fedbd14f 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -29,113 +29,142 @@
>
> #define INT_MUTEX BIT(1)
>
> -#define MT8167_MUTEX_MOD_DISP_PWM 1
This patch doesn't only add support for MT8195 vdosys1, but also changes
all definitions to a different "format", and also changes the type for
"mutex_mod" from int to long.
In reality, the actual functional change is minimal, compared to the size of
this entire patch.
Please, split this patch in two parts: one patch changing the defines and
the mutex_mod type (specifying that it's a preparation for adding support for
mt8195 vdosys1 mutex) and one patch adding such support.
Thanks!
Regards,
- Angelo
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-14 15:01 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 15:01 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mtk-mutex support for mt8195 vdosys1.
> The vdosys1 path component contains ovl_adaptor, merge5,
> and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> so change it to support multi-bit control.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
> 1 file changed, 175 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 36502b27fe20..7767fedbd14f 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -29,113 +29,142 @@
>
> #define INT_MUTEX BIT(1)
>
> -#define MT8167_MUTEX_MOD_DISP_PWM 1
This patch doesn't only add support for MT8195 vdosys1, but also changes
all definitions to a different "format", and also changes the type for
"mutex_mod" from int to long.
In reality, the actual functional change is minimal, compared to the size of
this entire patch.
Please, split this patch in two parts: one patch changing the defines and
the mutex_mod type (specifying that it's a preparation for adding support for
mt8195 vdosys1 mutex) and one patch adding such support.
Thanks!
Regards,
- Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-14 15:01 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-14 15:01 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add mtk-mutex support for mt8195 vdosys1.
> The vdosys1 path component contains ovl_adaptor, merge5,
> and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> so change it to support multi-bit control.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++-------------
> 1 file changed, 175 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 36502b27fe20..7767fedbd14f 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -29,113 +29,142 @@
>
> #define INT_MUTEX BIT(1)
>
> -#define MT8167_MUTEX_MOD_DISP_PWM 1
This patch doesn't only add support for MT8195 vdosys1, but also changes
all definitions to a different "format", and also changes the type for
"mutex_mod" from int to long.
In reality, the actual functional change is minimal, compared to the size of
this entire patch.
Please, split this patch in two parts: one patch changing the defines and
the mutex_mod type (specifying that it's a preparation for adding support for
mt8195 vdosys1 mutex) and one patch adding such support.
Thanks!
Regards,
- Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-15 7:49 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 7:49 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
nit: can you please fix the indentation here?
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
This looks like being a debugging print, use dev_dbg please.
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
...and this is another debugging print, imo.
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
Printing the line number here isn't giving any valuable information, as this
function is almost a one-liner... plus, this is a debug print and, as such,
you should either use dev_dbg instead or simply remove it: if anything needs
debugging of this part, you'll probably want to use ftrace anyway, so I don't
really see the need of having this print in place.
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
If you want to know when you're hitting a function, you should use ftrace
instead of a print. Please remove this message.
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
Also remove this one.
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
Please fix indentation:
.driver = {
.......
},
Regards,
- Angelo
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-15 7:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 7:49 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
nit: can you please fix the indentation here?
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
This looks like being a debugging print, use dev_dbg please.
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
...and this is another debugging print, imo.
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
Printing the line number here isn't giving any valuable information, as this
function is almost a one-liner... plus, this is a debug print and, as such,
you should either use dev_dbg instead or simply remove it: if anything needs
debugging of this part, you'll probably want to use ftrace anyway, so I don't
really see the need of having this print in place.
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
If you want to know when you're hitting a function, you should use ftrace
instead of a print. Please remove this message.
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
Also remove this one.
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
Please fix indentation:
.driver = {
.......
},
Regards,
- Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-15 7:49 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 7:49 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
nit: can you please fix the indentation here?
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
This looks like being a debugging print, use dev_dbg please.
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
...and this is another debugging print, imo.
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
Printing the line number here isn't giving any valuable information, as this
function is almost a one-liner... plus, this is a debug print and, as such,
you should either use dev_dbg instead or simply remove it: if anything needs
debugging of this part, you'll probably want to use ftrace anyway, so I don't
really see the need of having this print in place.
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
If you want to know when you're hitting a function, you should use ftrace
instead of a print. Please remove this message.
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
Also remove this one.
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
Please fix indentation:
.driver = {
.......
},
Regards,
- Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-15 8:08 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 8:08 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-15 8:08 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 8:08 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-15 8:08 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 111+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-15 8:08 UTC (permalink / raw)
To: Nancy.Lin, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-By: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-15 16:21 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 16:21 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 6007e00679a8..d7d0eda813d1 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -54,6 +54,10 @@ properties:
> command to SMI to speed up the data rate.
> type: boolean
>
> + mediatek,merge-mute:
> + description: Support mute function. Mute the content of merge output.
> + type: boolean
> +
> mediatek,gce-client-reg:
> description:
> The register of client driver can be configured by gce with 4 arguments
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-15 16:21 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 16:21 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 6007e00679a8..d7d0eda813d1 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -54,6 +54,10 @@ properties:
> command to SMI to speed up the data rate.
> type: boolean
>
> + mediatek,merge-mute:
> + description: Support mute function. Mute the content of merge output.
> + type: boolean
> +
> mediatek,gce-client-reg:
> description:
> The register of client driver can be configured by gce with 4 arguments
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property for mt8195
@ 2021-10-15 16:21 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 16:21 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> MT8195 vdosys1 merge1 to merge4 have HW mute function.
> Add MERGE additional mute property description.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 6007e00679a8..d7d0eda813d1 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -54,6 +54,10 @@ properties:
> command to SMI to speed up the data rate.
> type: boolean
>
> + mediatek,merge-mute:
> + description: Support mute function. Mute the content of merge output.
> + type: boolean
> +
> mediatek,gce-client-reg:
> description:
> The register of client driver can be configured by gce with 4 arguments
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-15 23:37 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
> 1 file changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> new file mode 100644
> index 000000000000..e127f0b392d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -0,0 +1,145 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + ETHDR is designed for HDR video and graphics conversion in the external display path.
> + It handles multiple HDR input types and performs tone mapping, color space/color
> + format conversion, and then combine different layers, output the required HDR or
> + SDR signal to the subsequent display path. This engine is composed of two video
> + frontends, two graphic frontends, one video backend and a mixer.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-disp-ethdr
> + reg:
> + maxItems: 7
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + interrupts:
> + minItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
In description, you does not mention that ethdr has dma function. I
expect that video front end and graphics front end direct link to
another hardware function block and no dma function. If it has both
direct link and dma function, add explain in description.
> + minItems: 1
> + maxItems: 2
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> + power-domains:
> + maxItems: 1
> + resets:
> + maxItems: 5
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + disp_ethdr@1c114000 {
> + compatible = "mediatek,mt8195-disp-ethdr";
> + reg = <0 0x1c114000 0 0x1000>,
> + <0 0x1c115000 0 0x1000>,
> + <0 0x1c117000 0 0x1000>,
> + <0 0x1c119000 0 0x1000>,
> + <0 0x1c11A000 0 0x1000>,
> + <0 0x1c11B000 0 0x1000>,
> + <0 0x1c11C000 0 0x1000>;
> + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds";
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
> + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> + <&vdosys1 CLK_VDO1_26M_SLOW>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> + <&topckgen CLK_TOP_ETHDR_SEL>;
> + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
> + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
> + "ethdr_top";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
> + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> + };
> +
> +...
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-15 23:37 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
> 1 file changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> new file mode 100644
> index 000000000000..e127f0b392d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -0,0 +1,145 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + ETHDR is designed for HDR video and graphics conversion in the external display path.
> + It handles multiple HDR input types and performs tone mapping, color space/color
> + format conversion, and then combine different layers, output the required HDR or
> + SDR signal to the subsequent display path. This engine is composed of two video
> + frontends, two graphic frontends, one video backend and a mixer.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-disp-ethdr
> + reg:
> + maxItems: 7
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + interrupts:
> + minItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
In description, you does not mention that ethdr has dma function. I
expect that video front end and graphics front end direct link to
another hardware function block and no dma function. If it has both
direct link and dma function, add explain in description.
> + minItems: 1
> + maxItems: 2
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> + power-domains:
> + maxItems: 1
> + resets:
> + maxItems: 5
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + disp_ethdr@1c114000 {
> + compatible = "mediatek,mt8195-disp-ethdr";
> + reg = <0 0x1c114000 0 0x1000>,
> + <0 0x1c115000 0 0x1000>,
> + <0 0x1c117000 0 0x1000>,
> + <0 0x1c119000 0 0x1000>,
> + <0 0x1c11A000 0 0x1000>,
> + <0 0x1c11B000 0 0x1000>,
> + <0 0x1c11C000 0 0x1000>;
> + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds";
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
> + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> + <&vdosys1 CLK_VDO1_26M_SLOW>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> + <&topckgen CLK_TOP_ETHDR_SEL>;
> + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
> + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
> + "ethdr_top";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
> + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> + };
> +
> +...
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-15 23:37 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:37 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 ETHDR definition.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++
> 1 file changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> new file mode 100644
> index 000000000000..e127f0b392d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
> @@ -0,0 +1,145 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Ethdr Device Tree Bindings
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + ETHDR is designed for HDR video and graphics conversion in the external display path.
> + It handles multiple HDR input types and performs tone mapping, color space/color
> + format conversion, and then combine different layers, output the required HDR or
> + SDR signal to the subsequent display path. This engine is composed of two video
> + frontends, two graphic frontends, one video backend and a mixer.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt8195-disp-ethdr
> + reg:
> + maxItems: 7
> + reg-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + interrupts:
> + minItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
In description, you does not mention that ethdr has dma function. I
expect that video front end and graphics front end direct link to
another hardware function block and no dma function. If it has both
direct link and dma function, add explain in description.
> + minItems: 1
> + maxItems: 2
> + clocks:
> + items:
> + - description: mixer clock
> + - description: video frontend 0 clock
> + - description: video frontend 1 clock
> + - description: graphic frontend 0 clock
> + - description: graphic frontend 1 clock
> + - description: video backend clock
> + - description: autodownload and menuload clock
> + - description: video frontend 0 async clock
> + - description: video frontend 1 async clock
> + - description: graphic frontend 0 async clock
> + - description: graphic frontend 1 async clock
> + - description: video backend async clock
> + - description: ethdr top clock
> + clock-names:
> + items:
> + - const: mixer
> + - const: vdo_fe0
> + - const: vdo_fe1
> + - const: gfx_fe0
> + - const: gfx_fe1
> + - const: vdo_be
> + - const: adl_ds
> + - const: vdo_fe0_async
> + - const: vdo_fe1_async
> + - const: gfx_fe0_async
> + - const: gfx_fe1_async
> + - const: vdo_be_async
> + - const: ethdr_top
> + power-domains:
> + maxItems: 1
> + resets:
> + maxItems: 5
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + disp_ethdr@1c114000 {
> + compatible = "mediatek,mt8195-disp-ethdr";
> + reg = <0 0x1c114000 0 0x1000>,
> + <0 0x1c115000 0 0x1000>,
> + <0 0x1c117000 0 0x1000>,
> + <0 0x1c119000 0 0x1000>,
> + <0 0x1c11A000 0 0x1000>,
> + <0 0x1c11B000 0 0x1000>,
> + <0 0x1c11C000 0 0x1000>;
> + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds";
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
> + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
> + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> + <&vdosys1 CLK_VDO1_26M_SLOW>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> + <&topckgen CLK_TOP_ETHDR_SEL>;
> + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
> + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
> + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
> + "ethdr_top";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
> + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> + };
> +
> +...
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-15 23:41 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:41 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 reset control bit for MT8195 platform.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..aab8d74496a6 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,16 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* VDOSYS1 */
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
> +
> #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-10-15 23:41 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:41 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 reset control bit for MT8195 platform.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..aab8d74496a6 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,16 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* VDOSYS1 */
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
> +
> #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit
@ 2021-10-15 23:41 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-15 23:41 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add vdosys1 reset control bit for MT8195 platform.
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..aab8d74496a6 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -26,4 +26,16 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* VDOSYS1 */
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
> +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
> +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
> +
> #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-19 16:38 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-19 16:38 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> 4 files changed, 333 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index a38e88e82d12..6e604a933ed0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index a33b13fe2b6e..b3a372cab0bd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -8,6 +8,7 @@
>
> #include <linux/soc/mediatek/mtk-cmdq.h>
> #include "mtk_drm_plane.h"
> +#include "mtk_mdp_rdma.h"
>
> int mtk_aal_clk_enable(struct device *dev);
> void mtk_aal_clk_disable(struct device *dev);
> @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_mdp_rdma_clk_enable(struct device *dev);
> +void mtk_mdp_rdma_clk_disable(struct device *dev);
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt);
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..d05b1ef976bc
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_mdp_rdma.h"
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE BIT(0)
Use one 'tab' to replace 8 space.
> +#define MDP_RDMA_RESET 0x008
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B BIT(5)
> +#define FLD_SIMPLE_MODE BIT(4)
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_COMMAND_DIV BIT(0)
> +#define FLD_EXT_PREULTRA_EN BIT(3)
> +#define FLD_RD_REQ_TYPE GENMASK(7, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_ULTRA_EN GENMASK(13, 12)
> +#define VAL_ULTRA_EN_ENABLE 1
> +#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
> +#define VAL_PRE_ULTRA_EN_ENABLE 1
> +#define FLD_EXT_ULTRA_EN BIT(18)
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB BIT(25)
> +#define FLD_BIT_NUMBER GENMASK(19, 18)
> +#define FLD_SWAP BIT(14)
> +#define FLD_UNIFORM_CONFIG BIT(17)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define FLD_SRC_FORMAT GENMASK(3, 0)
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN BIT(22)
> +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> +#define FLD_UFBDC_EN BIT(12)
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB GENMASK(22, 0)
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H GENMASK(30, 16)
> +#define FLD_MF_SRC_W GENMASK(14, 0)
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H GENMASK(30, 16)
> +#define FLD_MF_CLIP_W GENMASK(14, 0)
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
> +#define FLD_TRANS_EN BIT(16)
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 GENMASK(31, 0)
> +
> +#define RDMA_CSC_FULL709_TO_RGB 5
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +struct mtk_mdp_rdma {
> + void __iomem *regs;
> + struct clk *clk;
> + struct cmdq_client_reg cmdq_reg;
Align indent of members.
> +};
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
> + VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
> + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> +}
> +
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> +}
> +
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> +}
> +
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> + const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
> + bool csc_enable = fmt_info->is_yuv ? true : false;
> + unsigned int src_pitch_y = cfg->pitch;
> + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> + unsigned int offset_y = 0;
> +
> + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> +
> + if (!csc_enable && fmt_info->has_alpha)
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> + else
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
> + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_OUTPUT_10B);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
In mtk_plane_update_new_state(), new_state->color_encoding has the
information that non-RBG color is BT601, BT709, or BT2020.
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
Drop bpp_y, and
offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
> +
> + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
If x_left > 0, CLIP_W could still be set to width?
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
If y_top > 0, CLIP_H could still be set to height?
> +}
> +
> +int mtk_mdp_rdma_clk_enable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + pm_runtime_get_sync(dev);
Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
> + clk_prepare_enable(rdma->clk);
> + return 0;
> +}
> +
> +void mtk_mdp_rdma_clk_disable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(rdma->clk);
> + pm_runtime_put(dev);
Ditto.
Regards,
Chun-Kuang.
> +}
> +
> +static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_mdp_rdma_component_ops = {
> + .bind = mtk_mdp_rdma_bind,
> + .unbind = mtk_mdp_rdma_unbind,
> +};
> +
> +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + struct mtk_mdp_rdma *priv;
> + int ret = 0;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap rdma\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get rdma clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> + return ret;
> +}
> +
> +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> +
> +struct platform_driver mtk_mdp_rdma_driver = {
> + .probe = mtk_mdp_rdma_probe,
> + .remove = mtk_mdp_rdma_remove,
> + .driver = {
> + .name = "mediatek-mdp-rdma",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> + },
> +};
> +module_platform_driver(mtk_mdp_rdma_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..868e8ca40de3
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +struct mtk_mdp_rdma_cfg {
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-19 16:38 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-19 16:38 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> 4 files changed, 333 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index a38e88e82d12..6e604a933ed0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index a33b13fe2b6e..b3a372cab0bd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -8,6 +8,7 @@
>
> #include <linux/soc/mediatek/mtk-cmdq.h>
> #include "mtk_drm_plane.h"
> +#include "mtk_mdp_rdma.h"
>
> int mtk_aal_clk_enable(struct device *dev);
> void mtk_aal_clk_disable(struct device *dev);
> @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_mdp_rdma_clk_enable(struct device *dev);
> +void mtk_mdp_rdma_clk_disable(struct device *dev);
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt);
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..d05b1ef976bc
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_mdp_rdma.h"
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE BIT(0)
Use one 'tab' to replace 8 space.
> +#define MDP_RDMA_RESET 0x008
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B BIT(5)
> +#define FLD_SIMPLE_MODE BIT(4)
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_COMMAND_DIV BIT(0)
> +#define FLD_EXT_PREULTRA_EN BIT(3)
> +#define FLD_RD_REQ_TYPE GENMASK(7, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_ULTRA_EN GENMASK(13, 12)
> +#define VAL_ULTRA_EN_ENABLE 1
> +#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
> +#define VAL_PRE_ULTRA_EN_ENABLE 1
> +#define FLD_EXT_ULTRA_EN BIT(18)
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB BIT(25)
> +#define FLD_BIT_NUMBER GENMASK(19, 18)
> +#define FLD_SWAP BIT(14)
> +#define FLD_UNIFORM_CONFIG BIT(17)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define FLD_SRC_FORMAT GENMASK(3, 0)
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN BIT(22)
> +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> +#define FLD_UFBDC_EN BIT(12)
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB GENMASK(22, 0)
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H GENMASK(30, 16)
> +#define FLD_MF_SRC_W GENMASK(14, 0)
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H GENMASK(30, 16)
> +#define FLD_MF_CLIP_W GENMASK(14, 0)
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
> +#define FLD_TRANS_EN BIT(16)
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 GENMASK(31, 0)
> +
> +#define RDMA_CSC_FULL709_TO_RGB 5
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +struct mtk_mdp_rdma {
> + void __iomem *regs;
> + struct clk *clk;
> + struct cmdq_client_reg cmdq_reg;
Align indent of members.
> +};
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
> + VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
> + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> +}
> +
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> +}
> +
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> +}
> +
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> + const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
> + bool csc_enable = fmt_info->is_yuv ? true : false;
> + unsigned int src_pitch_y = cfg->pitch;
> + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> + unsigned int offset_y = 0;
> +
> + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> +
> + if (!csc_enable && fmt_info->has_alpha)
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> + else
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
> + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_OUTPUT_10B);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
In mtk_plane_update_new_state(), new_state->color_encoding has the
information that non-RBG color is BT601, BT709, or BT2020.
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
Drop bpp_y, and
offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
> +
> + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
If x_left > 0, CLIP_W could still be set to width?
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
If y_top > 0, CLIP_H could still be set to height?
> +}
> +
> +int mtk_mdp_rdma_clk_enable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + pm_runtime_get_sync(dev);
Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
> + clk_prepare_enable(rdma->clk);
> + return 0;
> +}
> +
> +void mtk_mdp_rdma_clk_disable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(rdma->clk);
> + pm_runtime_put(dev);
Ditto.
Regards,
Chun-Kuang.
> +}
> +
> +static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_mdp_rdma_component_ops = {
> + .bind = mtk_mdp_rdma_bind,
> + .unbind = mtk_mdp_rdma_unbind,
> +};
> +
> +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + struct mtk_mdp_rdma *priv;
> + int ret = 0;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap rdma\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get rdma clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> + return ret;
> +}
> +
> +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> +
> +struct platform_driver mtk_mdp_rdma_driver = {
> + .probe = mtk_mdp_rdma_probe,
> + .remove = mtk_mdp_rdma_remove,
> + .driver = {
> + .name = "mediatek-mdp-rdma",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> + },
> +};
> +module_platform_driver(mtk_mdp_rdma_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..868e8ca40de3
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +struct mtk_mdp_rdma_cfg {
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> --
> 2.18.0
>
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-19 16:38 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-19 16:38 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> the ovl_adaptor component.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> 4 files changed, 333 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index a38e88e82d12..6e604a933ed0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index a33b13fe2b6e..b3a372cab0bd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -8,6 +8,7 @@
>
> #include <linux/soc/mediatek/mtk-cmdq.h>
> #include "mtk_drm_plane.h"
> +#include "mtk_mdp_rdma.h"
>
> int mtk_aal_clk_enable(struct device *dev);
> void mtk_aal_clk_disable(struct device *dev);
> @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_mdp_rdma_clk_enable(struct device *dev);
> +void mtk_mdp_rdma_clk_disable(struct device *dev);
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt);
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..d05b1ef976bc
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_mdp_rdma.h"
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE BIT(0)
Use one 'tab' to replace 8 space.
> +#define MDP_RDMA_RESET 0x008
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B BIT(5)
> +#define FLD_SIMPLE_MODE BIT(4)
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_COMMAND_DIV BIT(0)
> +#define FLD_EXT_PREULTRA_EN BIT(3)
> +#define FLD_RD_REQ_TYPE GENMASK(7, 4)
> +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> +#define FLD_ULTRA_EN GENMASK(13, 12)
> +#define VAL_ULTRA_EN_ENABLE 1
> +#define FLD_PRE_ULTRA_EN GENMASK(17, 16)
> +#define VAL_PRE_ULTRA_EN_ENABLE 1
> +#define FLD_EXT_ULTRA_EN BIT(18)
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB BIT(25)
> +#define FLD_BIT_NUMBER GENMASK(19, 18)
> +#define FLD_SWAP BIT(14)
> +#define FLD_UNIFORM_CONFIG BIT(17)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define FLD_SRC_FORMAT GENMASK(3, 0)
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN BIT(22)
> +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> +#define FLD_UFBDC_EN BIT(12)
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB GENMASK(22, 0)
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H GENMASK(30, 16)
> +#define FLD_MF_SRC_W GENMASK(14, 0)
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H GENMASK(30, 16)
> +#define FLD_MF_CLIP_W GENMASK(14, 0)
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 GENMASK(31, 0)
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL GENMASK(27, 23)
> +#define FLD_TRANS_EN BIT(16)
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 GENMASK(31, 0)
> +
> +#define RDMA_CSC_FULL709_TO_RGB 5
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +struct mtk_mdp_rdma {
> + void __iomem *regs;
> + struct clk *clk;
> + struct cmdq_client_reg cmdq_reg;
Align indent of members.
> +};
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 |
> + VAL_ULTRA_EN_ENABLE << 12 | VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_GMCIF_CON, FLD_EXT_ULTRA_EN |
> + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN | FLD_RD_REQ_TYPE |
> + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> +}
> +
> +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> +}
> +
> +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_EN, FLD_ROT_ENABLE);
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET);
> +}
> +
> +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> + const struct drm_format_info *fmt_info = drm_format_info(cfg->fmt);
> + bool csc_enable = fmt_info->is_yuv ? true : false;
> + unsigned int src_pitch_y = cfg->pitch;
> + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> + unsigned int offset_y = 0;
> +
> + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> +
> + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_SWAP | FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> +
> + if (!csc_enable && fmt_info->has_alpha)
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg,
> + priv->regs, MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> + else
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_CON, FLD_OUTPUT_ARGB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, FLD_MF_BKGD_WB);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_COMP_CON,
> + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN | FLD_AFBC_EN);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_OUTPUT_10B);
> + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_TRANSFORM_0, FLD_INT_MATRIX_SEL);
In mtk_plane_update_new_state(), new_state->color_encoding has the
information that non-RBG color is BT601, BT709, or BT2020.
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top * src_pitch_y;
Drop bpp_y, and
offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;
> +
> + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_SRC_OFFSET_0, FLD_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
If x_left > 0, CLIP_W could still be set to width?
> + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv->cmdq_reg, priv->regs,
> + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
If y_top > 0, CLIP_H could still be set to height?
> +}
> +
> +int mtk_mdp_rdma_clk_enable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + pm_runtime_get_sync(dev);
Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
> + clk_prepare_enable(rdma->clk);
> + return 0;
> +}
> +
> +void mtk_mdp_rdma_clk_disable(struct device *dev)
> +{
> + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(rdma->clk);
> + pm_runtime_put(dev);
Ditto.
Regards,
Chun-Kuang.
> +}
> +
> +static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_mdp_rdma_component_ops = {
> + .bind = mtk_mdp_rdma_bind,
> + .unbind = mtk_mdp_rdma_unbind,
> +};
> +
> +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + struct mtk_mdp_rdma *priv;
> + int ret = 0;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap rdma\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get rdma clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> + return ret;
> +}
> +
> +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> +
> +struct platform_driver mtk_mdp_rdma_driver = {
> + .probe = mtk_mdp_rdma_probe,
> + .remove = mtk_mdp_rdma_remove,
> + .driver = {
> + .name = "mediatek-mdp-rdma",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> + },
> +};
> +module_platform_driver(mtk_mdp_rdma_driver);
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..868e8ca40de3
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +struct mtk_mdp_rdma_cfg {
> + unsigned int pitch;
> + unsigned int addr0;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + int fmt;
> +};
> +
> +#endif // __MTK_MDP_RDMA_H__
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-21 15:02 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:02 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add merge new API.
> 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
> 2. Add merge new advance config API. The original merge API is
> mtk_ddp_comp_funcs function prototype. The API interface parameters
> cannot be modified, so add a new config API for extension.
> 3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
> are configured with each drm plane update. Need to enable/disable
> merge with cmdq making sure all the settings taken effect in the
> same vblank.
Separate this patch into three patches.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
> 2 files changed, 82 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index b3a372cab0bd..2446ad0a4977 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_merge_start(struct device *dev);
> void mtk_merge_stop(struct device *dev);
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
>
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index b05e1df79c3d..696bb948352b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -17,6 +17,7 @@
> #define DISP_REG_MERGE_CTRL 0x000
> #define MERGE_EN 1
> #define DISP_REG_MERGE_CFG_0 0x010
> +#define DISP_REG_MERGE_CFG_1 0x014
> #define DISP_REG_MERGE_CFG_4 0x020
> #define DISP_REG_MERGE_CFG_10 0x038
> /* no swap */
> @@ -25,9 +26,12 @@
> #define DISP_REG_MERGE_CFG_12 0x040
> #define CFG_10_10_1PI_2PO_BUF_MODE 6
> #define CFG_10_10_2PI_2PO_BUF_MODE 8
> +#define CFG_11_10_1PI_2PO_MERGE 18
> #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> #define DISP_REG_MERGE_CFG_24 0x070
> #define DISP_REG_MERGE_CFG_25 0x074
> +#define DISP_REG_MERGE_CFG_26 0x078
> +#define DISP_REG_MERGE_CFG_27 0x07c
> #define DISP_REG_MERGE_CFG_36 0x0a0
> #define ULTRA_EN BIT(0)
> #define PREULTRA_EN BIT(4)
> @@ -54,26 +58,52 @@
> #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
>
> +#define DISP_REG_MERGE_MUTE_0 0xf00
> +
> struct mtk_disp_merge {
> void __iomem *regs;
> struct clk *clk;
> struct clk *async_clk;
> struct cmdq_client_reg cmdq_reg;
> bool fifo_en;
> + bool mute_support;
Align indent of members.
> };
>
> void mtk_merge_start(struct device *dev)
> +{
> + mtk_merge_enable(dev, NULL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_merge_disable(dev, NULL);
> }
>
> -void mtk_merge_stop(struct device *dev)
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
support, but the naming make them so different. So I would like this
function name to be mtk_merge_start_cmdq().
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
Ditto.
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
I'm not sure whether it's worth to have this function. It seems that
mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
this function into mtk_merge_enable().
And I would like to mute in mtk_merge_disable() to let register be restored.
Regards,
Chun-Kuang.
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->mute_support)
> + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_MUTE_0);
> }
>
> static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> void mtk_merge_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
>
> - if (!h || !w) {
> - dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> + if (!h || !l_w) {
> + dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
> return;
> }
>
> @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
> mode = CFG_10_10_2PI_2PO_BUF_MODE;
> }
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + if (r_w)
> + mode = CFG_11_10_1PI_2PO_MERGE;
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_0);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_4);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + /*
> + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> + * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
> + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> + * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
> + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_24);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> - DISP_REG_MERGE_CFG_25);
> + if (r_w)
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> + else
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> +
> + /*
> + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
> + * Only take effect when the merge is setting to merge mode.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_27);
> +
> mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
> @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
> priv->fifo_en = of_property_read_bool(dev->of_node,
> "mediatek,merge-fifo-en");
>
> + priv->mute_support = of_property_read_bool(dev->of_node,
> + "mediatek,merge-mute");
> platform_set_drvdata(pdev, priv);
>
> ret = component_add(dev, &mtk_disp_merge_component_ops);
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-21 15:02 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:02 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add merge new API.
> 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
> 2. Add merge new advance config API. The original merge API is
> mtk_ddp_comp_funcs function prototype. The API interface parameters
> cannot be modified, so add a new config API for extension.
> 3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
> are configured with each drm plane update. Need to enable/disable
> merge with cmdq making sure all the settings taken effect in the
> same vblank.
Separate this patch into three patches.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
> 2 files changed, 82 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index b3a372cab0bd..2446ad0a4977 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_merge_start(struct device *dev);
> void mtk_merge_stop(struct device *dev);
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
>
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index b05e1df79c3d..696bb948352b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -17,6 +17,7 @@
> #define DISP_REG_MERGE_CTRL 0x000
> #define MERGE_EN 1
> #define DISP_REG_MERGE_CFG_0 0x010
> +#define DISP_REG_MERGE_CFG_1 0x014
> #define DISP_REG_MERGE_CFG_4 0x020
> #define DISP_REG_MERGE_CFG_10 0x038
> /* no swap */
> @@ -25,9 +26,12 @@
> #define DISP_REG_MERGE_CFG_12 0x040
> #define CFG_10_10_1PI_2PO_BUF_MODE 6
> #define CFG_10_10_2PI_2PO_BUF_MODE 8
> +#define CFG_11_10_1PI_2PO_MERGE 18
> #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> #define DISP_REG_MERGE_CFG_24 0x070
> #define DISP_REG_MERGE_CFG_25 0x074
> +#define DISP_REG_MERGE_CFG_26 0x078
> +#define DISP_REG_MERGE_CFG_27 0x07c
> #define DISP_REG_MERGE_CFG_36 0x0a0
> #define ULTRA_EN BIT(0)
> #define PREULTRA_EN BIT(4)
> @@ -54,26 +58,52 @@
> #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
>
> +#define DISP_REG_MERGE_MUTE_0 0xf00
> +
> struct mtk_disp_merge {
> void __iomem *regs;
> struct clk *clk;
> struct clk *async_clk;
> struct cmdq_client_reg cmdq_reg;
> bool fifo_en;
> + bool mute_support;
Align indent of members.
> };
>
> void mtk_merge_start(struct device *dev)
> +{
> + mtk_merge_enable(dev, NULL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_merge_disable(dev, NULL);
> }
>
> -void mtk_merge_stop(struct device *dev)
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
support, but the naming make them so different. So I would like this
function name to be mtk_merge_start_cmdq().
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
Ditto.
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
I'm not sure whether it's worth to have this function. It seems that
mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
this function into mtk_merge_enable().
And I would like to mute in mtk_merge_disable() to let register be restored.
Regards,
Chun-Kuang.
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->mute_support)
> + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_MUTE_0);
> }
>
> static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> void mtk_merge_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
>
> - if (!h || !w) {
> - dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> + if (!h || !l_w) {
> + dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
> return;
> }
>
> @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
> mode = CFG_10_10_2PI_2PO_BUF_MODE;
> }
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + if (r_w)
> + mode = CFG_11_10_1PI_2PO_MERGE;
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_0);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_4);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + /*
> + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> + * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
> + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> + * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
> + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_24);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> - DISP_REG_MERGE_CFG_25);
> + if (r_w)
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> + else
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> +
> + /*
> + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
> + * Only take effect when the merge is setting to merge mode.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_27);
> +
> mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
> @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
> priv->fifo_en = of_property_read_bool(dev->of_node,
> "mediatek,merge-fifo-en");
>
> + priv->mute_support = of_property_read_bool(dev->of_node,
> + "mediatek,merge-mute");
> platform_set_drvdata(pdev, priv);
>
> ret = component_add(dev, &mtk_disp_merge_component_ops);
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-21 15:02 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:02 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add merge new API.
> 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
> 2. Add merge new advance config API. The original merge API is
> mtk_ddp_comp_funcs function prototype. The API interface parameters
> cannot be modified, so add a new config API for extension.
> 3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges
> are configured with each drm plane update. Need to enable/disable
> merge with cmdq making sure all the settings taken effect in the
> same vblank.
Separate this patch into three patches.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++---
> 2 files changed, 82 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index b3a372cab0bd..2446ad0a4977 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_merge_start(struct device *dev);
> void mtk_merge_stop(struct device *dev);
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);
>
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> index b05e1df79c3d..696bb948352b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -17,6 +17,7 @@
> #define DISP_REG_MERGE_CTRL 0x000
> #define MERGE_EN 1
> #define DISP_REG_MERGE_CFG_0 0x010
> +#define DISP_REG_MERGE_CFG_1 0x014
> #define DISP_REG_MERGE_CFG_4 0x020
> #define DISP_REG_MERGE_CFG_10 0x038
> /* no swap */
> @@ -25,9 +26,12 @@
> #define DISP_REG_MERGE_CFG_12 0x040
> #define CFG_10_10_1PI_2PO_BUF_MODE 6
> #define CFG_10_10_2PI_2PO_BUF_MODE 8
> +#define CFG_11_10_1PI_2PO_MERGE 18
> #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> #define DISP_REG_MERGE_CFG_24 0x070
> #define DISP_REG_MERGE_CFG_25 0x074
> +#define DISP_REG_MERGE_CFG_26 0x078
> +#define DISP_REG_MERGE_CFG_27 0x07c
> #define DISP_REG_MERGE_CFG_36 0x0a0
> #define ULTRA_EN BIT(0)
> #define PREULTRA_EN BIT(4)
> @@ -54,26 +58,52 @@
> #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
>
> +#define DISP_REG_MERGE_MUTE_0 0xf00
> +
> struct mtk_disp_merge {
> void __iomem *regs;
> struct clk *clk;
> struct clk *async_clk;
> struct cmdq_client_reg cmdq_reg;
> bool fifo_en;
> + bool mute_support;
Align indent of members.
> };
>
> void mtk_merge_start(struct device *dev)
> +{
> + mtk_merge_enable(dev, NULL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_merge_disable(dev, NULL);
> }
>
> -void mtk_merge_stop(struct device *dev)
> +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
support, but the naming make them so different. So I would like this
function name to be mtk_merge_start_cmdq().
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)
Ditto.
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
>
> - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)
I'm not sure whether it's worth to have this function. It seems that
mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
this function into mtk_merge_enable().
And I would like to mute in mtk_merge_disable() to let register be restored.
Regards,
Chun-Kuang.
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->mute_support)
> + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_MUTE_0);
> }
>
> static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> void mtk_merge_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
> + unsigned int h, unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
>
> - if (!h || !w) {
> - dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
> + if (!h || !l_w) {
> + dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
> return;
> }
>
> @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w,
> mode = CFG_10_10_2PI_2PO_BUF_MODE;
> }
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + if (r_w)
> + mode = CFG_11_10_1PI_2PO_MERGE;
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_0);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_1);
> + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_4);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + /*
> + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> + * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
> + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> + * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
> + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_24);
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> - DISP_REG_MERGE_CFG_25);
> + if (r_w)
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> + else
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_25);
> +
> + /*
> + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
> + * Only take effect when the merge is setting to merge mode.
> + */
> + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_26);
> + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
> + DISP_REG_MERGE_CFG_27);
> +
> mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
> DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
> @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
> priv->fifo_en = of_property_read_bool(dev->of_node,
> "mediatek,merge-fifo-en");
>
> + priv->mute_support = of_property_read_bool(dev->of_node,
> + "mediatek,merge-mute");
> platform_set_drvdata(pdev, priv);
>
> ret = component_add(dev, &mtk_disp_merge_component_ops);
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-21 15:44 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:44 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
>
> ETHDR is a part of ovl_adaptor.
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combine
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> 3 files changed, 429 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 6e604a933ed0..fb158a1e7f06 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> + mtk_ethdr.o \
> mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..99e5a95aebed
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
Align the indent with mdp rdma driver.
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define MIXER_INx_MODE_BYPASS 0
MIXER_INX_MODE_BYPASS
> +#define MIXER_INx_MODE_EVEN_EXTEND 1
> +#define MIXER_INx_MODE_ODD_EXTEND 2
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *mmsys_dev;
> + spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> + unsigned long flags;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + if (!priv->vblank_cb) {
> + spin_unlock_irqrestore(&priv->lock, flags);
> + return IRQ_NONE;
> + }
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
> + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
fmt is useless, so remove.
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, 0, cmdq_pkt);
> + return;
> + }
> +
> + if (pending->x % 2)
> + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, mixer_pad_mode, cmdq_pkt);
Drop mixer_pad_mode, and
mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx + 1,
pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
MIXER_INx_MODE_BYPASS,
cmdq_pkt);
Regards,
Chun-Kuang.
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, pending->width / 2 - 1, cmdq_pkt);
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
> + mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-21 15:44 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:44 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
>
> ETHDR is a part of ovl_adaptor.
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combine
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> 3 files changed, 429 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 6e604a933ed0..fb158a1e7f06 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> + mtk_ethdr.o \
> mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..99e5a95aebed
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
Align the indent with mdp rdma driver.
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define MIXER_INx_MODE_BYPASS 0
MIXER_INX_MODE_BYPASS
> +#define MIXER_INx_MODE_EVEN_EXTEND 1
> +#define MIXER_INx_MODE_ODD_EXTEND 2
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *mmsys_dev;
> + spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> + unsigned long flags;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + if (!priv->vblank_cb) {
> + spin_unlock_irqrestore(&priv->lock, flags);
> + return IRQ_NONE;
> + }
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
> + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
fmt is useless, so remove.
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, 0, cmdq_pkt);
> + return;
> + }
> +
> + if (pending->x % 2)
> + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, mixer_pad_mode, cmdq_pkt);
Drop mixer_pad_mode, and
mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx + 1,
pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
MIXER_INx_MODE_BYPASS,
cmdq_pkt);
Regards,
Chun-Kuang.
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, pending->width / 2 - 1, cmdq_pkt);
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
> + mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-21 15:44 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-21 15:44 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
>
> ETHDR is a part of ovl_adaptor.
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combine
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> 3 files changed, 429 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 6e604a933ed0..fb158a1e7f06 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> + mtk_ethdr.o \
> mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..99e5a95aebed
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_INTEN 0x4
> + #define MIX_FME_CPL_INTEN BIT(1)
Align the indent with mdp rdma driver.
> +#define MIX_INTSTA 0x8
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> + #define OUTPUT_NO_RND BIT(3)
> + #define SOURCE_RGB_SEL BIT(7)
> + #define BACKGROUND_RELAY (4 << 9)
> +#define MIX_ROI_BGCLR 0x20
> + #define BGCLR_BLACK 0xff000000
> +#define MIX_SRC_CON 0x24
> + #define MIX_SRC_L0_EN BIT(0)
> +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> + #define NON_PREMULTI_SOURCE (2 << 12)
> +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> +
> +#define MIXER_INx_MODE_BYPASS 0
MIXER_INX_MODE_BYPASS
> +#define MIXER_INx_MODE_EVEN_EXTEND 1
> +#define MIXER_INx_MODE_ODD_EXTEND 2
> +#define DEFAULT_9BIT_ALPHA 0x100
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> + struct device *mmsys_dev;
> + spinlock_t lock; /* protects vblank_cb and vblank_cb_data */
> + void (*vblank_cb)(void *data);
> + void *vblank_cb_data;
> + int irq;
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +void mtk_ethdr_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = vblank_cb;
> + priv->vblank_cb_data = vblank_cb_data;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +void mtk_ethdr_disable_vblank(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + priv->vblank_cb = NULL;
> + priv->vblank_cb_data = NULL;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> +}
> +
> +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> +{
> + struct mtk_ethdr *priv = dev_id;
> + unsigned long flags;
> +
> + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + if (!priv->vblank_cb) {
> + spin_unlock_irqrestore(&priv->lock, flags);
> + return IRQ_NONE;
> + }
> +
> + priv->vblank_cb(priv->vblank_cb_data);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
> + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
fmt is useless, so remove.
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx >= 4)
> + return;
> +
> + if (!pending->enable) {
> + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, MIXER_INx_MODE_BYPASS, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, 0, cmdq_pkt);
> + return;
> + }
> +
> + if (pending->x % 2)
> + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> +
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE,
> + idx + 1, mixer_pad_mode, cmdq_pkt);
Drop mixer_pad_mode, and
mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx + 1,
pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
MIXER_INx_MODE_BYPASS,
cmdq_pkt);
Regards,
Chun-Kuang.
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> + idx + 1, pending->width / 2 - 1, cmdq_pkt);
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 0, cmdq_pkt);
> + } else {
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_HDR_ALPHA_SEL,
> + idx + 1, 1, cmdq_pkt);
> + }
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> + mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> +
> + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending->width, &mixer->cmdq_base,
> + mixer->regs, MIX_L_SRC_SIZE(idx));
> + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> + 0x1ff);
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> + BIT(idx));
> +}
> +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
2021-10-14 14:56 ` AngeloGioacchino Del Regno
(?)
@ 2021-10-22 7:05 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 16:56 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/21 08:21, Nancy.Lin ha scritto:
> > MT8195 vdosys1 has more than 32 reset bits and a different reset
> > base
> > than other chips. Modify mmsys for support 64 bit and different
> > reset
> > base.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> > drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> > 3 files changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 648baaec112b..f67801c42fd9 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -123,6 +123,7 @@
> > #define MT8195_VDO1_MIXER_SOUT_SEL_IN
> > 0xf68
> > #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 <<
> > 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
>
> All other definitions are indented with tabulations, but these are
> spaces here.
> Please, do not mix formatting.
>
> Regards,
> - Angelo
OK, I will fix it.
Regards,
Nancy
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-22 7:05 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 16:56 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/21 08:21, Nancy.Lin ha scritto:
> > MT8195 vdosys1 has more than 32 reset bits and a different reset
> > base
> > than other chips. Modify mmsys for support 64 bit and different
> > reset
> > base.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> > drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> > 3 files changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 648baaec112b..f67801c42fd9 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -123,6 +123,7 @@
> > #define MT8195_VDO1_MIXER_SOUT_SEL_IN
> > 0xf68
> > #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 <<
> > 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
>
> All other definitions are indented with tabulations, but these are
> spaces here.
> Please, do not mix formatting.
>
> Regards,
> - Angelo
OK, I will fix it.
Regards,
Nancy
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
@ 2021-10-22 7:05 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 16:56 +0200, AngeloGioacchino Del Regno wrote:
> Il 04/10/21 08:21, Nancy.Lin ha scritto:
> > MT8195 vdosys1 has more than 32 reset bits and a different reset
> > base
> > than other chips. Modify mmsys for support 64 bit and different
> > reset
> > base.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> > drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++-----
> > drivers/soc/mediatek/mtk-mmsys.h | 2 ++
> > 3 files changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > index 648baaec112b..f67801c42fd9 100644
> > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -123,6 +123,7 @@
> > #define MT8195_VDO1_MIXER_SOUT_SEL_IN
> > 0xf68
> > #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 <<
> > 0)
> >
> > +#define MT8195_VDO1_SW0_RST_B 0x1d0
>
> All other definitions are indented with tabulations, but these are
> spaces here.
> Please, do not mix formatting.
>
> Regards,
> - Angelo
OK, I will fix it.
Regards,
Nancy
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
2021-10-15 23:37 ` Chun-Kuang Hu
(?)
@ 2021-10-22 7:18 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:18 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add vdosys1 ETHDR definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,ethdr.yaml | 145
> > ++++++++++++++++++
> > 1 file changed, 145 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> > aml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > new file mode 100644
> > index 000000000000..e127f0b392d0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > @@ -0,0 +1,145 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslRmbyBny$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslYl8ES2J$
> >
> > +
> > +title: Mediatek Ethdr Device Tree Bindings
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > + - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > + ETHDR is designed for HDR video and graphics conversion in the
> > external display path.
> > + It handles multiple HDR input types and performs tone mapping,
> > color space/color
> > + format conversion, and then combine different layers, output the
> > required HDR or
> > + SDR signal to the subsequent display path. This engine is
> > composed of two video
> > + frontends, two graphic frontends, one video backend and a mixer.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8195-disp-ethdr
> > + reg:
> > + maxItems: 7
> > + reg-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + interrupts:
> > + minItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
>
> In description, you does not mention that ethdr has dma function. I
> expect that video front end and graphics front end direct link to
> another hardware function block and no dma function. If it has both
> direct link and dma function, add explain in description.
>
There is DMA hardware inside the ETHDR engine, which are DS and ADL.
The two engines can read hardware reg settings from dram and then apply
the settings during the v-blanking period.
I will explain it in description.
Regards,
Nancy
> > + minItems: 1
> > + maxItems: 2
> > + clocks:
> > + items:
> > + - description: mixer clock
> > + - description: video frontend 0 clock
> > + - description: video frontend 1 clock
> > + - description: graphic frontend 0 clock
> > + - description: graphic frontend 1 clock
> > + - description: video backend clock
> > + - description: autodownload and menuload clock
> > + - description: video frontend 0 async clock
> > + - description: video frontend 1 async clock
> > + - description: graphic frontend 0 async clock
> > + - description: graphic frontend 1 async clock
> > + - description: video backend async clock
> > + - description: ethdr top clock
> > + clock-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + - const: vdo_fe0_async
> > + - const: vdo_fe1_async
> > + - const: gfx_fe0_async
> > + - const: gfx_fe1_async
> > + - const: vdo_be_async
> > + - const: ethdr_top
> > + power-domains:
> > + maxItems: 1
> > + resets:
> > + maxItems: 5
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + disp_ethdr@1c114000 {
> > + compatible = "mediatek,mt8195-disp-ethdr";
> > + reg = <0 0x1c114000 0 0x1000>,
> > + <0 0x1c115000 0 0x1000>,
> > + <0 0x1c117000 0 0x1000>,
> > + <0 0x1c119000 0 0x1000>,
> > + <0 0x1c11A000 0 0x1000>,
> > + <0 0x1c11B000 0 0x1000>,
> > + <0 0x1c11C000 0 0x1000>;
> > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0",
> > "gfx_fe1",
> > + "vdo_be", "adl_ds";
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX
> > 0x4000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x5000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x7000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x9000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xA000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xB000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xC000 0x1000>;
> > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> > + <&vdosys1 CLK_VDO1_26M_SLOW>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> > + <&topckgen CLK_TOP_ETHDR_SEL>;
> > + clock-names = "mixer", "vdo_fe0", "vdo_fe1",
> > "gfx_fe0", "gfx_fe1",
> > + "vdo_be", "adl_ds", "vdo_fe0_async",
> > "vdo_fe1_async",
> > + "gfx_fe0_async",
> > "gfx_fe1_async","vdo_be_async",
> > + "ethdr_top";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> > + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*
> > disp mixer */
> > + resets = <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-22 7:18 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:18 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add vdosys1 ETHDR definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,ethdr.yaml | 145
> > ++++++++++++++++++
> > 1 file changed, 145 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> > aml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > new file mode 100644
> > index 000000000000..e127f0b392d0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > @@ -0,0 +1,145 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslRmbyBny$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslYl8ES2J$
> >
> > +
> > +title: Mediatek Ethdr Device Tree Bindings
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > + - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > + ETHDR is designed for HDR video and graphics conversion in the
> > external display path.
> > + It handles multiple HDR input types and performs tone mapping,
> > color space/color
> > + format conversion, and then combine different layers, output the
> > required HDR or
> > + SDR signal to the subsequent display path. This engine is
> > composed of two video
> > + frontends, two graphic frontends, one video backend and a mixer.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8195-disp-ethdr
> > + reg:
> > + maxItems: 7
> > + reg-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + interrupts:
> > + minItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
>
> In description, you does not mention that ethdr has dma function. I
> expect that video front end and graphics front end direct link to
> another hardware function block and no dma function. If it has both
> direct link and dma function, add explain in description.
>
There is DMA hardware inside the ETHDR engine, which are DS and ADL.
The two engines can read hardware reg settings from dram and then apply
the settings during the v-blanking period.
I will explain it in description.
Regards,
Nancy
> > + minItems: 1
> > + maxItems: 2
> > + clocks:
> > + items:
> > + - description: mixer clock
> > + - description: video frontend 0 clock
> > + - description: video frontend 1 clock
> > + - description: graphic frontend 0 clock
> > + - description: graphic frontend 1 clock
> > + - description: video backend clock
> > + - description: autodownload and menuload clock
> > + - description: video frontend 0 async clock
> > + - description: video frontend 1 async clock
> > + - description: graphic frontend 0 async clock
> > + - description: graphic frontend 1 async clock
> > + - description: video backend async clock
> > + - description: ethdr top clock
> > + clock-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + - const: vdo_fe0_async
> > + - const: vdo_fe1_async
> > + - const: gfx_fe0_async
> > + - const: gfx_fe1_async
> > + - const: vdo_be_async
> > + - const: ethdr_top
> > + power-domains:
> > + maxItems: 1
> > + resets:
> > + maxItems: 5
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + disp_ethdr@1c114000 {
> > + compatible = "mediatek,mt8195-disp-ethdr";
> > + reg = <0 0x1c114000 0 0x1000>,
> > + <0 0x1c115000 0 0x1000>,
> > + <0 0x1c117000 0 0x1000>,
> > + <0 0x1c119000 0 0x1000>,
> > + <0 0x1c11A000 0 0x1000>,
> > + <0 0x1c11B000 0 0x1000>,
> > + <0 0x1c11C000 0 0x1000>;
> > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0",
> > "gfx_fe1",
> > + "vdo_be", "adl_ds";
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX
> > 0x4000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x5000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x7000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x9000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xA000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xB000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xC000 0x1000>;
> > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> > + <&vdosys1 CLK_VDO1_26M_SLOW>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> > + <&topckgen CLK_TOP_ETHDR_SEL>;
> > + clock-names = "mixer", "vdo_fe0", "vdo_fe1",
> > "gfx_fe0", "gfx_fe1",
> > + "vdo_be", "adl_ds", "vdo_fe0_async",
> > "vdo_fe1_async",
> > + "gfx_fe0_async",
> > "gfx_fe1_async","vdo_be_async",
> > + "ethdr_top";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> > + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*
> > disp mixer */
> > + resets = <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-10-22 7:18 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:18 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add vdosys1 ETHDR definition.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,ethdr.yaml | 145
> > ++++++++++++++++++
> > 1 file changed, 145 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
> > aml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > new file mode 100644
> > index 000000000000..e127f0b392d0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
> > .yaml
> > @@ -0,0 +1,145 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslRmbyBny$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6Q5VtKDLZHoYN5bEe_S_yTm7kWd_rwPjidk5R6NBVLXVIMVYK4VVXWslYl8ES2J$
> >
> > +
> > +title: Mediatek Ethdr Device Tree Bindings
> > +
> > +maintainers:
> > + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > + - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > + ETHDR is designed for HDR video and graphics conversion in the
> > external display path.
> > + It handles multiple HDR input types and performs tone mapping,
> > color space/color
> > + format conversion, and then combine different layers, output the
> > required HDR or
> > + SDR signal to the subsequent display path. This engine is
> > composed of two video
> > + frontends, two graphic frontends, one video backend and a mixer.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: mediatek,mt8195-disp-ethdr
> > + reg:
> > + maxItems: 7
> > + reg-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + interrupts:
> > + minItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
>
> In description, you does not mention that ethdr has dma function. I
> expect that video front end and graphics front end direct link to
> another hardware function block and no dma function. If it has both
> direct link and dma function, add explain in description.
>
There is DMA hardware inside the ETHDR engine, which are DS and ADL.
The two engines can read hardware reg settings from dram and then apply
the settings during the v-blanking period.
I will explain it in description.
Regards,
Nancy
> > + minItems: 1
> > + maxItems: 2
> > + clocks:
> > + items:
> > + - description: mixer clock
> > + - description: video frontend 0 clock
> > + - description: video frontend 1 clock
> > + - description: graphic frontend 0 clock
> > + - description: graphic frontend 1 clock
> > + - description: video backend clock
> > + - description: autodownload and menuload clock
> > + - description: video frontend 0 async clock
> > + - description: video frontend 1 async clock
> > + - description: graphic frontend 0 async clock
> > + - description: graphic frontend 1 async clock
> > + - description: video backend async clock
> > + - description: ethdr top clock
> > + clock-names:
> > + items:
> > + - const: mixer
> > + - const: vdo_fe0
> > + - const: vdo_fe1
> > + - const: gfx_fe0
> > + - const: gfx_fe1
> > + - const: vdo_be
> > + - const: adl_ds
> > + - const: vdo_fe0_async
> > + - const: vdo_fe1_async
> > + - const: gfx_fe0_async
> > + - const: gfx_fe1_async
> > + - const: vdo_be_async
> > + - const: ethdr_top
> > + power-domains:
> > + maxItems: 1
> > + resets:
> > + maxItems: 5
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - power-domains
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + disp_ethdr@1c114000 {
> > + compatible = "mediatek,mt8195-disp-ethdr";
> > + reg = <0 0x1c114000 0 0x1000>,
> > + <0 0x1c115000 0 0x1000>,
> > + <0 0x1c117000 0 0x1000>,
> > + <0 0x1c119000 0 0x1000>,
> > + <0 0x1c11A000 0 0x1000>,
> > + <0 0x1c11B000 0 0x1000>,
> > + <0 0x1c11C000 0 0x1000>;
> > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0",
> > "gfx_fe1",
> > + "vdo_be", "adl_ds";
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX
> > 0x4000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x5000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x7000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0x9000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xA000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xB000 0x1000>,
> > + <&gce1 SUBSYS_1c11XXXX
> > 0xC000 0x1000>;
> > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> > + <&vdosys1 CLK_VDO1_26M_SLOW>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> > + <&topckgen CLK_TOP_ETHDR_SEL>;
> > + clock-names = "mixer", "vdo_fe0", "vdo_fe1",
> > "gfx_fe0", "gfx_fe1",
> > + "vdo_be", "adl_ds", "vdo_fe0_async",
> > "vdo_fe1_async",
> > + "gfx_fe0_async",
> > "gfx_fe1_async","vdo_be_async",
> > + "ethdr_top";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> > + interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*
> > disp mixer */
> > + resets = <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
> > + <&vdosys1
> > MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-10-14 15:01 ` AngeloGioacchino Del Regno
(?)
@ 2021-10-22 7:33 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 17:01 +0200, AngeloGioacchino Del Regno wrote:
> > Add mtk-mutex support for mt8195 vdosys1.
> > The vdosys1 path component contains ovl_adaptor, merge5,
> > and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> > so change it to support multi-bit control.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++------
> > -------
> > 1 file changed, 175 insertions(+), 121 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 36502b27fe20..7767fedbd14f 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -29,113 +29,142 @@
> >
> > #define INT_MUTEX BIT(1)
> >
> > -#define MT8167_MUTEX_MOD_DISP_PWM 1
>
> This patch doesn't only add support for MT8195 vdosys1, but also
> changes
> all definitions to a different "format", and also changes the type
> for
> "mutex_mod" from int to long.
> In reality, the actual functional change is minimal, compared to the
> size of
> this entire patch.
>
> Please, split this patch in two parts: one patch changing the defines
> and
> the mutex_mod type (specifying that it's a preparation for adding
> support for
> mt8195 vdosys1 mutex) and one patch adding such support.
>
> Thanks!
>
> Regards,
> - Angelo
OK, I will separate it into two patches.
Regards,
Nancy
>
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-22 7:33 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 17:01 +0200, AngeloGioacchino Del Regno wrote:
> > Add mtk-mutex support for mt8195 vdosys1.
> > The vdosys1 path component contains ovl_adaptor, merge5,
> > and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> > so change it to support multi-bit control.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++------
> > -------
> > 1 file changed, 175 insertions(+), 121 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 36502b27fe20..7767fedbd14f 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -29,113 +29,142 @@
> >
> > #define INT_MUTEX BIT(1)
> >
> > -#define MT8167_MUTEX_MOD_DISP_PWM 1
>
> This patch doesn't only add support for MT8195 vdosys1, but also
> changes
> all definitions to a different "format", and also changes the type
> for
> "mutex_mod" from int to long.
> In reality, the actual functional change is minimal, compared to the
> size of
> this entire patch.
>
> Please, split this patch in two parts: one patch changing the defines
> and
> the mutex_mod type (specifying that it's a preparation for adding
> support for
> mt8195 vdosys1 mutex) and one patch adding such support.
>
> Thanks!
>
> Regards,
> - Angelo
OK, I will separate it into two patches.
Regards,
Nancy
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-10-22 7:33 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-22 7:33 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Thu, 2021-10-14 at 17:01 +0200, AngeloGioacchino Del Regno wrote:
> > Add mtk-mutex support for mt8195 vdosys1.
> > The vdosys1 path component contains ovl_adaptor, merge5,
> > and dp_intf1. Ovl_adaptor is composed of several sub-elements,
> > so change it to support multi-bit control.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++------
> > -------
> > 1 file changed, 175 insertions(+), 121 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 36502b27fe20..7767fedbd14f 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -29,113 +29,142 @@
> >
> > #define INT_MUTEX BIT(1)
> >
> > -#define MT8167_MUTEX_MOD_DISP_PWM 1
>
> This patch doesn't only add support for MT8195 vdosys1, but also
> changes
> all definitions to a different "format", and also changes the type
> for
> "mutex_mod" from int to long.
> In reality, the actual functional change is minimal, compared to the
> size of
> this entire patch.
>
> Please, split this patch in two parts: one patch changing the defines
> and
> the mutex_mod type (specifying that it's a preparation for adding
> support for
> mt8195 vdosys1 mutex) and one patch adding such support.
>
> Thanks!
>
> Regards,
> - Angelo
OK, I will separate it into two patches.
Regards,
Nancy
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
2021-10-19 16:38 ` Chun-Kuang Hu
(?)
@ 2021-10-25 1:48 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 1:48 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Wed, 2021-10-20 at 00:38 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> > the ovl_adaptor component.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305
> > ++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> > 4 files changed, 333 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index a38e88e82d12..6e604a933ed0 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index a33b13fe2b6e..b3a372cab0bd 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -8,6 +8,7 @@
> >
> > #include <linux/soc/mediatek/mtk-cmdq.h>
> > #include "mtk_drm_plane.h"
> > +#include "mtk_mdp_rdma.h"
> >
> > int mtk_aal_clk_enable(struct device *dev);
> > void mtk_aal_clk_disable(struct device *dev);
> > @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_mdp_rdma_clk_enable(struct device *dev);
> > +void mtk_mdp_rdma_clk_disable(struct device *dev);
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt);
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..d05b1ef976bc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
OK.
>
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE BIT(0)
>
> Use one 'tab' to replace 8 space.
OK.
>
> > +#define MDP_RDMA_RESET 0x008
> > +#define MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B BIT(5)
> > +#define FLD_SIMPLE_MODE BIT(4)
> > +#define MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_COMMAND_DIV BIT(0)
> > +#define FLD_EXT_PREULTRA_EN BIT(3)
> > +#define FLD_RD_REQ_TYPE GENMASK(7,
> > 4)
> > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> > +#define FLD_ULTRA_EN GENMASK(13,
> > 12)
> > +#define VAL_ULTRA_EN_ENABLE 1
> > +#define FLD_PRE_ULTRA_EN GENMASK(17,
> > 16)
> > +#define VAL_PRE_ULTRA_EN_ENABLE 1
> > +#define FLD_EXT_ULTRA_EN BIT(18)
> > +#define MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB BIT(25)
> > +#define FLD_BIT_NUMBER GENMASK(19,
> > 18)
> > +#define FLD_SWAP BIT(14)
> > +#define FLD_UNIFORM_CONFIG BIT(17)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define FLD_SRC_FORMAT GENMASK(3,
> > 0)
> > +#define MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN BIT(22)
> > +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> > +#define FLD_UFBDC_EN BIT(12)
> > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB GENMASK(22,
> > 0)
> > +#define MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H GENMASK(30,
> > 16)
> > +#define FLD_MF_SRC_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H GENMASK(30,
> > 16)
> > +#define FLD_MF_CLIP_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 GENMASK(31,
> > 0)
> > +#define MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL GENMASK(27,
> > 23)
> > +#define FLD_TRANS_EN BIT(16)
> > +#define MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 GENMASK(31,
> > 0)
> > +
> > +#define RDMA_CSC_FULL709_TO_RGB 5
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +struct mtk_mdp_rdma {
> > + void __iomem *regs;
> > + struct clk *clk;
> > + struct cmdq_client_reg cmdq_reg;
>
> Align indent of members.
OK.
>
> > +};
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct
> > cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN |
> > VAL_PRE_ULTRA_EN_ENABLE << 16 |
> > + VAL_ULTRA_EN_ENABLE << 12 |
> > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_GMCIF_CON,
> > FLD_EXT_ULTRA_EN |
> > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN |
> > FLD_RD_REQ_TYPE |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> > +}
> > +
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv-
> > >cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > +}
> > +
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > +}
> > +
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(cfg->fmt);
> > + bool csc_enable = fmt_info->is_yuv ? true : false;
> > + unsigned int src_pitch_y = cfg->pitch;
> > + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> > + unsigned int offset_y = 0;
> > +
> > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_SWAP |
> > FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> > +
> > + if (!csc_enable && fmt_info->has_alpha)
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > FLD_MF_BKGD_WB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs, MDP_RDMA_COMP_CON,
> > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN |
> > FLD_AFBC_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_OUTPUT_10B);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23,
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0,
> > FLD_INT_MATRIX_SEL);
>
> In mtk_plane_update_new_state(), new_state->color_encoding has the
> information that non-RBG color is BT601, BT709, or BT2020.
>
OK, I will add color encoding info for color space convert.
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top *
> > src_pitch_y;
>
> Drop bpp_y, and
>
> offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top *
> src_pitch_y;
>
OK.
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_OFFSET_0,
> > FLD_SRC_OFFSET_0);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
>
> If x_left > 0, CLIP_W could still be set to width?
>
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
>
> If y_top > 0, CLIP_H could still be set to height?
>
The parameters (x_left, y_top, width, height) in mtk_mdp_rdma_cfg
struct means: rdma read data from frame buffer base addr offset
(x_left, y_top) with size (width, height). The parameters (width,
height) is not the source image size but the real size that RDMA want
to read.
> > +}
> > +
> > +int mtk_mdp_rdma_clk_enable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + pm_runtime_get_sync(dev);
>
> Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
OK, I will move the pm runtime control to ovl_adaptor.
>
> > + clk_prepare_enable(rdma->clk);
> > + return 0;
> > +}
> > +
> > +void mtk_mdp_rdma_clk_disable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + clk_disable_unprepare(rdma->clk);
> > + pm_runtime_put(dev);
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
Regards,
Nancy
> > +}
> > +
> > +static int mtk_mdp_rdma_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_mdp_rdma_component_ops = {
> > + .bind = mtk_mdp_rdma_bind,
> > + .unbind = mtk_mdp_rdma_unbind,
> > +};
> > +
> > +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + struct mtk_mdp_rdma *priv;
> > + int ret = 0;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap rdma\n");
> > + return PTR_ERR(priv->regs);
> > + }
> > +
> > + priv->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(priv->clk)) {
> > + dev_err(dev, "failed to get rdma clk\n");
> > + return PTR_ERR(priv->clk);
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + platform_set_drvdata(pdev, priv);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > + return ret;
> > +}
> > +
> > +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] =
> > {
> > + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> > +
> > +struct platform_driver mtk_mdp_rdma_driver = {
> > + .probe = mtk_mdp_rdma_probe,
> > + .remove = mtk_mdp_rdma_remove,
> > + .driver = {
> > + .name = "mediatek-mdp-rdma",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> > + },
> > +};
> > +module_platform_driver(mtk_mdp_rdma_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..868e8ca40de3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + unsigned int pitch;
> > + unsigned int addr0;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + int fmt;
> > +};
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-25 1:48 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 1:48 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Wed, 2021-10-20 at 00:38 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> > the ovl_adaptor component.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305
> > ++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> > 4 files changed, 333 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index a38e88e82d12..6e604a933ed0 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index a33b13fe2b6e..b3a372cab0bd 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -8,6 +8,7 @@
> >
> > #include <linux/soc/mediatek/mtk-cmdq.h>
> > #include "mtk_drm_plane.h"
> > +#include "mtk_mdp_rdma.h"
> >
> > int mtk_aal_clk_enable(struct device *dev);
> > void mtk_aal_clk_disable(struct device *dev);
> > @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_mdp_rdma_clk_enable(struct device *dev);
> > +void mtk_mdp_rdma_clk_disable(struct device *dev);
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt);
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..d05b1ef976bc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
OK.
>
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE BIT(0)
>
> Use one 'tab' to replace 8 space.
OK.
>
> > +#define MDP_RDMA_RESET 0x008
> > +#define MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B BIT(5)
> > +#define FLD_SIMPLE_MODE BIT(4)
> > +#define MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_COMMAND_DIV BIT(0)
> > +#define FLD_EXT_PREULTRA_EN BIT(3)
> > +#define FLD_RD_REQ_TYPE GENMASK(7,
> > 4)
> > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> > +#define FLD_ULTRA_EN GENMASK(13,
> > 12)
> > +#define VAL_ULTRA_EN_ENABLE 1
> > +#define FLD_PRE_ULTRA_EN GENMASK(17,
> > 16)
> > +#define VAL_PRE_ULTRA_EN_ENABLE 1
> > +#define FLD_EXT_ULTRA_EN BIT(18)
> > +#define MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB BIT(25)
> > +#define FLD_BIT_NUMBER GENMASK(19,
> > 18)
> > +#define FLD_SWAP BIT(14)
> > +#define FLD_UNIFORM_CONFIG BIT(17)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define FLD_SRC_FORMAT GENMASK(3,
> > 0)
> > +#define MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN BIT(22)
> > +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> > +#define FLD_UFBDC_EN BIT(12)
> > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB GENMASK(22,
> > 0)
> > +#define MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H GENMASK(30,
> > 16)
> > +#define FLD_MF_SRC_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H GENMASK(30,
> > 16)
> > +#define FLD_MF_CLIP_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 GENMASK(31,
> > 0)
> > +#define MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL GENMASK(27,
> > 23)
> > +#define FLD_TRANS_EN BIT(16)
> > +#define MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 GENMASK(31,
> > 0)
> > +
> > +#define RDMA_CSC_FULL709_TO_RGB 5
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +struct mtk_mdp_rdma {
> > + void __iomem *regs;
> > + struct clk *clk;
> > + struct cmdq_client_reg cmdq_reg;
>
> Align indent of members.
OK.
>
> > +};
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct
> > cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN |
> > VAL_PRE_ULTRA_EN_ENABLE << 16 |
> > + VAL_ULTRA_EN_ENABLE << 12 |
> > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_GMCIF_CON,
> > FLD_EXT_ULTRA_EN |
> > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN |
> > FLD_RD_REQ_TYPE |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> > +}
> > +
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv-
> > >cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > +}
> > +
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > +}
> > +
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(cfg->fmt);
> > + bool csc_enable = fmt_info->is_yuv ? true : false;
> > + unsigned int src_pitch_y = cfg->pitch;
> > + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> > + unsigned int offset_y = 0;
> > +
> > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_SWAP |
> > FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> > +
> > + if (!csc_enable && fmt_info->has_alpha)
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > FLD_MF_BKGD_WB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs, MDP_RDMA_COMP_CON,
> > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN |
> > FLD_AFBC_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_OUTPUT_10B);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23,
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0,
> > FLD_INT_MATRIX_SEL);
>
> In mtk_plane_update_new_state(), new_state->color_encoding has the
> information that non-RBG color is BT601, BT709, or BT2020.
>
OK, I will add color encoding info for color space convert.
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top *
> > src_pitch_y;
>
> Drop bpp_y, and
>
> offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top *
> src_pitch_y;
>
OK.
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_OFFSET_0,
> > FLD_SRC_OFFSET_0);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
>
> If x_left > 0, CLIP_W could still be set to width?
>
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
>
> If y_top > 0, CLIP_H could still be set to height?
>
The parameters (x_left, y_top, width, height) in mtk_mdp_rdma_cfg
struct means: rdma read data from frame buffer base addr offset
(x_left, y_top) with size (width, height). The parameters (width,
height) is not the source image size but the real size that RDMA want
to read.
> > +}
> > +
> > +int mtk_mdp_rdma_clk_enable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + pm_runtime_get_sync(dev);
>
> Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
OK, I will move the pm runtime control to ovl_adaptor.
>
> > + clk_prepare_enable(rdma->clk);
> > + return 0;
> > +}
> > +
> > +void mtk_mdp_rdma_clk_disable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + clk_disable_unprepare(rdma->clk);
> > + pm_runtime_put(dev);
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
Regards,
Nancy
> > +}
> > +
> > +static int mtk_mdp_rdma_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_mdp_rdma_component_ops = {
> > + .bind = mtk_mdp_rdma_bind,
> > + .unbind = mtk_mdp_rdma_unbind,
> > +};
> > +
> > +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + struct mtk_mdp_rdma *priv;
> > + int ret = 0;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap rdma\n");
> > + return PTR_ERR(priv->regs);
> > + }
> > +
> > + priv->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(priv->clk)) {
> > + dev_err(dev, "failed to get rdma clk\n");
> > + return PTR_ERR(priv->clk);
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + platform_set_drvdata(pdev, priv);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > + return ret;
> > +}
> > +
> > +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] =
> > {
> > + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> > +
> > +struct platform_driver mtk_mdp_rdma_driver = {
> > + .probe = mtk_mdp_rdma_probe,
> > + .remove = mtk_mdp_rdma_remove,
> > + .driver = {
> > + .name = "mediatek-mdp-rdma",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> > + },
> > +};
> > +module_platform_driver(mtk_mdp_rdma_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..868e8ca40de3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + unsigned int pitch;
> > + unsigned int addr0;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + int fmt;
> > +};
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195
@ 2021-10-25 1:48 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 1:48 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Wed, 2021-10-20 at 00:38 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of
> > the ovl_adaptor component.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 +
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305
> > ++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++
> > 4 files changed, 333 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index a38e88e82d12..6e604a933ed0 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index a33b13fe2b6e..b3a372cab0bd 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -8,6 +8,7 @@
> >
> > #include <linux/soc/mediatek/mtk-cmdq.h>
> > #include "mtk_drm_plane.h"
> > +#include "mtk_mdp_rdma.h"
> >
> > int mtk_aal_clk_enable(struct device *dev);
> > void mtk_aal_clk_disable(struct device *dev);
> > @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_mdp_rdma_clk_enable(struct device *dev);
> > +void mtk_mdp_rdma_clk_disable(struct device *dev);
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt);
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > new file mode 100644
> > index 000000000000..d05b1ef976bc
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> > @@ -0,0 +1,305 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
OK.
>
> > +#include "mtk_mdp_rdma.h"
> > +
> > +#define MDP_RDMA_EN 0x000
> > +#define FLD_ROT_ENABLE BIT(0)
>
> Use one 'tab' to replace 8 space.
OK.
>
> > +#define MDP_RDMA_RESET 0x008
> > +#define MDP_RDMA_CON 0x020
> > +#define FLD_OUTPUT_10B BIT(5)
> > +#define FLD_SIMPLE_MODE BIT(4)
> > +#define MDP_RDMA_GMCIF_CON 0x028
> > +#define FLD_COMMAND_DIV BIT(0)
> > +#define FLD_EXT_PREULTRA_EN BIT(3)
> > +#define FLD_RD_REQ_TYPE GENMASK(7,
> > 4)
> > +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7
> > +#define FLD_ULTRA_EN GENMASK(13,
> > 12)
> > +#define VAL_ULTRA_EN_ENABLE 1
> > +#define FLD_PRE_ULTRA_EN GENMASK(17,
> > 16)
> > +#define VAL_PRE_ULTRA_EN_ENABLE 1
> > +#define FLD_EXT_ULTRA_EN BIT(18)
> > +#define MDP_RDMA_SRC_CON 0x030
> > +#define FLD_OUTPUT_ARGB BIT(25)
> > +#define FLD_BIT_NUMBER GENMASK(19,
> > 18)
> > +#define FLD_SWAP BIT(14)
> > +#define FLD_UNIFORM_CONFIG BIT(17)
> > +#define RDMA_INPUT_10BIT BIT(18)
> > +#define FLD_SRC_FORMAT GENMASK(3,
> > 0)
> > +#define MDP_RDMA_COMP_CON 0x038
> > +#define FLD_AFBC_EN BIT(22)
> > +#define FLD_AFBC_YUV_TRANSFORM BIT(21)
> > +#define FLD_UFBDC_EN BIT(12)
> > +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> > +#define FLD_MF_BKGD_WB GENMASK(22,
> > 0)
> > +#define MDP_RDMA_MF_SRC_SIZE 0x070
> > +#define FLD_MF_SRC_H GENMASK(30,
> > 16)
> > +#define FLD_MF_SRC_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> > +#define FLD_MF_CLIP_H GENMASK(30,
> > 16)
> > +#define FLD_MF_CLIP_W GENMASK(14,
> > 0)
> > +#define MDP_RDMA_SRC_OFFSET_0 0x118
> > +#define FLD_SRC_OFFSET_0 GENMASK(31,
> > 0)
> > +#define MDP_RDMA_TRANSFORM_0 0x200
> > +#define FLD_INT_MATRIX_SEL GENMASK(27,
> > 23)
> > +#define FLD_TRANS_EN BIT(16)
> > +#define MDP_RDMA_SRC_BASE_0 0xf00
> > +#define FLD_SRC_BASE_0 GENMASK(31,
> > 0)
> > +
> > +#define RDMA_CSC_FULL709_TO_RGB 5
> > +
> > +enum rdma_format {
> > + RDMA_INPUT_FORMAT_RGB565 = 0,
> > + RDMA_INPUT_FORMAT_RGB888 = 1,
> > + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> > + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> > + RDMA_INPUT_FORMAT_UYVY = 4,
> > + RDMA_INPUT_FORMAT_YUY2 = 5,
> > + RDMA_INPUT_FORMAT_Y8 = 7,
> > + RDMA_INPUT_FORMAT_YV12 = 8,
> > + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> > + RDMA_INPUT_FORMAT_NV12 = 12,
> > + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> > + RDMA_INPUT_FORMAT_Y410 = 14
> > +};
> > +
> > +struct mtk_mdp_rdma {
> > + void __iomem *regs;
> > + struct clk *clk;
> > + struct cmdq_client_reg cmdq_reg;
>
> Align indent of members.
OK.
>
> > +};
> > +
> > +static unsigned int rdma_fmt_convert(unsigned int fmt)
> > +{
> > + switch (fmt) {
> > + default:
> > + case DRM_FORMAT_RGB565:
> > + return RDMA_INPUT_FORMAT_RGB565;
> > + case DRM_FORMAT_BGR565:
> > + return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
> > + case DRM_FORMAT_RGB888:
> > + return RDMA_INPUT_FORMAT_RGB888;
> > + case DRM_FORMAT_BGR888:
> > + return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
> > + case DRM_FORMAT_RGBX8888:
> > + case DRM_FORMAT_RGBA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888;
> > + case DRM_FORMAT_BGRX8888:
> > + case DRM_FORMAT_BGRA8888:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
> > + case DRM_FORMAT_XRGB8888:
> > + case DRM_FORMAT_ARGB8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888;
> > + case DRM_FORMAT_XBGR8888:
> > + case DRM_FORMAT_ABGR8888:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
> > + case DRM_FORMAT_ABGR2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_ARGB2101010:
> > + return RDMA_INPUT_FORMAT_RGBA8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_RGBA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_BGRA1010102:
> > + return RDMA_INPUT_FORMAT_ARGB8888 |
> > RDMA_INPUT_10BIT;
> > + case DRM_FORMAT_UYVY:
> > + return RDMA_INPUT_FORMAT_UYVY;
> > + case DRM_FORMAT_YUYV:
> > + return RDMA_INPUT_FORMAT_YUY2;
> > + }
> > +}
> > +
> > +static void mtk_mdp_rdma_fifo_config(struct device *dev, struct
> > cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN |
> > VAL_PRE_ULTRA_EN_ENABLE << 16 |
> > + VAL_ULTRA_EN_ENABLE << 12 |
> > VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_GMCIF_CON,
> > FLD_EXT_ULTRA_EN |
> > + FLD_PRE_ULTRA_EN | FLD_ULTRA_EN |
> > FLD_RD_REQ_TYPE |
> > + FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
> > +}
> > +
> > +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv-
> > >cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > +}
> > +
> > +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_EN,
> > FLD_ROT_ENABLE);
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > MDP_RDMA_RESET);
> > +}
> > +
> > +void mtk_mdp_rdma_config(struct device *dev, struct
> > mtk_mdp_rdma_cfg *cfg,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(cfg->fmt);
> > + bool csc_enable = fmt_info->is_yuv ? true : false;
> > + unsigned int src_pitch_y = cfg->pitch;
> > + unsigned int bpp_y = fmt_info->cpp[0] * 8;
> > + unsigned int offset_y = 0;
> > +
> > + mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
> > + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_SRC_CON, FLD_SWAP |
> > FLD_SRC_FORMAT | FLD_BIT_NUMBER);
> > +
> > + if (!csc_enable && fmt_info->has_alpha)
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB,
> > &priv->cmdq_reg,
> > + priv->regs, MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > + else
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_CON,
> > FLD_OUTPUT_ARGB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> > FLD_MF_BKGD_WB);
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
> > >regs, MDP_RDMA_COMP_CON,
> > + FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN |
> > FLD_AFBC_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_OUTPUT_10B);
> > + mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_CON, FLD_SIMPLE_MODE);
> > + mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
> > + mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23,
> > &priv->cmdq_reg, priv->regs,
> > + MDP_RDMA_TRANSFORM_0,
> > FLD_INT_MATRIX_SEL);
>
> In mtk_plane_update_new_state(), new_state->color_encoding has the
> information that non-RBG color is BT601, BT709, or BT2020.
>
OK, I will add color encoding info for color space convert.
> > +
> > + offset_y = (cfg->x_left * bpp_y >> 3) + cfg->y_top *
> > src_pitch_y;
>
> Drop bpp_y, and
>
> offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top *
> src_pitch_y;
>
OK.
> > +
> > + mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_SRC_OFFSET_0,
> > FLD_SRC_OFFSET_0);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
> > priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
>
> If x_left > 0, CLIP_W could still be set to width?
>
> > + mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
> > >cmdq_reg, priv->regs,
> > + MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
>
> If y_top > 0, CLIP_H could still be set to height?
>
The parameters (x_left, y_top, width, height) in mtk_mdp_rdma_cfg
struct means: rdma read data from frame buffer base addr offset
(x_left, y_top) with size (width, height). The parameters (width,
height) is not the source image size but the real size that RDMA want
to read.
> > +}
> > +
> > +int mtk_mdp_rdma_clk_enable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + pm_runtime_get_sync(dev);
>
> Align with other sub driver, pm runtime control is in mtk_drm_crtc.c
OK, I will move the pm runtime control to ovl_adaptor.
>
> > + clk_prepare_enable(rdma->clk);
> > + return 0;
> > +}
> > +
> > +void mtk_mdp_rdma_clk_disable(struct device *dev)
> > +{
> > + struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
> > +
> > + clk_disable_unprepare(rdma->clk);
> > + pm_runtime_put(dev);
>
> Ditto.
>
> Regards,
> Chun-Kuang.
>
Regards,
Nancy
> > +}
> > +
> > +static int mtk_mdp_rdma_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_mdp_rdma_unbind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_mdp_rdma_component_ops = {
> > + .bind = mtk_mdp_rdma_bind,
> > + .unbind = mtk_mdp_rdma_unbind,
> > +};
> > +
> > +static int mtk_mdp_rdma_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + struct mtk_mdp_rdma *priv;
> > + int ret = 0;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap rdma\n");
> > + return PTR_ERR(priv->regs);
> > + }
> > +
> > + priv->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(priv->clk)) {
> > + dev_err(dev, "failed to get rdma clk\n");
> > + return PTR_ERR(priv->clk);
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + platform_set_drvdata(pdev, priv);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_mdp_rdma_component_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > + return ret;
> > +}
> > +
> > +static int mtk_mdp_rdma_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] =
> > {
> > + { .compatible = "mediatek,mt8195-vdo1-rdma", },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);
> > +
> > +struct platform_driver mtk_mdp_rdma_driver = {
> > + .probe = mtk_mdp_rdma_probe,
> > + .remove = mtk_mdp_rdma_remove,
> > + .driver = {
> > + .name = "mediatek-mdp-rdma",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_mdp_rdma_driver_dt_match,
> > + },
> > +};
> > +module_platform_driver(mtk_mdp_rdma_driver);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > new file mode 100644
> > index 000000000000..868e8ca40de3
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MDP_RDMA_H__
> > +#define __MTK_MDP_RDMA_H__
> > +
> > +struct mtk_mdp_rdma_cfg {
> > + unsigned int pitch;
> > + unsigned int addr0;
> > + unsigned int width;
> > + unsigned int height;
> > + unsigned int x_left;
> > + unsigned int y_top;
> > + int fmt;
> > +};
> > +
> > +#endif // __MTK_MDP_RDMA_H__
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
2021-10-21 15:02 ` Chun-Kuang Hu
(?)
@ 2021-10-25 2:10 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:10 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:02 +0800, Chun-Kuang Hu wrote:
> >
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add merge new API.
> > 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute
> > API.
> > 2. Add merge new advance config API. The original merge API is
> > mtk_ddp_comp_funcs function prototype. The API interface
> > parameters
> > cannot be modified, so add a new config API for extension.
> > 3. Add merge enable/disable API for cmdq support. The ovl_adaptor
> > merges
> > are configured with each drm plane update. Need to
> > enable/disable
> > merge with cmdq making sure all the settings taken effect in the
> > same vblank.
>
> Separate this patch into three patches.
>
OK.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86
> > ++++++++++++++++++++---
> > 2 files changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index b3a372cab0bd..2446ad0a4977 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev,
> > unsigned int width,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > void mtk_merge_start(struct device *dev);
> > void mtk_merge_stop(struct device *dev);
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> >
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > index b05e1df79c3d..696bb948352b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -17,6 +17,7 @@
> > #define DISP_REG_MERGE_CTRL 0x000
> > #define MERGE_EN 1
> > #define DISP_REG_MERGE_CFG_0 0x010
> > +#define DISP_REG_MERGE_CFG_1 0x014
> > #define DISP_REG_MERGE_CFG_4 0x020
> > #define DISP_REG_MERGE_CFG_10 0x038
> > /* no swap */
> > @@ -25,9 +26,12 @@
> > #define DISP_REG_MERGE_CFG_12 0x040
> > #define CFG_10_10_1PI_2PO_BUF_MODE 6
> > #define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define CFG_11_10_1PI_2PO_MERGE 18
> > #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> > #define DISP_REG_MERGE_CFG_24 0x070
> > #define DISP_REG_MERGE_CFG_25 0x074
> > +#define DISP_REG_MERGE_CFG_26 0x078
> > +#define DISP_REG_MERGE_CFG_27 0x07c
> > #define DISP_REG_MERGE_CFG_36 0x0a0
> > #define ULTRA_EN BIT(0)
> > #define PREULTRA_EN BIT(4)
> > @@ -54,26 +58,52 @@
> > #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> > #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
> >
> > +#define DISP_REG_MERGE_MUTE_0 0xf00
> > +
> > struct mtk_disp_merge {
> > void __iomem *regs;
> > struct clk *clk;
> > struct clk *async_clk;
> > struct cmdq_client_reg cmdq_reg;
> > bool fifo_en;
> > + bool mute_support;
>
> Align indent of members.
>
OK.
> > };
> >
> > void mtk_merge_start(struct device *dev)
> > +{
> > + mtk_merge_enable(dev, NULL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_merge_disable(dev, NULL);
> > }
> >
> > -void mtk_merge_stop(struct device *dev)
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
> support, but the naming make them so different. So I would like this
> function name to be mtk_merge_start_cmdq().
>
OK.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> Ditto.
OK.
>
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> I'm not sure whether it's worth to have this function. It seems that
> mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
> this function into mtk_merge_enable().
> And I would like to mute in mtk_merge_disable() to let register be
> restored.
>
> Regards,
> Chun-Kuang.
>
OK. I will remove the unmute API, and move unmute function into merge
start/stop.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->mute_support)
> > + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_REG_MERGE_MUTE_0);
> > }
> >
> > static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct
> > mtk_disp_merge *priv,
> > void mtk_merge_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc,
> > cmdq_pkt);
> > +}
> > +
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> >
> > - if (!h || !w) {
> > - dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > + if (!h || !l_w) {
> > + dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, l_w, h);
> > return;
> > }
> >
> > @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev,
> > unsigned int w,
> > mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > }
> >
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + if (r_w)
> > + mode = CFG_11_10_1PI_2PO_MERGE;
> > +
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_0);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv-
> > >cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_4);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + /*
> > + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> > + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> > + * If r_w > 0, the merge is in merge mode (input0 and
> > input1 merge together),
> > + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> > + * If r_w = 0, the merge is in buffer mode, the input goes
> > through SRAM0 and
> > + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same
> > size.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_24);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > - DISP_REG_MERGE_CFG_25);
> > + if (r_w)
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > + else
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > +
> > + /*
> > + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only
> > used in LR merge.
> > + * Only take effect when the merge is setting to merge
> > mode.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_27);
> > +
> > mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv-
> > >regs,
> > @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct
> > platform_device *pdev)
> > priv->fifo_en = of_property_read_bool(dev->of_node,
> > "mediatek,merge-fifo-
> > en");
> >
> > + priv->mute_support = of_property_read_bool(dev->of_node,
> > + "mediatek,merge-
> > mute");
> > platform_set_drvdata(pdev, priv);
> >
> > ret = component_add(dev, &mtk_disp_merge_component_ops);
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-25 2:10 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:10 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:02 +0800, Chun-Kuang Hu wrote:
> >
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add merge new API.
> > 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute
> > API.
> > 2. Add merge new advance config API. The original merge API is
> > mtk_ddp_comp_funcs function prototype. The API interface
> > parameters
> > cannot be modified, so add a new config API for extension.
> > 3. Add merge enable/disable API for cmdq support. The ovl_adaptor
> > merges
> > are configured with each drm plane update. Need to
> > enable/disable
> > merge with cmdq making sure all the settings taken effect in the
> > same vblank.
>
> Separate this patch into three patches.
>
OK.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86
> > ++++++++++++++++++++---
> > 2 files changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index b3a372cab0bd..2446ad0a4977 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev,
> > unsigned int width,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > void mtk_merge_start(struct device *dev);
> > void mtk_merge_stop(struct device *dev);
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> >
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > index b05e1df79c3d..696bb948352b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -17,6 +17,7 @@
> > #define DISP_REG_MERGE_CTRL 0x000
> > #define MERGE_EN 1
> > #define DISP_REG_MERGE_CFG_0 0x010
> > +#define DISP_REG_MERGE_CFG_1 0x014
> > #define DISP_REG_MERGE_CFG_4 0x020
> > #define DISP_REG_MERGE_CFG_10 0x038
> > /* no swap */
> > @@ -25,9 +26,12 @@
> > #define DISP_REG_MERGE_CFG_12 0x040
> > #define CFG_10_10_1PI_2PO_BUF_MODE 6
> > #define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define CFG_11_10_1PI_2PO_MERGE 18
> > #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> > #define DISP_REG_MERGE_CFG_24 0x070
> > #define DISP_REG_MERGE_CFG_25 0x074
> > +#define DISP_REG_MERGE_CFG_26 0x078
> > +#define DISP_REG_MERGE_CFG_27 0x07c
> > #define DISP_REG_MERGE_CFG_36 0x0a0
> > #define ULTRA_EN BIT(0)
> > #define PREULTRA_EN BIT(4)
> > @@ -54,26 +58,52 @@
> > #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> > #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
> >
> > +#define DISP_REG_MERGE_MUTE_0 0xf00
> > +
> > struct mtk_disp_merge {
> > void __iomem *regs;
> > struct clk *clk;
> > struct clk *async_clk;
> > struct cmdq_client_reg cmdq_reg;
> > bool fifo_en;
> > + bool mute_support;
>
> Align indent of members.
>
OK.
> > };
> >
> > void mtk_merge_start(struct device *dev)
> > +{
> > + mtk_merge_enable(dev, NULL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_merge_disable(dev, NULL);
> > }
> >
> > -void mtk_merge_stop(struct device *dev)
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
> support, but the naming make them so different. So I would like this
> function name to be mtk_merge_start_cmdq().
>
OK.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> Ditto.
OK.
>
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> I'm not sure whether it's worth to have this function. It seems that
> mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
> this function into mtk_merge_enable().
> And I would like to mute in mtk_merge_disable() to let register be
> restored.
>
> Regards,
> Chun-Kuang.
>
OK. I will remove the unmute API, and move unmute function into merge
start/stop.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->mute_support)
> > + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_REG_MERGE_MUTE_0);
> > }
> >
> > static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct
> > mtk_disp_merge *priv,
> > void mtk_merge_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc,
> > cmdq_pkt);
> > +}
> > +
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> >
> > - if (!h || !w) {
> > - dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > + if (!h || !l_w) {
> > + dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, l_w, h);
> > return;
> > }
> >
> > @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev,
> > unsigned int w,
> > mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > }
> >
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + if (r_w)
> > + mode = CFG_11_10_1PI_2PO_MERGE;
> > +
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_0);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv-
> > >cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_4);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + /*
> > + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> > + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> > + * If r_w > 0, the merge is in merge mode (input0 and
> > input1 merge together),
> > + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> > + * If r_w = 0, the merge is in buffer mode, the input goes
> > through SRAM0 and
> > + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same
> > size.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_24);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > - DISP_REG_MERGE_CFG_25);
> > + if (r_w)
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > + else
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > +
> > + /*
> > + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only
> > used in LR merge.
> > + * Only take effect when the merge is setting to merge
> > mode.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_27);
> > +
> > mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv-
> > >regs,
> > @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct
> > platform_device *pdev)
> > priv->fifo_en = of_property_read_bool(dev->of_node,
> > "mediatek,merge-fifo-
> > en");
> >
> > + priv->mute_support = of_property_read_bool(dev->of_node,
> > + "mediatek,merge-
> > mute");
> > platform_set_drvdata(pdev, priv);
> >
> > ret = component_add(dev, &mtk_disp_merge_component_ops);
> > --
> > 2.18.0
> >
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
@ 2021-10-25 2:10 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:10 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:02 +0800, Chun-Kuang Hu wrote:
> >
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add merge new API.
> > 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute
> > API.
> > 2. Add merge new advance config API. The original merge API is
> > mtk_ddp_comp_funcs function prototype. The API interface
> > parameters
> > cannot be modified, so add a new config API for extension.
> > 3. Add merge enable/disable API for cmdq support. The ovl_adaptor
> > merges
> > are configured with each drm plane update. Need to
> > enable/disable
> > merge with cmdq making sure all the settings taken effect in the
> > same vblank.
>
> Separate this patch into three patches.
>
OK.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86
> > ++++++++++++++++++++---
> > 2 files changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index b3a372cab0bd..2446ad0a4977 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev,
> > unsigned int width,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > void mtk_merge_start(struct device *dev);
> > void mtk_merge_stop(struct device *dev);
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> >
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > index b05e1df79c3d..696bb948352b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -17,6 +17,7 @@
> > #define DISP_REG_MERGE_CTRL 0x000
> > #define MERGE_EN 1
> > #define DISP_REG_MERGE_CFG_0 0x010
> > +#define DISP_REG_MERGE_CFG_1 0x014
> > #define DISP_REG_MERGE_CFG_4 0x020
> > #define DISP_REG_MERGE_CFG_10 0x038
> > /* no swap */
> > @@ -25,9 +26,12 @@
> > #define DISP_REG_MERGE_CFG_12 0x040
> > #define CFG_10_10_1PI_2PO_BUF_MODE 6
> > #define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define CFG_11_10_1PI_2PO_MERGE 18
> > #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> > #define DISP_REG_MERGE_CFG_24 0x070
> > #define DISP_REG_MERGE_CFG_25 0x074
> > +#define DISP_REG_MERGE_CFG_26 0x078
> > +#define DISP_REG_MERGE_CFG_27 0x07c
> > #define DISP_REG_MERGE_CFG_36 0x0a0
> > #define ULTRA_EN BIT(0)
> > #define PREULTRA_EN BIT(4)
> > @@ -54,26 +58,52 @@
> > #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> > #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
> >
> > +#define DISP_REG_MERGE_MUTE_0 0xf00
> > +
> > struct mtk_disp_merge {
> > void __iomem *regs;
> > struct clk *clk;
> > struct clk *async_clk;
> > struct cmdq_client_reg cmdq_reg;
> > bool fifo_en;
> > + bool mute_support;
>
> Align indent of members.
>
OK.
> > };
> >
> > void mtk_merge_start(struct device *dev)
> > +{
> > + mtk_merge_enable(dev, NULL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_merge_disable(dev, NULL);
> > }
> >
> > -void mtk_merge_stop(struct device *dev)
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
> support, but the naming make them so different. So I would like this
> function name to be mtk_merge_start_cmdq().
>
OK.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> Ditto.
OK.
>
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> I'm not sure whether it's worth to have this function. It seems that
> mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
> this function into mtk_merge_enable().
> And I would like to mute in mtk_merge_disable() to let register be
> restored.
>
> Regards,
> Chun-Kuang.
>
OK. I will remove the unmute API, and move unmute function into merge
start/stop.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->mute_support)
> > + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_REG_MERGE_MUTE_0);
> > }
> >
> > static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct
> > mtk_disp_merge *priv,
> > void mtk_merge_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc,
> > cmdq_pkt);
> > +}
> > +
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> >
> > - if (!h || !w) {
> > - dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > + if (!h || !l_w) {
> > + dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, l_w, h);
> > return;
> > }
> >
> > @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev,
> > unsigned int w,
> > mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > }
> >
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + if (r_w)
> > + mode = CFG_11_10_1PI_2PO_MERGE;
> > +
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_0);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv-
> > >cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_4);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + /*
> > + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> > + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> > + * If r_w > 0, the merge is in merge mode (input0 and
> > input1 merge together),
> > + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> > + * If r_w = 0, the merge is in buffer mode, the input goes
> > through SRAM0 and
> > + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same
> > size.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_24);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > - DISP_REG_MERGE_CFG_25);
> > + if (r_w)
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > + else
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > +
> > + /*
> > + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only
> > used in LR merge.
> > + * Only take effect when the merge is setting to merge
> > mode.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_27);
> > +
> > mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv-
> > >regs,
> > @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct
> > platform_device *pdev)
> > priv->fifo_en = of_property_read_bool(dev->of_node,
> > "mediatek,merge-fifo-
> > en");
> >
> > + priv->mute_support = of_property_read_bool(dev->of_node,
> > + "mediatek,merge-
> > mute");
> > platform_set_drvdata(pdev, priv);
> >
> > ret = component_add(dev, &mtk_disp_merge_component_ops);
> > --
> > 2.18.0
> >
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
2021-10-21 15:44 ` Chun-Kuang Hu
(?)
@ 2021-10-25 2:24 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:24 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:44 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
> >
> > ETHDR is a part of ovl_adaptor.
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combine
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 403
> > +++++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> > 3 files changed, 429 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 6e604a933ed0..fb158a1e7f06 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > + mtk_ethdr.o \
> > mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..99e5a95aebed
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,403 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
>
> Align the indent with mdp rdma driver.
>
OK.
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define MIXER_INx_MODE_BYPASS 0
>
> MIXER_INX_MODE_BYPASS
>
OK.
> > +#define MIXER_INx_MODE_EVEN_EXTEND 1
> > +#define MIXER_INx_MODE_ODD_EXTEND 2
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *mmsys_dev;
> > + spinlock_t lock; /* protects vblank_cb and vblank_cb_data
> > */
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > + unsigned long flags;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + if (!priv->vblank_cb) {
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > + return IRQ_NONE;
> > + }
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int offset = (pending->x & 1) << 31 | pending->y
> > << 16 | pending->x;
> > + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
>
> fmt is useless, so remove.
>
OK.
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1,
> > MIXER_INx_MODE_BYPASS, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, 0, cmdq_pkt);
> > + return;
> > + }
> > +
> > + if (pending->x % 2)
> > + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1, mixer_pad_mode, cmdq_pkt);
>
> Drop mixer_pad_mode, and
>
> mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx
> + 1,
> pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
> MIXER_INx_MODE_BYPASS,
> cmdq_pkt);
>
OK.
> Regards,
> Chun-Kuang.
Regards,
Nancy
>
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, pending->width / 2 - 1,
> > cmdq_pkt);
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending-
> > >width, &mixer->cmdq_base,
> > + mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-25 2:24 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:24 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:44 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
> >
> > ETHDR is a part of ovl_adaptor.
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combine
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 403
> > +++++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> > 3 files changed, 429 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 6e604a933ed0..fb158a1e7f06 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > + mtk_ethdr.o \
> > mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..99e5a95aebed
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,403 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
>
> Align the indent with mdp rdma driver.
>
OK.
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define MIXER_INx_MODE_BYPASS 0
>
> MIXER_INX_MODE_BYPASS
>
OK.
> > +#define MIXER_INx_MODE_EVEN_EXTEND 1
> > +#define MIXER_INx_MODE_ODD_EXTEND 2
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *mmsys_dev;
> > + spinlock_t lock; /* protects vblank_cb and vblank_cb_data
> > */
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > + unsigned long flags;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + if (!priv->vblank_cb) {
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > + return IRQ_NONE;
> > + }
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int offset = (pending->x & 1) << 31 | pending->y
> > << 16 | pending->x;
> > + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
>
> fmt is useless, so remove.
>
OK.
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1,
> > MIXER_INx_MODE_BYPASS, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, 0, cmdq_pkt);
> > + return;
> > + }
> > +
> > + if (pending->x % 2)
> > + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1, mixer_pad_mode, cmdq_pkt);
>
> Drop mixer_pad_mode, and
>
> mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx
> + 1,
> pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
> MIXER_INx_MODE_BYPASS,
> cmdq_pkt);
>
OK.
> Regards,
> Chun-Kuang.
Regards,
Nancy
>
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, pending->width / 2 - 1,
> > cmdq_pkt);
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending-
> > >width, &mixer->cmdq_base,
> > + mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 13/16] drm/mediatek: add ETHDR support for MT8195
@ 2021-10-25 2:24 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:24 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:44 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:22寫道：
> >
> > ETHDR is a part of ovl_adaptor.
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combine
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 403
> > +++++++++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++
> > 3 files changed, 429 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 6e604a933ed0..fb158a1e7f06 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > mtk_dpi.o \
> > + mtk_ethdr.o \
> > mtk_mdp_rdma.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..99e5a95aebed
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,403 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/reset.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_INTEN 0x4
> > + #define MIX_FME_CPL_INTEN BIT(1)
>
> Align the indent with mdp rdma driver.
>
OK.
> > +#define MIX_INTSTA 0x8
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > + #define OUTPUT_NO_RND BIT(3)
> > + #define SOURCE_RGB_SEL BIT(7)
> > + #define BACKGROUND_RELAY (4 << 9)
> > +#define MIX_ROI_BGCLR 0x20
> > + #define BGCLR_BLACK 0xff000000
> > +#define MIX_SRC_CON 0x24
> > + #define MIX_SRC_L0_EN BIT(0)
> > +#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> > + #define NON_PREMULTI_SOURCE (2 << 12)
> > +#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> > +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > + #define MIX_FUNC_DCM_ENABLE 0xffffffff
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > + #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > + #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > + #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
> > +
> > +#define MIXER_INx_MODE_BYPASS 0
>
> MIXER_INX_MODE_BYPASS
>
OK.
> > +#define MIXER_INx_MODE_EVEN_EXTEND 1
> > +#define MIXER_INx_MODE_ODD_EXTEND 2
> > +#define DEFAULT_9BIT_ALPHA 0x100
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > + struct device *mmsys_dev;
> > + spinlock_t lock; /* protects vblank_cb and vblank_cb_data
> > */
> > + void (*vblank_cb)(void *data);
> > + void *vblank_cb_data;
> > + int irq;
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +void mtk_ethdr_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = vblank_cb;
> > + priv->vblank_cb_data = vblank_cb_data;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(MIX_FME_CPL_INTEN, priv-
> > >ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
> > +}
> > +
> > +void mtk_ethdr_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + priv->vblank_cb = NULL;
> > + priv->vblank_cb_data = NULL;
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTEN);
> > +}
> > +
> > +static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
> > +{
> > + struct mtk_ethdr *priv = dev_id;
> > + unsigned long flags;
> > +
> > + writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
> > MIX_INTSTA);
> > +
> > + spin_lock_irqsave(&priv->lock, flags);
> > + if (!priv->vblank_cb) {
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > + return IRQ_NONE;
> > + }
> > +
> > + priv->vblank_cb(priv->vblank_cb_data);
> > + spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int offset = (pending->x & 1) << 31 | pending->y
> > << 16 | pending->x;
> > + unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
>
> fmt is useless, so remove.
>
OK.
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx >= 4)
> > + return;
> > +
> > + if (!pending->enable) {
> > + mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1,
> > MIXER_INx_MODE_BYPASS, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, 0, cmdq_pkt);
> > + return;
> > + }
> > +
> > + if (pending->x % 2)
> > + mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
> > +
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_MODE,
> > + idx + 1, mixer_pad_mode, cmdq_pkt);
>
> Drop mixer_pad_mode, and
>
> mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx
> + 1,
> pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :
> MIXER_INx_MODE_BYPASS,
> cmdq_pkt);
>
OK.
> Regards,
> Chun-Kuang.
Regards,
Nancy
>
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_BIWIDTH,
> > + idx + 1, pending->width / 2 - 1,
> > cmdq_pkt);
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 0, cmdq_pkt);
> > + } else {
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_HDR_ALPHA_SEL,
> > + idx + 1, 1, cmdq_pkt);
> > + }
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > + mtk_mmsys_ddp_config(priv->mmsys_dev,
> > MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,
> > + DEFAULT_9BIT_ALPHA, cmdq_pkt);
> > +
> > + mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending-
> > >width, &mixer->cmdq_base,
> > + mixer->regs, MIX_L_SRC_SIZE(idx));
> > + mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
> > >regs, MIX_L_SRC_OFFSET(idx));
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> > mixer->regs, MIX_L_SRC_CON(idx),
> > + 0x1ff);
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > + BIT(idx));
> > +}
> > +
_______________________________________________
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
2021-10-15 7:49 ` AngeloGioacchino Del Regno
(?)
@ 2021-10-25 2:42 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Fri, 2021-10-15 at 09:49 +0200, AngeloGioacchino Del Regno wrote:
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
>
> nit: can you please fix the indentation here?
>
OK, I will fix it.
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx];
> > + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2) %
> > 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0,
> > 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type type)
> > +{
> > + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type,
> > alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
>
> This looks like being a debugging print, use dev_dbg please.
>
OK.
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
>
> ...and this is another debugging print, imo.
OK.
>
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
>
> Printing the line number here isn't giving any valuable information,
> as this
> function is almost a one-liner... plus, this is a debug print and, as
> such,
> you should either use dev_dbg instead or simply remove it: if
> anything needs
> debugging of this part, you'll probably want to use ftrace anyway, so
> I don't
> really see the need of having this print in place.
>
OK.
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node->parent,
> > node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
>
> If you want to know when you're hitting a function, you should use
> ftrace
> instead of a print. Please remove this message.
>
OK.
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
>
> Also remove this one.
>
OK.
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
>
> Please fix indentation:
> .driver = {
> .......
> },
>
OK.
> Regards,
> - Angelo
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-25 2:42 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Fri, 2021-10-15 at 09:49 +0200, AngeloGioacchino Del Regno wrote:
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
>
> nit: can you please fix the indentation here?
>
OK, I will fix it.
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx];
> > + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2) %
> > 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0,
> > 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type type)
> > +{
> > + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type,
> > alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
>
> This looks like being a debugging print, use dev_dbg please.
>
OK.
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
>
> ...and this is another debugging print, imo.
OK.
>
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
>
> Printing the line number here isn't giving any valuable information,
> as this
> function is almost a one-liner... plus, this is a debug print and, as
> such,
> you should either use dev_dbg instead or simply remove it: if
> anything needs
> debugging of this part, you'll probably want to use ftrace anyway, so
> I don't
> really see the need of having this print in place.
>
OK.
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node->parent,
> > node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
>
> If you want to know when you're hitting a function, you should use
> ftrace
> instead of a print. Please remove this message.
>
OK.
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
>
> Also remove this one.
>
OK.
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
>
> Please fix indentation:
> .driver = {
> .......
> },
>
OK.
> Regards,
> - Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-25 2:42 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-25 2:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi Angelo,
Thanks for the review.
On Fri, 2021-10-15 at 09:49 +0200, AngeloGioacchino Del Regno wrote:
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644
> > drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
>
> nit: can you please fix the indentation here?
>
OK, I will fix it.
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx];
> > + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 +
> > 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2) %
> > 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0,
> > 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type type)
> > +{
> > + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type,
> > alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
>
> This looks like being a debugging print, use dev_dbg please.
>
OK.
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device of
> > node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
>
> ...and this is another debugging print, imo.
OK.
>
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
>
> Printing the line number here isn't giving any valuable information,
> as this
> function is almost a one-liner... plus, this is a debug print and, as
> such,
> you should either use dev_dbg instead or simply remove it: if
> anything needs
> debugging of this part, you'll probably want to use ftrace anyway, so
> I don't
> really see the need of having this print in place.
>
OK.
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node->parent,
> > node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
>
> If you want to know when you're hitting a function, you should use
> ftrace
> instead of a print. Please remove this message.
>
OK.
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
>
> Also remove this one.
>
OK.
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
>
> Please fix indentation:
> .driver = {
> .......
> },
>
OK.
> Regards,
> - Angelo
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
2021-10-04 6:21 ` Nancy.Lin
(?)
@ 2021-10-25 23:11 ` Chun-Kuang Hu
-1 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-25 23:11 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
pending->width is passed from caller function, the caller function
does not expect that pending->width is modified by callee function.
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
This is neither l_w nor r_w, why?
For example, if pending->width is 1922, l_w is 962, r_w is 960, and
MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
Does DRM framework not disable all layer before disable crtc? These
codes looks asymetric.
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
In clk_err, you count i to zero, so
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
Drop ovl_adaptor_comp_str[] and print i instead of
ovl_adaptor_comp_str[i]. We could know what the i mean in driver code.
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
This function looks like ovl_adaptor_comp_init(), I think things could
be done once.
Regards,
Chun-Kuang.
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..1ad9f7edfcc7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-25 23:11 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-25 23:11 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
pending->width is passed from caller function, the caller function
does not expect that pending->width is modified by callee function.
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
This is neither l_w nor r_w, why?
For example, if pending->width is 1922, l_w is 962, r_w is 960, and
MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
Does DRM framework not disable all layer before disable crtc? These
codes looks asymetric.
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
In clk_err, you count i to zero, so
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
Drop ovl_adaptor_comp_str[] and print i instead of
ovl_adaptor_comp_str[i]. We could know what the i mean in driver code.
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
This function looks like ovl_adaptor_comp_init(), I think things could
be done once.
Regards,
Chun-Kuang.
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..1ad9f7edfcc7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-25 23:11 ` Chun-Kuang Hu
0 siblings, 0 replies; 111+ messages in thread
From: Chun-Kuang Hu @ 2021-10-25 23:11 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
>
> Add ovl_adaptor driver for MT8195.
> Ovl_adaptor is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> an ETHDR. Two RDMAs merge into one layer, so this module support 4
> layers.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 4 files changed, 516 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fb158a1e7f06..3abd27d7c91d 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_gamma.o \
> mtk_disp_merge.o \
> mtk_disp_ovl.o \
> + mtk_disp_ovl_adaptor.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 2446ad0a4977..6a4f4c42aedb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> + void (*vblank_cb)(void *),
> + void *vblank_cb_data);
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> +void mtk_ovl_adaptor_start(struct device *dev);
> +void mtk_ovl_adaptor_stop(struct device *dev);
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> +
> int mtk_mdp_rdma_clk_enable(struct device *dev);
> void mtk_mdp_rdma_clk_disable(struct device *dev);
> void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> new file mode 100644
> index 000000000000..bfb5a9d29c26
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_disp_drv.h"
Alphabetic order.
> +#include "mtk_ethdr.h"
> +
> +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> +
> +enum mtk_ovl_adaptor_comp_type {
> + OVL_ADAPTOR_TYPE_RDMA = 0,
> + OVL_ADAPTOR_TYPE_MERGE,
> + OVL_ADAPTOR_TYPE_ETHDR,
> + OVL_ADAPTOR_TYPE_NUM,
> +};
> +
> +enum mtk_ovl_adaptor_comp_id {
> + OVL_ADAPTOR_MDP_RDMA0,
> + OVL_ADAPTOR_MDP_RDMA1,
> + OVL_ADAPTOR_MDP_RDMA2,
> + OVL_ADAPTOR_MDP_RDMA3,
> + OVL_ADAPTOR_MDP_RDMA4,
> + OVL_ADAPTOR_MDP_RDMA5,
> + OVL_ADAPTOR_MDP_RDMA6,
> + OVL_ADAPTOR_MDP_RDMA7,
> + OVL_ADAPTOR_MERGE0,
> + OVL_ADAPTOR_MERGE1,
> + OVL_ADAPTOR_MERGE2,
> + OVL_ADAPTOR_MERGE3,
> + OVL_ADAPTOR_ETHDR0,
> + OVL_ADAPTOR_ID_MAX
> +};
> +
> +struct ovl_adaptor_comp_match {
> + enum mtk_ovl_adaptor_comp_type type;
> + int alias_id;
> +};
> +
> +struct mtk_disp_ovl_adaptor {
> + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> + struct device *mmsys_dev;
> +};
> +
> +static const char * const ovl_adaptor_comp_str[] = {
> + "OVL_ADAPTOR_MDP_RDMA0",
> + "OVL_ADAPTOR_MDP_RDMA1",
> + "OVL_ADAPTOR_MDP_RDMA2",
> + "OVL_ADAPTOR_MDP_RDMA3",
> + "OVL_ADAPTOR_MDP_RDMA4",
> + "OVL_ADAPTOR_MDP_RDMA5",
> + "OVL_ADAPTOR_MDP_RDMA6",
> + "OVL_ADAPTOR_MDP_RDMA7",
> + "OVL_ADAPTOR_MERGE0",
> + "OVL_ADAPTOR_MERGE1",
> + "OVL_ADAPTOR_MERGE2",
> + "OVL_ADAPTOR_MERGE3",
> + "OVL_ADAPTOR_ETHDR",
> + "OVL_ADAPTOR_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
> + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> +};
> +
> +static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
> + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
> + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
> + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
> + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
> + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
> + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
> + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
> + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
> + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> +};
> +
> +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + struct device *ethdr;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> + unsigned int l_w = 0;
> + unsigned int r_w = 0;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
> + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> +
> + if (!pending->enable) {
> + mtk_merge_disable(merge, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> + return;
> + }
> +
> + /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
> + pending->width = ALIGN_DOWN(pending->width, 2);
pending->width is passed from caller function, the caller function
does not expect that pending->width is modified by callee function.
> +
> + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + if (use_dual_pipe) {
> + l_w = (pending->width / 2) + ((pending->width / 2) % 2);
> + r_w = pending->width - l_w;
> + } else {
> + l_w = pending->width;
> + }
> + mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> + idx, pending->width / 2, cmdq_pkt);
This is neither l_w nor r_w, why?
For example, if pending->width is 1922, l_w is 962, r_w is 960, and
MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
> + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> + idx, pending->height, cmdq_pkt);
> +
> + rdma_config.width = l_w;
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.pitch = pending->pitch;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> +
> + if (use_dual_pipe) {
> + rdma_config.x_left = l_w;
> + rdma_config.width = r_w;
> + mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
> + }
> +
> + mtk_merge_enable(merge, cmdq_pkt);
> + mtk_merge_unmute(merge, cmdq_pkt);
> +
> + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> + else
> + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> +
> + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> + vrefresh, bpc, cmdq_pkt);
> +}
> +
> +void mtk_ovl_adaptor_start(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +void mtk_ovl_adaptor_stop(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *rdma_l;
> + struct device *rdma_r;
> + struct device *merge;
> + u32 i;
> +
> + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> + rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> + rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> +
> + mtk_mdp_rdma_stop(rdma_l, NULL);
> + mtk_mdp_rdma_stop(rdma_r, NULL);
> + mtk_merge_stop(merge);
Does DRM framework not disable all layer before disable crtc? These
codes looks asymetric.
> + }
> +
> + mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int ret;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
In clk_err, you count i to zero, so
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + ret = mtk_mdp_rdma_clk_enable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + ret = mtk_merge_clk_enable(comp);
> + else
> + ret = mtk_ethdr_clk_enable(comp);
> + if (ret) {
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, ovl_adaptor_comp_str[i]);
Drop ovl_adaptor_comp_str[] and print i instead of
ovl_adaptor_comp_str[i]. We could know what the i mean in driver code.
> + goto clk_err;
> + }
> + }
> +
> + return ret;
> +
> +clk_err:
> + while (--i >= 0) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> + return ret;
> +}
> +
> +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> + struct device *comp;
> + int i;
> +
> + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
> + comp = ovl_adaptor->ovl_adaptor_comp[i];
> +
> + if (i < OVL_ADAPTOR_MERGE0)
> + mtk_mdp_rdma_clk_disable(comp);
> + else if (i < OVL_ADAPTOR_ETHDR0)
> + mtk_merge_clk_disable(comp);
> + else
> + mtk_ethdr_clk_disable(comp);
> + }
> +}
> +
> +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> +{
> + return MTK_OVL_ADAPTOR_LAYER_NUM;
> +}
> +
> +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),
> + void *vblank_cb_data)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> + vblank_cb, vblank_cb_data);
> +}
> +
> +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
> +
> + mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> +}
> +
> +static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_ovl_adaptor_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> + }, {
> + .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> + },
> + {},
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + struct platform_device *comp_pdev;
> + int i, ret;
> +
> + parent = dev->parent->parent->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> +
> + drm_of_component_match_add(dev, match, compare_of, node);
> + dev_info(dev, "Adding component match for %pOF\n", node);
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {
> + .bind = mtk_disp_ovl_adaptor_comp_bind,
> + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> +{
> + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s-%d", __func__, __LINE__);
> +
> + component_bind_all(dev, priv->mmsys_dev);
> + return 0;
> +}
> +
> +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> +{
> +}
> +
> +static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {
> + .bind = mtk_disp_ovl_adaptor_master_bind,
> + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> +};
> +
> +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> +{
> + struct device_node *node;
> +
> + for_each_child_of_node(dev->parent->parent->of_node->parent, node) {
> + const struct of_device_id *of_id;
> + struct platform_device *comp_pdev;
> + enum mtk_ovl_adaptor_comp_type type;
> + int id;
> +
> + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node))
> + continue;
> +
> + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> +
> + id = ovl_adaptor_comp_get_id(dev, node, type);
> + if (id < 0)
> + continue;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev)
> + return -EPROBE_DEFER;
> +
> + if (!platform_get_drvdata(comp_pdev))
> + return -EPROBE_DEFER;
This function looks like ovl_adaptor_comp_init(), I think things could
be done once.
Regards,
Chun-Kuang.
> + }
> + return 0;
> +}
> +
> +static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_ovl_adaptor *priv;
> + struct device *dev = &pdev->dev;
> + struct component_match *match = NULL;
> + int ret;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> + if (ret < 0)
> + return ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->mmsys_dev = pdev->dev.platform_data;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = ovl_adaptor_comp_init(dev, &match);
> + if (ret) {
> + dev_notice(dev, "ovl_adaptor comp init fail\n");
> + return ret;
> + }
> + component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> + if (ret != 0) {
> + pm_runtime_disable(dev);
> + dev_err(dev, "Failed to add component: %d\n", ret);
> + }
> +
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> + pm_runtime_disable(&pdev->dev);
> + return 0;
> +}
> +
> +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> + .probe = mtk_disp_ovl_adaptor_probe,
> + .remove = mtk_disp_ovl_adaptor_remove,
> + .driver = {
> + .name = "mediatek-disp-ovl-adaptor",
> + .owner = THIS_MODULE,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..1ad9f7edfcc7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> --
> 2.18.0
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
2021-10-25 23:11 ` Chun-Kuang Hu
(?)
@ 2021-10-26 7:53 ` Nancy.Lin
-1 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-26 7:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Tue, 2021-10-26 at 07:11 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
>
OK.
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state,
> > cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels
> > align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
>
> pending->width is passed from caller function, the caller function
> does not expect that pending->width is modified by callee function.
>
OK, I will add local variable to keep the 2 pixel align width.
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2)
> > % 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height,
> > 0, 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
>
> This is neither l_w nor r_w, why?
> For example, if pending->width is 1922, l_w is 962, r_w is 960, and
> MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
>
The async width is set to the merge output width / 2, not for merge
input (l_w/r_w).
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config,
> > cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
>
> Does DRM framework not disable all layer before disable crtc? These
> codes looks asymetric.
>
DRM framework disable all layers before disabling crtc. This is a
redundant code fragment. I will remove it.
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> In clk_err, you count i to zero, so
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
>
> Drop ovl_adaptor_comp_str[] and print i instead of
> ovl_adaptor_comp_str[i]. We could know what the i mean in driver
> code.
>
OK.
>
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device
> > of node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node-
> > >parent, node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
>
> This function looks like ovl_adaptor_comp_init(), I think things
> could
> be done once.
>
> Regards,
> Chun-Kuang.
>
OK.
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index a58cebd01d35..1ad9f7edfcc7 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_ccorr_driver;
> > extern struct platform_driver mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-26 7:53 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-26 7:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Tue, 2021-10-26 at 07:11 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
>
OK.
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state,
> > cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels
> > align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
>
> pending->width is passed from caller function, the caller function
> does not expect that pending->width is modified by callee function.
>
OK, I will add local variable to keep the 2 pixel align width.
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2)
> > % 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height,
> > 0, 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
>
> This is neither l_w nor r_w, why?
> For example, if pending->width is 1922, l_w is 962, r_w is 960, and
> MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
>
The async width is set to the merge output width / 2, not for merge
input (l_w/r_w).
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config,
> > cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
>
> Does DRM framework not disable all layer before disable crtc? These
> codes looks asymetric.
>
DRM framework disable all layers before disabling crtc. This is a
redundant code fragment. I will remove it.
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> In clk_err, you count i to zero, so
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
>
> Drop ovl_adaptor_comp_str[] and print i instead of
> ovl_adaptor_comp_str[i]. We could know what the i mean in driver
> code.
>
OK.
>
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device
> > of node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node-
> > >parent, node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
>
> This function looks like ovl_adaptor_comp_init(), I think things
> could
> be done once.
>
> Regards,
> Chun-Kuang.
>
OK.
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index a58cebd01d35..1ad9f7edfcc7 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_ccorr_driver;
> > extern struct platform_driver mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 111+ messages in thread
* Re: [PATCH v6 14/16] drm/mediatek: add ovl_adaptor support for MT8195
@ 2021-10-26 7:53 ` Nancy.Lin
0 siblings, 0 replies; 111+ messages in thread
From: Nancy.Lin @ 2021-10-26 7:53 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
Thanks for the review.
On Tue, 2021-10-26 at 07:11 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道：
> >
> > Add ovl_adaptor driver for MT8195.
> > Ovl_adaptor is an encapsulated module and designed for simplified
> > DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and
> > an ETHDR. Two RDMAs merge into one layer, so this module support 4
> > layers.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 +
> > .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498
> > ++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 4 files changed, 516 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index fb158a1e7f06..3abd27d7c91d 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> > mtk_disp_gamma.o \
> > mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > + mtk_disp_ovl_adaptor.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > mtk_drm_ddp_comp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 2446ad0a4977..6a4f4c42aedb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev);
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev);
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev,
> > + void (*vblank_cb)(void *),
> > + void *vblank_cb_data);
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev);
> > +void mtk_ovl_adaptor_start(struct device *dev);
> > +void mtk_ovl_adaptor_stop(struct device *dev);
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
> > +
> > int mtk_mdp_rdma_clk_enable(struct device *dev);
> > void mtk_mdp_rdma_clk_disable(struct device *dev);
> > void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > new file mode 100644
> > index 000000000000..bfb5a9d29c26
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
> > @@ -0,0 +1,498 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <drm/drm_of.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_disp_drv.h"
>
> Alphabetic order.
>
OK.
> > +#include "mtk_ethdr.h"
> > +
> > +#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920
> > +#define MTK_OVL_ADAPTOR_LAYER_NUM 4
> > +
> > +enum mtk_ovl_adaptor_comp_type {
> > + OVL_ADAPTOR_TYPE_RDMA = 0,
> > + OVL_ADAPTOR_TYPE_MERGE,
> > + OVL_ADAPTOR_TYPE_ETHDR,
> > + OVL_ADAPTOR_TYPE_NUM,
> > +};
> > +
> > +enum mtk_ovl_adaptor_comp_id {
> > + OVL_ADAPTOR_MDP_RDMA0,
> > + OVL_ADAPTOR_MDP_RDMA1,
> > + OVL_ADAPTOR_MDP_RDMA2,
> > + OVL_ADAPTOR_MDP_RDMA3,
> > + OVL_ADAPTOR_MDP_RDMA4,
> > + OVL_ADAPTOR_MDP_RDMA5,
> > + OVL_ADAPTOR_MDP_RDMA6,
> > + OVL_ADAPTOR_MDP_RDMA7,
> > + OVL_ADAPTOR_MERGE0,
> > + OVL_ADAPTOR_MERGE1,
> > + OVL_ADAPTOR_MERGE2,
> > + OVL_ADAPTOR_MERGE3,
> > + OVL_ADAPTOR_ETHDR0,
> > + OVL_ADAPTOR_ID_MAX
> > +};
> > +
> > +struct ovl_adaptor_comp_match {
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int alias_id;
> > +};
> > +
> > +struct mtk_disp_ovl_adaptor {
> > + struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
> > + struct device *mmsys_dev;
> > +};
> > +
> > +static const char * const ovl_adaptor_comp_str[] = {
> > + "OVL_ADAPTOR_MDP_RDMA0",
> > + "OVL_ADAPTOR_MDP_RDMA1",
> > + "OVL_ADAPTOR_MDP_RDMA2",
> > + "OVL_ADAPTOR_MDP_RDMA3",
> > + "OVL_ADAPTOR_MDP_RDMA4",
> > + "OVL_ADAPTOR_MDP_RDMA5",
> > + "OVL_ADAPTOR_MDP_RDMA6",
> > + "OVL_ADAPTOR_MDP_RDMA7",
> > + "OVL_ADAPTOR_MERGE0",
> > + "OVL_ADAPTOR_MERGE1",
> > + "OVL_ADAPTOR_MERGE2",
> > + "OVL_ADAPTOR_MERGE3",
> > + "OVL_ADAPTOR_ETHDR",
> > + "OVL_ADAPTOR_ID_MAX"
> > +};
> > +
> > +static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM]
> > = {
> > + [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
> > + [OVL_ADAPTOR_TYPE_MERGE] = "merge",
> > + [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
> > +};
> > +
> > +static const struct ovl_adaptor_comp_match
> > comp_matches[OVL_ADAPTOR_ID_MAX] = {
> > + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0
> > },
> > + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1
> > },
> > + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2
> > },
> > + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3
> > },
> > + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4
> > },
> > + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5
> > },
> > + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6
> > },
> > + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7
> > },
> > + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
> > + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
> > + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
> > + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
> > + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },
> > +};
> > +
> > +void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int
> > idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + struct mtk_mdp_rdma_cfg rdma_config = {0};
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + struct device *ethdr;
> > + const struct drm_format_info *fmt_info =
> > drm_format_info(pending->format);
> > + bool use_dual_pipe = false;
> > + unsigned int l_w = 0;
> > + unsigned int r_w = 0;
> > +
> > + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__,
> > idx,
> > + pending->enable, pending->format);
> > + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> > + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> > + pending->x, pending->y, pending->width, pending-
> > >height);
> > +
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
> > + merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 +
> > idx];
> > + ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
> > +
> > + if (!pending->enable) {
> > + mtk_merge_disable(merge, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > + mtk_ethdr_layer_config(ethdr, idx, state,
> > cmdq_pkt);
> > + return;
> > + }
> > +
> > + /* ETHDR is in 1T2P domain, width needs to be 2 pixels
> > align */
> > + pending->width = ALIGN_DOWN(pending->width, 2);
>
> pending->width is passed from caller function, the caller function
> does not expect that pending->width is modified by callee function.
>
OK, I will add local variable to keep the 2 pixel align width.
> > +
> > + if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)
> > + use_dual_pipe = true;
> > +
> > + if (use_dual_pipe) {
> > + l_w = (pending->width / 2) + ((pending->width / 2)
> > % 2);
> > + r_w = pending->width - l_w;
> > + } else {
> > + l_w = pending->width;
> > + }
> > + mtk_merge_advance_config(merge, l_w, r_w, pending->height,
> > 0, 0, cmdq_pkt);
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> > + idx, pending->width / 2, cmdq_pkt);
>
> This is neither l_w nor r_w, why?
> For example, if pending->width is 1922, l_w is 962, r_w is 960, and
> MMSYS_CONFIG_MERGE_ASYNC_WIDTH is 961.
>
The async width is set to the merge output width / 2, not for merge
input (l_w/r_w).
> > + mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev,
> > MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> > + idx, pending->height, cmdq_pkt);
> > +
> > + rdma_config.width = l_w;
> > + rdma_config.height = pending->height;
> > + rdma_config.addr0 = pending->addr;
> > + rdma_config.pitch = pending->pitch;
> > + rdma_config.fmt = pending->format;
> > + mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
> > +
> > + if (use_dual_pipe) {
> > + rdma_config.x_left = l_w;
> > + rdma_config.width = r_w;
> > + mtk_mdp_rdma_config(rdma_r, &rdma_config,
> > cmdq_pkt);
> > + }
> > +
> > + mtk_merge_enable(merge, cmdq_pkt);
> > + mtk_merge_unmute(merge, cmdq_pkt);
> > +
> > + mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
> > + if (use_dual_pipe)
> > + mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
> > + else
> > + mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
> > +
> > + mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_config(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,
> > + vrefresh, bpc, cmdq_pkt);
> > +}
> > +
> > +void mtk_ovl_adaptor_start(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_start(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +void mtk_ovl_adaptor_stop(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *rdma_l;
> > + struct device *rdma_r;
> > + struct device *merge;
> > + u32 i;
> > +
> > + for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {
> > + rdma_l = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
> > + rdma_r = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
> > + merge = ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
> > +
> > + mtk_mdp_rdma_stop(rdma_l, NULL);
> > + mtk_mdp_rdma_stop(rdma_r, NULL);
> > + mtk_merge_stop(merge);
>
> Does DRM framework not disable all layer before disable crtc? These
> codes looks asymetric.
>
DRM framework disable all layers before disabling crtc. This is a
redundant code fragment. I will remove it.
> > + }
> > +
> > + mtk_ethdr_stop(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +int mtk_ovl_adaptor_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int ret;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> In clk_err, you count i to zero, so
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + ret = mtk_mdp_rdma_clk_enable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + ret = mtk_merge_clk_enable(comp);
> > + else
> > + ret = mtk_ethdr_clk_enable(comp);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to enable clock %d, err %d-
> > %s\n",
> > + i, ret, ovl_adaptor_comp_str[i]);
>
> Drop ovl_adaptor_comp_str[] and print i instead of
> ovl_adaptor_comp_str[i]. We could know what the i mean in driver
> code.
>
OK.
>
> > + goto clk_err;
> > + }
> > + }
> > +
> > + return ret;
> > +
> > +clk_err:
> > + while (--i >= 0) {
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > + return ret;
> > +}
> > +
> > +void mtk_ovl_adaptor_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > + struct device *comp;
> > + int i;
> > +
> > + for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX;
> > i++) {
>
> for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
>
OK.
> > + comp = ovl_adaptor->ovl_adaptor_comp[i];
> > +
> > + if (i < OVL_ADAPTOR_MERGE0)
> > + mtk_mdp_rdma_clk_disable(comp);
> > + else if (i < OVL_ADAPTOR_ETHDR0)
> > + mtk_merge_clk_disable(comp);
> > + else
> > + mtk_ethdr_clk_disable(comp);
> > + }
> > +}
> > +
> > +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
> > +{
> > + return MTK_OVL_ADAPTOR_LAYER_NUM;
> > +}
> > +
> > +void mtk_ovl_adaptor_enable_vblank(struct device *dev, void
> > (*vblank_cb)(void *),
> > + void *vblank_cb_data)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_enable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],
> > + vblank_cb, vblank_cb_data);
> > +}
> > +
> > +void mtk_ovl_adaptor_disable_vblank(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *ovl_adaptor =
> > dev_get_drvdata(dev);
> > +
> > + mtk_ethdr_disable_vblank(ovl_adaptor-
> > >ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
> > +}
> > +
> > +static int ovl_adaptor_comp_get_id(struct device *dev, struct
> > device_node *node,
> > + enum mtk_ovl_adaptor_comp_type
> > type)
> > +{
> > + int alias_id = of_alias_get_id(node,
> > private_comp_stem[type]);
> > + int ret;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> > + if (comp_matches[i].type == type &&
> > + comp_matches[i].alias_id == alias_id)
> > + return i;
> > +
> > + dev_err(dev, "Failed to get id. type: %d, alias: %d\n",
> > type, alias_id);
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
> > + {
> > + .compatible = "mediatek,mt8195-vdo1-rdma",
> > + .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
> > + }, {
> > + .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
> > + },
> > + {},
> > +};
> > +
> > +static int compare_of(struct device *dev, void *data)
> > +{
> > + return dev->of_node == data;
> > +}
> > +
> > +static int ovl_adaptor_comp_init(struct device *dev, struct
> > component_match **match)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > + struct device_node *node, *parent;
> > + struct platform_device *comp_pdev;
> > + int i, ret;
> > +
> > + parent = dev->parent->parent->of_node->parent;
> > +
> > + for_each_child_of_node(parent, node) {
> > + const struct of_device_id *of_id;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node)) {
> > + dev_info(dev, "Skipping disabled component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0) {
> > + dev_warn(dev, "Skipping unknown component
> > %pOF\n",
> > + node);
> > + continue;
> > + }
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev) {
> > + dev_warn(dev, "can't find platform device
> > of node:%s\n",
> > + node->name);
> > + return -ENODEV;
> > + }
> > + priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
> > +
> > + drm_of_component_match_add(dev, match, compare_of,
> > node);
> > + dev_info(dev, "Adding component match for %pOF\n",
> > node);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev,
> > struct device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_ovl_adaptor_comp_ops =
> > {
> > + .bind = mtk_disp_ovl_adaptor_comp_bind,
> > + .unbind = mtk_disp_ovl_adaptor_comp_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_master_bind(struct device *dev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
> > +
> > + dev_info(dev, "%s-%d", __func__, __LINE__);
> > +
> > + component_bind_all(dev, priv->mmsys_dev);
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev)
> > +{
> > +}
> > +
> > +static const struct component_master_ops
> > mtk_disp_ovl_adaptor_master_ops = {
> > + .bind = mtk_disp_ovl_adaptor_master_bind,
> > + .unbind = mtk_disp_ovl_adaptor_master_unbind,
> > +};
> > +
> > +static int mtk_disp_ovl_adaptor_check_comp(struct device *dev)
> > +{
> > + struct device_node *node;
> > +
> > + for_each_child_of_node(dev->parent->parent->of_node-
> > >parent, node) {
> > + const struct of_device_id *of_id;
> > + struct platform_device *comp_pdev;
> > + enum mtk_ovl_adaptor_comp_type type;
> > + int id;
> > +
> > + of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids,
> > node);
> > + if (!of_id)
> > + continue;
> > +
> > + if (!of_device_is_available(node))
> > + continue;
> > +
> > + type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
> > +
> > + id = ovl_adaptor_comp_get_id(dev, node, type);
> > + if (id < 0)
> > + continue;
> > +
> > + comp_pdev = of_find_device_by_node(node);
> > + if (!comp_pdev)
> > + return -EPROBE_DEFER;
> > +
> > + if (!platform_get_drvdata(comp_pdev))
> > + return -EPROBE_DEFER;
>
> This function looks like ovl_adaptor_comp_init(), I think things
> could
> be done once.
>
> Regards,
> Chun-Kuang.
>
OK.
> > + }
> > + return 0;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_probe(struct platform_device
> > *pdev)
> > +{
> > + struct mtk_disp_ovl_adaptor *priv;
> > + struct device *dev = &pdev->dev;
> > + struct component_match *match = NULL;
> > + int ret;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + ret = mtk_disp_ovl_adaptor_check_comp(dev);
> > + if (ret < 0)
> > + return ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->mmsys_dev = pdev->dev.platform_data;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = ovl_adaptor_comp_init(dev, &match);
> > + if (ret) {
> > + dev_notice(dev, "ovl_adaptor comp init fail\n");
> > + return ret;
> > + }
> > + component_master_add_with_match(dev,
> > &mtk_disp_ovl_adaptor_master_ops, match);
> > +
> > + pm_runtime_enable(dev);
> > +
> > + ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + if (ret != 0) {
> > + pm_runtime_disable(dev);
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > + }
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_ovl_adaptor_remove(struct platform_device
> > *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
> > + pm_runtime_disable(&pdev->dev);
> > + return 0;
> > +}
> > +
> > +struct platform_driver mtk_disp_ovl_adaptor_driver = {
> > + .probe = mtk_disp_ovl_adaptor_probe,
> > + .remove = mtk_disp_ovl_adaptor_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ovl-adaptor",
> > + .owner = THIS_MODULE,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index a58cebd01d35..1ad9f7edfcc7 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_ccorr_driver;
> > extern struct platform_driver mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > +extern struct platform_driver mtk_disp_ovl_adaptor_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > --
> > 2.18.0
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 111+ messages in thread
end of thread, other threads:[~2021-10-26 8:05 UTC | newest]
Thread overview: 111+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-04 6:21 [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-15 8:08 ` AngeloGioacchino Del Regno
2021-10-15 8:08 ` AngeloGioacchino Del Regno
2021-10-15 8:08 ` AngeloGioacchino Del Regno
2021-10-15 16:21 ` Chun-Kuang Hu
2021-10-15 16:21 ` Chun-Kuang Hu
2021-10-15 16:21 ` Chun-Kuang Hu
2021-10-04 6:21 ` [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-15 23:37 ` Chun-Kuang Hu
2021-10-15 23:37 ` Chun-Kuang Hu
2021-10-15 23:37 ` Chun-Kuang Hu
2021-10-22 7:18 ` Nancy.Lin
2021-10-22 7:18 ` Nancy.Lin
2021-10-22 7:18 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-15 23:41 ` Chun-Kuang Hu
2021-10-15 23:41 ` Chun-Kuang Hu
2021-10-15 23:41 ` Chun-Kuang Hu
2021-10-04 6:21 ` [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-14 14:52 ` AngeloGioacchino Del Regno
2021-10-14 14:52 ` AngeloGioacchino Del Regno
2021-10-14 14:52 ` AngeloGioacchino Del Regno
2021-10-04 6:21 ` [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 08/16] soc: mediatek: add cmdq support of " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-14 14:56 ` AngeloGioacchino Del Regno
2021-10-14 14:56 ` AngeloGioacchino Del Regno
2021-10-14 14:56 ` AngeloGioacchino Del Regno
2021-10-22 7:05 ` Nancy.Lin
2021-10-22 7:05 ` Nancy.Lin
2021-10-22 7:05 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-14 15:01 ` AngeloGioacchino Del Regno
2021-10-14 15:01 ` AngeloGioacchino Del Regno
2021-10-14 15:01 ` AngeloGioacchino Del Regno
2021-10-22 7:33 ` Nancy.Lin
2021-10-22 7:33 ` Nancy.Lin
2021-10-22 7:33 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-19 16:38 ` Chun-Kuang Hu
2021-10-19 16:38 ` Chun-Kuang Hu
2021-10-19 16:38 ` Chun-Kuang Hu
2021-10-25 1:48 ` Nancy.Lin
2021-10-25 1:48 ` Nancy.Lin
2021-10-25 1:48 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 12/16] drm/mediatek: add display merge api " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-21 15:02 ` Chun-Kuang Hu
2021-10-21 15:02 ` Chun-Kuang Hu
2021-10-21 15:02 ` Chun-Kuang Hu
2021-10-25 2:10 ` Nancy.Lin
2021-10-25 2:10 ` Nancy.Lin
2021-10-25 2:10 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 13/16] drm/mediatek: add ETHDR " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-21 15:44 ` Chun-Kuang Hu
2021-10-21 15:44 ` Chun-Kuang Hu
2021-10-21 15:44 ` Chun-Kuang Hu
2021-10-25 2:24 ` Nancy.Lin
2021-10-25 2:24 ` Nancy.Lin
2021-10-25 2:24 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 14/16] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-15 7:49 ` AngeloGioacchino Del Regno
2021-10-15 7:49 ` AngeloGioacchino Del Regno
2021-10-15 7:49 ` AngeloGioacchino Del Regno
2021-10-25 2:42 ` Nancy.Lin
2021-10-25 2:42 ` Nancy.Lin
2021-10-25 2:42 ` Nancy.Lin
2021-10-25 23:11 ` Chun-Kuang Hu
2021-10-25 23:11 ` Chun-Kuang Hu
2021-10-25 23:11 ` Chun-Kuang Hu
2021-10-26 7:53 ` Nancy.Lin
2021-10-26 7:53 ` Nancy.Lin
2021-10-26 7:53 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
2021-10-04 6:21 ` Nancy.Lin
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