* [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-17 9:03 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through
by several modules, such as, PSEUDO_OVL, ETHDR, and MERGE.
Add DRM and these modules support by the patches below:
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
---
Nancy.Lin (10):
[PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
[PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
[PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
[PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
[PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
[PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
[PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
[PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
[PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
[PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../display/mediatek/mediatek,disp.yaml | 10 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 ++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 24 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 ++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 63 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 375 ++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++-
drivers/soc/mediatek/mtk-mmsys.c | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 +++++---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
23 files changed, 3166 insertions(+), 194 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-17 9:03 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
The hardware path of vdosys1 with DPTx output need to go through
by several modules, such as, PSEUDO_OVL, ETHDR, and MERGE.
Add DRM and these modules support by the patches below:
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
---
Nancy.Lin (10):
[PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
[PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
[PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
[PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
[PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
[PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
[PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
[PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
[PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
[PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../display/mediatek/mediatek,disp.yaml | 10 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 ++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 24 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 ++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 63 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 375 ++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++-
drivers/soc/mediatek/mtk-mmsys.c | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 +++++---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
23 files changed, 3166 insertions(+), 194 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195
@ 2021-07-17 9:03 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
The hardware path of vdosys1 with DPTx output need to go through
by several modules, such as, PSEUDO_OVL, ETHDR, and MERGE.
Add DRM and these modules support by the patches below:
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
This series are based on the following patch:
[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2] arm64: dts: mt8195: add IOMMU and smi nodes
https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3] [01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
https://patchwork.kernel.org/project/linux-mediatek/patch/20210630023504.18177-2-yong.wu@mediatek.com/
[4] Add gce support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=515599
[5] Add MediaTek SoC DRM (vdosys0) support for mt8195
https://patchwork.kernel.org/project/linux-mediatek/list/?series=516277
---
Nancy.Lin (10):
[PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
[PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
[PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
[PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
[PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
[PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
[PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
[PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
[PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm
data.
[PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
.../display/mediatek/mediatek,disp.yaml | 10 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 ++++++
drivers/gpu/drm/mediatek/Makefile | 5 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 24 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 ++
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 37 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 63 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 375 ++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++-
drivers/soc/mediatek/mtk-mmsys.c | 11 +
drivers/soc/mediatek/mtk-mutex.c | 270 +++++---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
23 files changed, 3166 insertions(+), 194 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
--
2.18.0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:03 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..bb6d28572b48 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,11 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
new file mode 100644
index 000000000000..9059d96ce70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek pseudo ovl Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ The Mediatek pseudo ovl function block is composed of eight RDMA and
+ four MERGE devices. It's encapsulated as an overlay device, which supports
+ 4 layers.
+
+properties:
+ compatible:
+ oneOf:
+ # pseudo ovl controller
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ maxItems: 1
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const:
+ - mediatek,mt8195-vdo1-merge
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: merge clock
+ - description: merge async clock
+ clock-names:
+ items:
+ - const: merge
+ - const: merge_async
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma",
+ "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-17 9:03 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..bb6d28572b48 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,11 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
new file mode 100644
index 000000000000..9059d96ce70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek pseudo ovl Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ The Mediatek pseudo ovl function block is composed of eight RDMA and
+ four MERGE devices. It's encapsulated as an overlay device, which supports
+ 4 layers.
+
+properties:
+ compatible:
+ oneOf:
+ # pseudo ovl controller
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ maxItems: 1
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const:
+ - mediatek,mt8195-vdo1-merge
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: merge clock
+ - description: merge async clock
+ clock-names:
+ items:
+ - const: merge
+ - const: merge_async
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma",
+ "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-17 9:03 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:03 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..bb6d28572b48 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,11 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
new file mode 100644
index 000000000000..9059d96ce70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek pseudo ovl Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ The Mediatek pseudo ovl function block is composed of eight RDMA and
+ four MERGE devices. It's encapsulated as an overlay device, which supports
+ 4 layers.
+
+properties:
+ compatible:
+ oneOf:
+ # pseudo ovl controller
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ maxItems: 1
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const:
+ - mediatek,mt8195-vdo1-merge
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: merge clock
+ - description: merge async clock
+ clock-names:
+ items:
+ - const: merge
+ - const: merge_async
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma",
+ "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++++++++++++++++
2 files changed, 142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index bb6d28572b48..a339c8be8225 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -235,6 +235,11 @@ properties:
- items:
- const: mediatek,mt8195-disp-pseudo-ovl
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..7320350910be
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
+
+...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++++++++++++++++
2 files changed, 142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index bb6d28572b48..a339c8be8225 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -235,6 +235,11 @@ properties:
- items:
- const: mediatek,mt8195-disp-pseudo-ovl
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..7320350910be
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 02/10] dt-bindings: mediatek: add ethdr definition for mt8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
1. Add ethdr definition file for mt8195 display.
2. Add mediatek,ethdr.yaml to decribe ethdr module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,ethdr.yaml | 137 ++++++++++++++++++
2 files changed, 142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index bb6d28572b48..a339c8be8225 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -235,6 +235,11 @@ properties:
- items:
- const: mediatek,mt8195-disp-pseudo-ovl
+ # ETHDR: see Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-ethdr
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 000000000000..7320350910be
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek ethdr Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ ETHDR is designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color space/color
+ format conversion, and then combine different layers, output the required HDR or
+ SDR signal to the subsequent display path. This engine is composed of two video
+ frontends, two graphic frontends, one video backend and a mixer.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt8195-disp-ethdr
+ reg:
+ maxItems: 7
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ interrupts:
+ minItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ minItems: 1
+ maxItems: 2
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
+
+...
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 +++++++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..5dc9bf6edda0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -20,6 +20,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,8 +1290,199 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
};
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma", "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
};
bring-up {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 +++++++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..5dc9bf6edda0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -20,6 +20,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,8 +1290,199 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
};
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma", "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
};
bring-up {
--
2.18.0
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add display node for vdosys1.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 206 +++++++++++++++++++++++
1 file changed, 206 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa2a7849b822..5dc9bf6edda0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -20,6 +20,21 @@
aliases {
gce0 = &gce0;
gce1 = &gce1;
+ mutex0 = &mutex;
+ mutex1 = &mutex1;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ vdo1_rdma0 = &vdo1_rdma0;
+ vdo1_rdma1 = &vdo1_rdma1;
+ vdo1_rdma2 = &vdo1_rdma2;
+ vdo1_rdma3 = &vdo1_rdma3;
+ vdo1_rdma4 = &vdo1_rdma4;
+ vdo1_rdma5 = &vdo1_rdma5;
+ vdo1_rdma6 = &vdo1_rdma6;
+ vdo1_rdma7 = &vdo1_rdma7;
};
clocks {
@@ -1275,8 +1290,199 @@
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-vdosys1", "syscon";
reg = <0 0x1c100000 0 0x1000>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
#clock-cells = <1>;
};
+
+ mutex1: disp_mutex0@1c101000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo1_mutex";
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ clock-names = "vdo1_mutex";
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ vdo1_rdma0: vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma", "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: vdo1_rdma@1c105000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: vdo1_rdma@1c106000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: vdo1_rdma@1c107000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: vdo1_rdma@1c108000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: vdo1_rdma@1c109000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: vdo1_rdma@1c10a000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: vdo1_rdma@1c10b000 {
+ compatible = "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+ merge2: disp_vpp_merge@1c10d000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ };
+
+ merge3: disp_vpp_merge@1c10e000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ };
+
+ merge4: disp_vpp_merge@1c10f000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ };
+
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ };
+
};
bring-up {
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..bc4e291dbe35 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..f9b227a07fe6 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..bc4e291dbe35 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..f9b227a07fe6 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..bc4e291dbe35 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..f9b227a07fe6 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..9c40b394f533 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_ETHDR] = MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..9c40b394f533 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_ETHDR] = MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add mtk-mutex support for mt8195 vdosys1.
The vdosys1 path component contains pseudo_ovl, ethdr, merge5,
and dp_intf1. Pseudo_ovl and ethdr components are both composed
of several sub-elements, so change it to support multi-bit control.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 270 ++++++++++++++++++-------------
1 file changed, 162 insertions(+), 108 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index cb8bbf7f3fd8..9c40b394f533 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -29,101 +29,130 @@
#define INT_MUTEX BIT(1)
-#define MT8167_MUTEX_MOD_DISP_PWM 1
-#define MT8167_MUTEX_MOD_DISP_OVL0 6
-#define MT8167_MUTEX_MOD_DISP_OVL1 7
-#define MT8167_MUTEX_MOD_DISP_RDMA0 8
-#define MT8167_MUTEX_MOD_DISP_RDMA1 9
-#define MT8167_MUTEX_MOD_DISP_WDMA0 10
-#define MT8167_MUTEX_MOD_DISP_CCORR 11
-#define MT8167_MUTEX_MOD_DISP_COLOR 12
-#define MT8167_MUTEX_MOD_DISP_AAL 13
-#define MT8167_MUTEX_MOD_DISP_GAMMA 14
-#define MT8167_MUTEX_MOD_DISP_DITHER 15
-#define MT8167_MUTEX_MOD_DISP_UFOE 16
-
-#define MT8183_MUTEX_MOD_DISP_RDMA0 0
-#define MT8183_MUTEX_MOD_DISP_RDMA1 1
-#define MT8183_MUTEX_MOD_DISP_OVL0 9
-#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
-#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
-#define MT8183_MUTEX_MOD_DISP_WDMA0 12
-#define MT8183_MUTEX_MOD_DISP_COLOR0 13
-#define MT8183_MUTEX_MOD_DISP_CCORR0 14
-#define MT8183_MUTEX_MOD_DISP_AAL0 15
-#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
-#define MT8183_MUTEX_MOD_DISP_DITHER0 17
-
-#define MT8173_MUTEX_MOD_DISP_OVL0 11
-#define MT8173_MUTEX_MOD_DISP_OVL1 12
-#define MT8173_MUTEX_MOD_DISP_RDMA0 13
-#define MT8173_MUTEX_MOD_DISP_RDMA1 14
-#define MT8173_MUTEX_MOD_DISP_RDMA2 15
-#define MT8173_MUTEX_MOD_DISP_WDMA0 16
-#define MT8173_MUTEX_MOD_DISP_WDMA1 17
-#define MT8173_MUTEX_MOD_DISP_COLOR0 18
-#define MT8173_MUTEX_MOD_DISP_COLOR1 19
-#define MT8173_MUTEX_MOD_DISP_AAL 20
-#define MT8173_MUTEX_MOD_DISP_GAMMA 21
-#define MT8173_MUTEX_MOD_DISP_UFOE 22
-#define MT8173_MUTEX_MOD_DISP_PWM0 23
-#define MT8173_MUTEX_MOD_DISP_PWM1 24
-#define MT8173_MUTEX_MOD_DISP_OD 25
-
-#define MT8195_MUTEX_MOD_DISP_OVL0 0
-#define MT8195_MUTEX_MOD_DISP_WDMA0 1
-#define MT8195_MUTEX_MOD_DISP_RDMA0 2
-#define MT8195_MUTEX_MOD_DISP_COLOR0 3
-#define MT8195_MUTEX_MOD_DISP_CCORR0 4
-#define MT8195_MUTEX_MOD_DISP_AAL0 5
-#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
-#define MT8195_MUTEX_MOD_DISP_DITHER0 7
-#define MT8195_MUTEX_MOD_DISP_DSI0 8
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
-#define MT8195_MUTEX_MOD_DISP_OVL1 10
-#define MT8195_MUTEX_MOD_DISP_WDMA1 11
-#define MT8195_MUTEX_MOD_DISP_RDMA1 12
-#define MT8195_MUTEX_MOD_DISP_COLOR1 13
-#define MT8195_MUTEX_MOD_DISP_CCORR1 14
-#define MT8195_MUTEX_MOD_DISP_AAL1 15
-#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
-#define MT8195_MUTEX_MOD_DISP_DITHER1 17
-#define MT8195_MUTEX_MOD_DISP_DSI1 18
-#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
-#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
-#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
-#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
-#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
-#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
-#define MT8195_MUTEX_MOD_DISP_PWM0 27
-#define MT8195_MUTEX_MOD_DISP_PWM1 28
-
-#define MT2712_MUTEX_MOD_DISP_PWM2 10
-#define MT2712_MUTEX_MOD_DISP_OVL0 11
-#define MT2712_MUTEX_MOD_DISP_OVL1 12
-#define MT2712_MUTEX_MOD_DISP_RDMA0 13
-#define MT2712_MUTEX_MOD_DISP_RDMA1 14
-#define MT2712_MUTEX_MOD_DISP_RDMA2 15
-#define MT2712_MUTEX_MOD_DISP_WDMA0 16
-#define MT2712_MUTEX_MOD_DISP_WDMA1 17
-#define MT2712_MUTEX_MOD_DISP_COLOR0 18
-#define MT2712_MUTEX_MOD_DISP_COLOR1 19
-#define MT2712_MUTEX_MOD_DISP_AAL0 20
-#define MT2712_MUTEX_MOD_DISP_UFOE 22
-#define MT2712_MUTEX_MOD_DISP_PWM0 23
-#define MT2712_MUTEX_MOD_DISP_PWM1 24
-#define MT2712_MUTEX_MOD_DISP_OD0 25
-#define MT2712_MUTEX_MOD2_DISP_AAL1 33
-#define MT2712_MUTEX_MOD2_DISP_OD1 34
-
-#define MT2701_MUTEX_MOD_DISP_OVL 3
-#define MT2701_MUTEX_MOD_DISP_WDMA 6
-#define MT2701_MUTEX_MOD_DISP_COLOR 7
-#define MT2701_MUTEX_MOD_DISP_BLS 9
-#define MT2701_MUTEX_MOD_DISP_RDMA0 10
-#define MT2701_MUTEX_MOD_DISP_RDMA1 12
+#define MT8167_MUTEX_MOD_DISP_PWM BIT(1)
+#define MT8167_MUTEX_MOD_DISP_OVL0 BIT(6)
+#define MT8167_MUTEX_MOD_DISP_OVL1 BIT(7)
+#define MT8167_MUTEX_MOD_DISP_RDMA0 BIT(8)
+#define MT8167_MUTEX_MOD_DISP_RDMA1 BIT(9)
+#define MT8167_MUTEX_MOD_DISP_WDMA0 BIT(10)
+#define MT8167_MUTEX_MOD_DISP_CCORR BIT(11)
+#define MT8167_MUTEX_MOD_DISP_COLOR BIT(12)
+#define MT8167_MUTEX_MOD_DISP_AAL BIT(13)
+#define MT8167_MUTEX_MOD_DISP_GAMMA BIT(14)
+#define MT8167_MUTEX_MOD_DISP_DITHER BIT(15)
+#define MT8167_MUTEX_MOD_DISP_UFOE BIT(16)
+
+#define MT8183_MUTEX_MOD_DISP_RDMA0 BIT(0)
+#define MT8183_MUTEX_MOD_DISP_RDMA1 BIT(1)
+#define MT8183_MUTEX_MOD_DISP_OVL0 BIT(9)
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L BIT(10)
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L BIT(11)
+#define MT8183_MUTEX_MOD_DISP_WDMA0 BIT(12)
+#define MT8183_MUTEX_MOD_DISP_COLOR0 BIT(13)
+#define MT8183_MUTEX_MOD_DISP_CCORR0 BIT(14)
+#define MT8183_MUTEX_MOD_DISP_AAL0 BIT(15)
+#define MT8183_MUTEX_MOD_DISP_GAMMA0 BIT(16)
+#define MT8183_MUTEX_MOD_DISP_DITHER0 BIT(17)
+
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
+
+#define MT8195_MUTEX_MOD_DISP_OVL0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP_WDMA0 BIT(1)
+#define MT8195_MUTEX_MOD_DISP_RDMA0 BIT(2)
+#define MT8195_MUTEX_MOD_DISP_COLOR0 BIT(3)
+#define MT8195_MUTEX_MOD_DISP_CCORR0 BIT(4)
+#define MT8195_MUTEX_MOD_DISP_AAL0 BIT(5)
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 BIT(6)
+#define MT8195_MUTEX_MOD_DISP_DITHER0 BIT(7)
+#define MT8195_MUTEX_MOD_DISP_DSI0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(9)
+#define MT8195_MUTEX_MOD_DISP_OVL1 BIT(10)
+#define MT8195_MUTEX_MOD_DISP_WDMA1 BIT(11)
+#define MT8195_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8195_MUTEX_MOD_DISP_COLOR1 BIT(13)
+#define MT8195_MUTEX_MOD_DISP_CCORR1 BIT(14)
+#define MT8195_MUTEX_MOD_DISP_AAL1 BIT(15)
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 BIT(16)
+#define MT8195_MUTEX_MOD_DISP_DITHER1 BIT(17)
+#define MT8195_MUTEX_MOD_DISP_DSI1 BIT(18)
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(19)
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE BIT(20)
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 BIT(22)
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 BIT(23)
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 BIT(24)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 BIT(25)
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 BIT(26)
+#define MT8195_MUTEX_MOD_DISP_PWM0 BIT(27)
+#define MT8195_MUTEX_MOD_DISP_PWM1 BIT(28)
+
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 BIT(0)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 BIT(1)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 BIT(2)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 BIT(3)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 BIT(4)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 BIT(5)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 BIT(6)
+#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 BIT(7)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 BIT(8)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 BIT(9)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 BIT(10)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 BIT(11)
+#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 BIT(12)
+#define MT8195_MUTEX_MOD_DISP1_VPP2_DL_RELAY BIT(13)
+#define MT8195_MUTEX_MOD_DISP1_VPP3_DL_RELAY BIT(14)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_DSC_DL_ASYNC BIT(15)
+#define MT8195_MUTEX_MOD_DISP1_VDO0_MERGE_DL_ASYNC BIT(16)
+#define MT8195_MUTEX_MOD_DISP1_VDO1_OUT_DL_RELAY BIT(17)
+#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER BIT(18)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 BIT(19)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 BIT(20)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 BIT(21)
+#define MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 BIT(22)
+#define MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 BIT(23)
+#define MT8195_MUTEX_MOD_DISP1_HDR_MLOAD BIT(24)
+#define MT8195_MUTEX_MOD_DISP1_DPI0 BIT(25)
+#define MT8195_MUTEX_MOD_DISP1_DPI1 BIT(26)
+#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 BIT(27)
+
+#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
+#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13)
+#define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14)
+#define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15)
+#define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16)
+#define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17)
+#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
+#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
+#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
+#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
+#define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
+#define MT2712_MUTEX_MOD2_DISP_OD1 BIT(34)
+
+#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
#define MT2712_MUTEX_SOF_SINGLE_MODE 0
#define MT2712_MUTEX_SOF_DSI0 1
@@ -174,7 +203,7 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
+ const unsigned long *mutex_mod;
const unsigned int *mutex_sof;
const unsigned int mutex_mod_reg;
const unsigned int mutex_sof_reg;
@@ -189,7 +218,7 @@ struct mtk_mutex_ctx {
const struct mtk_mutex_data *data;
};
-static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
[DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
@@ -198,7 +227,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
-static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
[DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
@@ -218,7 +247,7 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
@@ -233,7 +262,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
@@ -251,7 +280,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
-static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
@@ -265,7 +294,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+static const unsigned long mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
@@ -278,6 +307,27 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PSEUDO_OVL] = MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 |
+ MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 |
+ MT8195_MUTEX_MOD_DISP1_VPP_MERGE3,
+ [DDP_COMPONENT_ETHDR] = MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_GFX_FE1 |
+ MT8195_MUTEX_MOD_DISP1_HDR_VDO_BE0 |
+ MT8195_MUTEX_MOD_DISP1_HDR_MLOAD |
+ MT8195_MUTEX_MOD_DISP1_DISP_MIXER,
+ [DDP_COMPONENT_MERGE5] = MT8195_MUTEX_MOD_DISP1_VPP_MERGE4,
+ [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0,
};
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
@@ -432,17 +482,20 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF1:
+ sof_id = MUTEX_SOF_DP_INTF1;
+ break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << mtx->data->mutex_mod[id];
+ reg |= mtx->data->mutex_mod[id];
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg |= 1 << (mtx->data->mutex_mod[id] - 32);
+ reg |= (mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
return;
@@ -471,22 +524,23 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF1:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
mutex->id));
break;
default:
- if (mtx->data->mutex_mod[id] < 32) {
+ if (mtx->data->mutex_mod[id] <= BIT(31)) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << mtx->data->mutex_mod[id]);
+ reg &= ~(mtx->data->mutex_mod[id]);
writel_relaxed(reg, mtx->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(mtx->regs + offset);
- reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
+ reg &= ~(mtx->data->mutex_mod[id] >> 32);
writel_relaxed(reg, mtx->regs + offset);
}
break;
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
8 files changed, 584 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..fcce08710cef 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..7227ffbc3eae 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..3fa86f12feb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_COLOR] = "color",
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_AAL] = "aal",
+ [MTK_DISP_ETHDR] = "ethdr",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_UFOE] = "ufoe",
@@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
+ [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
@@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_DSC ||
+ type == MTK_DISP_ETHDR ||
type == MTK_DISP_GAMMA ||
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f55efba6e744 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_ETHDR,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..ace958a34bb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_ETHDR },
{ }
};
@@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_DSC ||
+ comp_type == MTK_DISP_ETHDR ||
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
@@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..ceadb28169b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+#define MIX_ROI_BGCLR 0x20
+#define MIX_SRC_CON 0x24
+#define MIX_L0_CON 0x28
+#define MIX_L0_SRC_SIZE 0x30
+#define MIX_L0_OFFSET 0x34
+#define MIX_L1_CON 0x40
+#define MIX_L1_SRC_SIZE 0x48
+#define MIX_L1_OFFSET 0x4c
+#define MIX_L2_CON 0x58
+#define MIX_L2_SRC_SIZE 0x60
+#define MIX_L2_OFFSET 0x64
+#define MIX_L3_CON 0x70
+#define MIX_L3_SRC_SIZE 0x78
+#define MIX_L3_OFFSET 0x7c
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
+#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
+#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
+#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
+#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
+#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
+
+#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
+#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
+#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
+#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
+#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
+#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
+#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
+#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
+#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
+#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
+#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
+#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
+
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
+#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_SW1_RST_B 0x1d4
+ #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
+#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
+#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
+ #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
+ #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
+ #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
+ #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
+#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
+#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
+#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
+#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
+#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
+
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ void __iomem *top_regs;
+ struct cmdq_client_reg top_cmdq_base;
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+static const unsigned int alpha_source_sel[] = {
+ HDR_ALPHA_SEL_MIXER_IN1,
+ HDR_ALPHA_SEL_MIXER_IN2,
+ HDR_ALPHA_SEL_MIXER_IN3,
+ HDR_ALPHA_SEL_MIXER_IN4,
+};
+
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx < 4)
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
+ mixer->regs, MIX_SRC_CON, BIT(idx));
+}
+
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ fmt = state->pending.format;
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ }
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_CON, 0x1ff);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_CON, 0x1ff);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_CON, 0x1ff);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_CON, 0x1ff);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
+ mixer->regs, MIX_ROI_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0204_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0320_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM0, ~0);
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM1, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
+ MIX_DATAPATH_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
+ MIX_ROI_BGCLR, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
+ MIX_EN, ~0);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
+ mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_SW1_RST_B,
+ HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..c8fc0581a632
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_ETHDR_H__
+#define __MTK_DISP_ETHDR_H__
+
+#include <linux/uaccess.h>
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+#endif
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
8 files changed, 584 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..fcce08710cef 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..7227ffbc3eae 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..3fa86f12feb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_COLOR] = "color",
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_AAL] = "aal",
+ [MTK_DISP_ETHDR] = "ethdr",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_UFOE] = "ufoe",
@@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
+ [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
@@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_DSC ||
+ type == MTK_DISP_ETHDR ||
type == MTK_DISP_GAMMA ||
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f55efba6e744 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_ETHDR,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..ace958a34bb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_ETHDR },
{ }
};
@@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_DSC ||
+ comp_type == MTK_DISP_ETHDR ||
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
@@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..ceadb28169b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+#define MIX_ROI_BGCLR 0x20
+#define MIX_SRC_CON 0x24
+#define MIX_L0_CON 0x28
+#define MIX_L0_SRC_SIZE 0x30
+#define MIX_L0_OFFSET 0x34
+#define MIX_L1_CON 0x40
+#define MIX_L1_SRC_SIZE 0x48
+#define MIX_L1_OFFSET 0x4c
+#define MIX_L2_CON 0x58
+#define MIX_L2_SRC_SIZE 0x60
+#define MIX_L2_OFFSET 0x64
+#define MIX_L3_CON 0x70
+#define MIX_L3_SRC_SIZE 0x78
+#define MIX_L3_OFFSET 0x7c
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
+#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
+#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
+#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
+#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
+#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
+
+#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
+#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
+#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
+#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
+#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
+#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
+#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
+#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
+#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
+#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
+#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
+#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
+
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
+#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_SW1_RST_B 0x1d4
+ #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
+#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
+#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
+ #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
+ #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
+ #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
+ #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
+#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
+#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
+#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
+#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
+#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
+
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ void __iomem *top_regs;
+ struct cmdq_client_reg top_cmdq_base;
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+static const unsigned int alpha_source_sel[] = {
+ HDR_ALPHA_SEL_MIXER_IN1,
+ HDR_ALPHA_SEL_MIXER_IN2,
+ HDR_ALPHA_SEL_MIXER_IN3,
+ HDR_ALPHA_SEL_MIXER_IN4,
+};
+
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx < 4)
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
+ mixer->regs, MIX_SRC_CON, BIT(idx));
+}
+
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ fmt = state->pending.format;
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ }
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_CON, 0x1ff);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_CON, 0x1ff);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_CON, 0x1ff);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_CON, 0x1ff);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
+ mixer->regs, MIX_ROI_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0204_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0320_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM0, ~0);
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM1, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
+ MIX_DATAPATH_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
+ MIX_ROI_BGCLR, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
+ MIX_EN, ~0);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
+ mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_SW1_RST_B,
+ HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..c8fc0581a632
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_ETHDR_H__
+#define __MTK_DISP_ETHDR_H__
+
+#include <linux/uaccess.h>
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+#endif
+
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add ETHDR module files:
ETHDR is designed for HDR video and graphics conversion in the external
display path. It handles multiple HDR input types and performs tone
mapping, color space/color format conversion, and then combines
different layers, output the required HDR or SDR signal to the
subsequent display path.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
8 files changed, 584 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 27c89847d43b..fcce08710cef 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_gem.o \
mtk_drm_plane.o \
mtk_dsi.o \
- mtk_dpi.o
+ mtk_dpi.o \
+ mtk_ethdr.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e27ce7fef57..7227ffbc3eae 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_ethdr_clk_enable(struct device *dev);
+void mtk_ethdr_clk_disable(struct device *dev);
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_start(struct device *dev);
+void mtk_ethdr_stop(struct device *dev);
+
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 9125d0f6352f..3fa86f12feb4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_ethdr = {
+ .clk_enable = mtk_ethdr_clk_enable,
+ .clk_disable = mtk_ethdr_clk_disable,
+ .config = mtk_ethdr_config,
+ .start = mtk_ethdr_start,
+ .stop = mtk_ethdr_stop,
+};
+
static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OVL] = "ovl",
[MTK_DISP_OVL_2L] = "ovl-2l",
@@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_COLOR] = "color",
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_AAL] = "aal",
+ [MTK_DISP_ETHDR] = "ethdr",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_UFOE] = "ufoe",
@@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
+ [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
@@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_DSC ||
+ type == MTK_DISP_ETHDR ||
type == MTK_DISP_GAMMA ||
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0afd78c0bc92..f55efba6e744 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_BLS,
MTK_DISP_DSC,
MTK_DISP_MERGE,
+ MTK_DISP_ETHDR,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 11c25daf05d8..ace958a34bb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-ethdr",
+ .data = (void *)MTK_DISP_ETHDR },
{ }
};
@@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_DSC ||
+ comp_type == MTK_DISP_ETHDR ||
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
@@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_ethdr_driver,
};
static int __init mtk_drm_init(void)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c4d802a43531..c87ebb5309d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
new file mode 100644
index 000000000000..ceadb28169b8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_ethdr.h"
+
+#define MIX_EN 0xc
+#define MIX_RST 0x14
+#define MIX_ROI_SIZE 0x18
+#define MIX_DATAPATH_CON 0x1c
+#define MIX_ROI_BGCLR 0x20
+#define MIX_SRC_CON 0x24
+#define MIX_L0_CON 0x28
+#define MIX_L0_SRC_SIZE 0x30
+#define MIX_L0_OFFSET 0x34
+#define MIX_L1_CON 0x40
+#define MIX_L1_SRC_SIZE 0x48
+#define MIX_L1_OFFSET 0x4c
+#define MIX_L2_CON 0x58
+#define MIX_L2_SRC_SIZE 0x60
+#define MIX_L2_OFFSET 0x64
+#define MIX_L3_CON 0x70
+#define MIX_L3_SRC_SIZE 0x78
+#define MIX_L3_OFFSET 0x7c
+#define MIX_FUNC_DCM0 0x120
+#define MIX_FUNC_DCM1 0x124
+
+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
+#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
+#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
+#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
+#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
+#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
+#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
+
+#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
+#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
+#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
+#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
+#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
+#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
+#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
+#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
+#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
+#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
+#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
+#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
+#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
+
+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
+#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
+#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_SW1_RST_B 0x1d4
+ #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
+#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
+#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
+ #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
+ #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
+ #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
+ #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
+#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
+#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
+#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
+#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
+#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
+
+#define MIXER_ALPHA_AEN BIT(8)
+#define MIXER_ALPHA 0xff
+#define ETHDR_CLK_NUM 13
+
+enum mtk_ethdr_comp_id {
+ ETHDR_MIXER,
+ ETHDR_VDO_FE0,
+ ETHDR_VDO_FE1,
+ ETHDR_GFX_FE0,
+ ETHDR_GFX_FE1,
+ ETHDR_VDO_BE,
+ ETHDR_ADL_DS,
+ ETHDR_ID_MAX
+};
+
+struct mtk_ethdr_comp {
+ struct device *dev;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_base;
+};
+
+struct mtk_ethdr {
+ void __iomem *top_regs;
+ struct cmdq_client_reg top_cmdq_base;
+ struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
+ struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
+};
+
+static const char * const ethdr_comp_str[] = {
+ "ETHDR_MIXER",
+ "ETHDR_VDO_FE0",
+ "ETHDR_VDO_FE1",
+ "ETHDR_GFX_FE0",
+ "ETHDR_GFX_FE1",
+ "ETHDR_VDO_BE",
+ "ETHDR_ADL_DS",
+ "ETHDR_ID_MAX"
+};
+
+static const char * const ethdr_clk_str[] = {
+ "ethdr_top",
+ "mixer",
+ "vdo_fe0",
+ "vdo_fe1",
+ "gfx_fe0",
+ "gfx_fe1",
+ "vdo_be",
+ "adl_ds",
+ "vdo_fe0_async",
+ "vdo_fe1_async",
+ "gfx_fe0_async",
+ "gfx_fe1_async",
+ "vdo_be_async",
+};
+
+static const unsigned int alpha_source_sel[] = {
+ HDR_ALPHA_SEL_MIXER_IN1,
+ HDR_ALPHA_SEL_MIXER_IN2,
+ HDR_ALPHA_SEL_MIXER_IN3,
+ HDR_ALPHA_SEL_MIXER_IN4,
+};
+
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ if (idx < 4)
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
+ mixer->regs, MIX_SRC_CON, BIT(idx));
+}
+
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s+ idx:%d", __func__, idx);
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int offset = (pending->y << 16) | pending->x;
+ unsigned int alpha_con = 0;
+ unsigned int fmt = 0;
+
+ fmt = state->pending.format;
+
+ if (state->base.fb && state->base.fb->format->has_alpha) {
+ alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
+ }
+
+ switch (idx) {
+ case 0:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L0_CON, 0x1ff);
+ break;
+ case 1:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L1_CON, 0x1ff);
+ break;
+ case 2:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L2_CON, 0x1ff);
+ break;
+ case 3:
+ mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_OFFSET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
+ mixer->regs, MIX_L3_CON, 0x1ff);
+ break;
+ default:
+ dev_dbg(dev, "%s Wrong layer ID\n", __func__);
+ break;
+ }
+}
+
+void mtk_ethdr_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
+ mixer->regs, MIX_ROI_SIZE, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
+}
+
+void mtk_ethdr_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
+ struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
+ struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
+ struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
+ struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0804_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_081C_HDR_DM_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
+ HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0100_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_012C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0134_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0138_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_013C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0140_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0144_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0148_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_014C_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0150_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0154_GFX_DV_WP, ~0);
+ mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
+ mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
+ HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0204_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_0320_VDO_DM_BE, ~0);
+ mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
+ HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
+
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM0, ~0);
+ mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
+ MIX_FUNC_DCM1, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
+ MIX_DATAPATH_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L0_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L1_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L2_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
+ MIX_L3_SRC_SIZE, ~0);
+ mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, ~0);
+ mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
+ MIX_ROI_BGCLR, ~0);
+ mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
+ MIX_EN, ~0);
+}
+
+void mtk_ethdr_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
+ mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+ mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
+ mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
+ priv->top_regs, VDO1_CONFIG_SW1_RST_B,
+ HDR_ASYNC_RESET_BIT);
+ mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
+ VDO1_CONFIG_SW0_RST_B, BIT(29));
+}
+
+int mtk_ethdr_clk_enable(struct device *dev)
+{
+ int i, ret;
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ dev_err(dev,
+ "ethdr_clk prepare enable failed\n");
+ return ret;
+}
+
+void mtk_ethdr_clk_disable(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ int i;
+
+ clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
+}
+
+static int mtk_ethdr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ return 0;
+}
+
+static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
+{
+}
+
+static const struct component_ops mtk_ethdr_component_ops = {
+ .bind = mtk_ethdr_bind,
+ .unbind = mtk_ethdr_unbind,
+};
+
+static int mtk_ethdr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ethdr *priv;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ for (i = 0; i < ETHDR_ID_MAX; i++) {
+ priv->ethdr_comp[i].dev = dev;
+ priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev,
+ &priv->ethdr_comp[i].cmdq_base, i);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+ dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
+ priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
+ }
+
+ for (i = 0; i < ETHDR_CLK_NUM; i++)
+ priv->ethdr_clk[i].id = ethdr_clk_str[i];
+ ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_ethdr_component_ops);
+ if (ret)
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ dev_info(dev, "%s-\n", __func__);
+
+ return ret;
+}
+
+static int mtk_ethdr_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_ethdr_component_ops);
+ return 0;
+}
+
+static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-ethdr"},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
+
+struct platform_driver mtk_ethdr_driver = {
+ .probe = mtk_ethdr_probe,
+ .remove = mtk_ethdr_remove,
+ .driver = {
+ .name = "mediatek-disp-ethdr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_ethdr_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
new file mode 100644
index 000000000000..c8fc0581a632
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_DISP_ETHDR_H__
+#define __MTK_DISP_ETHDR_H__
+
+#include <linux/uaccess.h>
+#include <drm/mediatek_drm.h>
+
+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+#endif
+
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
Two RDMAs merge into one layer, so this module support 4
layers. The four layers are blending at the EHTDR module next to it.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
10 files changed, 1453 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fcce08710cef..70b53487ab0c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_ethdr.o
+ mtk_ethdr.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7227ffbc3eae..f5d35007b84d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
+
int mtk_ethdr_clk_enable(struct device *dev);
void mtk_ethdr_clk_disable(struct device *dev);
void mtk_ethdr_config(struct device *dev, unsigned int w,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..8ec80e1887e0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_ethdr.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
+#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
+#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
+#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ struct cmdq_client_reg top_cmdq_base;
+ void __iomem *top_regs;
+ const struct pseudo_ovl_data *data;
+ struct device *next_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static const unsigned int merge_async_offset[] = {
+ VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
+};
+
+static const unsigned int merge_async_reset_bit[] = {
+ BIT(25), BIT(26), BIT(27), BIT(28)};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ break;
+ case 18:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
+ break;
+ default:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
+ break;
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, ~0);
+}
+
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ return pseudo_ovl->data->layer_nr;
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
+ &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
+ merge_async_offset[idx], ~0);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
+ mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
+ &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
+
+ pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ return 0;
+}
+
+static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
+ .bind = mtk_disp_pseudo_ovl_bind,
+ .unbind = mtk_disp_pseudo_ovl_unbind,
+};
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
+ if (ret != 0) {
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
+ }
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3fa86f12feb4..64cbb9e1cc83 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_pseudo_ovl_clk_enable,
+ .clk_disable = mtk_pseudo_ovl_clk_disable,
+ .config = mtk_pseudo_ovl_config,
+ .start = mtk_pseudo_ovl_start,
+ .stop = mtk_pseudo_ovl_stop,
+ .layer_nr = mtk_pseudo_ovl_layer_nr,
+ .layer_config = mtk_pseudo_ovl_layer_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ethdr = {
.clk_enable = mtk_ethdr_clk_enable,
.clk_disable = mtk_ethdr_clk_disable,
@@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
return 0;
}
+struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
+{
+ struct mtk_drm_private *private = drm->dev_private;
+ const enum mtk_ddp_comp_id *path;
+ unsigned int path_len = 0;
+ int i;
+
+ if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
+ private->data->main_len,
+ private->ddp_comp)) {
+ path_len = private->data->main_len;
+ path = private->data->main_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
+ private->data->ext_len,
+ private->ddp_comp)) {
+ path_len = private->data->ext_len;
+ path = private->data->ext_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
+ private->data->third_len,
+ private->ddp_comp)) {
+ path_len = private->data->third_len;
+ path = private->data->third_path;
+ }
+
+ if (!path_len)
+ return NULL;
+
+ for (i = 0U; i < path_len; i++)
+ if (dev == private->ddp_comp[path[i]].dev)
+ break;
+
+ if (i < (path_len - 1))
+ return private->ddp_comp[path[i + 1]].dev;
+ else
+ return NULL;
+}
+
int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id)
{
@@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index f55efba6e744..ec84dc258124 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DSC,
MTK_DISP_MERGE,
MTK_DISP_ETHDR,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
@@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
struct device *dev);
+struct device *mtk_drm_find_next_comp(struct drm_device *drm,
+ struct device *dev);
int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ace958a34bb5..ddc26160dea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ .compatible = "mediatek,mt8195-disp-ethdr",
.data = (void *)MTK_DISP_ETHDR },
{ }
@@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_disp_pseudo_ovl_driver,
&mtk_ethdr_driver,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..fc03cfda7601 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_disp_pseudo_ovl_driver;
extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
Two RDMAs merge into one layer, so this module support 4
layers. The four layers are blending at the EHTDR module next to it.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
10 files changed, 1453 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fcce08710cef..70b53487ab0c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_ethdr.o
+ mtk_ethdr.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7227ffbc3eae..f5d35007b84d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
+
int mtk_ethdr_clk_enable(struct device *dev);
void mtk_ethdr_clk_disable(struct device *dev);
void mtk_ethdr_config(struct device *dev, unsigned int w,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..8ec80e1887e0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_ethdr.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
+#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
+#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
+#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ struct cmdq_client_reg top_cmdq_base;
+ void __iomem *top_regs;
+ const struct pseudo_ovl_data *data;
+ struct device *next_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static const unsigned int merge_async_offset[] = {
+ VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
+};
+
+static const unsigned int merge_async_reset_bit[] = {
+ BIT(25), BIT(26), BIT(27), BIT(28)};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ break;
+ case 18:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
+ break;
+ default:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
+ break;
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, ~0);
+}
+
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ return pseudo_ovl->data->layer_nr;
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
+ &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
+ merge_async_offset[idx], ~0);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
+ mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
+ &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
+
+ pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ return 0;
+}
+
+static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
+ .bind = mtk_disp_pseudo_ovl_bind,
+ .unbind = mtk_disp_pseudo_ovl_unbind,
+};
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
+ if (ret != 0) {
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
+ }
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3fa86f12feb4..64cbb9e1cc83 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_pseudo_ovl_clk_enable,
+ .clk_disable = mtk_pseudo_ovl_clk_disable,
+ .config = mtk_pseudo_ovl_config,
+ .start = mtk_pseudo_ovl_start,
+ .stop = mtk_pseudo_ovl_stop,
+ .layer_nr = mtk_pseudo_ovl_layer_nr,
+ .layer_config = mtk_pseudo_ovl_layer_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ethdr = {
.clk_enable = mtk_ethdr_clk_enable,
.clk_disable = mtk_ethdr_clk_disable,
@@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
return 0;
}
+struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
+{
+ struct mtk_drm_private *private = drm->dev_private;
+ const enum mtk_ddp_comp_id *path;
+ unsigned int path_len = 0;
+ int i;
+
+ if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
+ private->data->main_len,
+ private->ddp_comp)) {
+ path_len = private->data->main_len;
+ path = private->data->main_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
+ private->data->ext_len,
+ private->ddp_comp)) {
+ path_len = private->data->ext_len;
+ path = private->data->ext_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
+ private->data->third_len,
+ private->ddp_comp)) {
+ path_len = private->data->third_len;
+ path = private->data->third_path;
+ }
+
+ if (!path_len)
+ return NULL;
+
+ for (i = 0U; i < path_len; i++)
+ if (dev == private->ddp_comp[path[i]].dev)
+ break;
+
+ if (i < (path_len - 1))
+ return private->ddp_comp[path[i + 1]].dev;
+ else
+ return NULL;
+}
+
int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id)
{
@@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index f55efba6e744..ec84dc258124 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DSC,
MTK_DISP_MERGE,
MTK_DISP_ETHDR,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
@@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
struct device *dev);
+struct device *mtk_drm_find_next_comp(struct drm_device *drm,
+ struct device *dev);
int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ace958a34bb5..ddc26160dea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ .compatible = "mediatek,mt8195-disp-ethdr",
.data = (void *)MTK_DISP_ETHDR },
{ }
@@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_disp_pseudo_ovl_driver,
&mtk_ethdr_driver,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..fc03cfda7601 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_disp_pseudo_ovl_driver;
extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add pseudo ovl module files:
Pseudo ovl is an encapsulated module and designed for simplified
DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
Two RDMAs merge into one layer, so this module support 4
layers. The four layers are blending at the EHTDR module next to it.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
.../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
10 files changed, 1453 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index fcce08710cef..70b53487ab0c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_drm_plane.o \
mtk_dsi.o \
mtk_dpi.o \
- mtk_ethdr.o
+ mtk_ethdr.o \
+ mtk_disp_pseudo_ovl.o \
+ mtk_mdp_rdma.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7227ffbc3eae..f5d35007b84d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_rdma_disable_vblank(struct device *dev);
+int mtk_pseudo_ovl_clk_enable(struct device *dev);
+void mtk_pseudo_ovl_clk_disable(struct device *dev);
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_pseudo_ovl_start(struct device *dev);
+void mtk_pseudo_ovl_stop(struct device *dev);
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
+
int mtk_ethdr_clk_enable(struct device *dev);
void mtk_ethdr_clk_disable(struct device *dev);
void mtk_ethdr_config(struct device *dev, unsigned int w,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
new file mode 100644
index 000000000000..8ec80e1887e0
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_mdp_rdma.h"
+#include "mtk_ethdr.h"
+
+#define DISP_MERGE_ENABLE 0x0
+ #define MERGE_ENABLE BIT(0)
+#define DISP_MERGE_CFG_0 0x10
+#define DISP_MERGE_CFG_1 0x14
+#define DISP_MERGE_CFG_4 0x20
+#define DISP_MERGE_CFG_5 0x24
+#define DISP_MERGE_CFG_10 0x38
+ #define CFG_10_NO_SWAP 0
+#define DISP_MERGE_CFG_12 0x40
+ #define CFG12_10_10_1PI_2PO_BUF_MODE 6
+ #define CFG12_11_10_1PI_2PO_MERGE 18
+#define DISP_MERGE_CFG_24 0x70
+#define DISP_MERGE_CFG_25 0x74
+#define DISP_MERGE_CFG_26 0x78
+#define DISP_MERGE_CFG_27 0x7c
+#define DISP_MERGE_MUTE_0 0xf00
+
+#define VDO1_CONFIG_SW0_RST_B 0x1d0
+#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
+#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
+#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
+#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
+
+#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
+
+enum mtk_pseudo_ovl_comp_type {
+ PSEUDO_OVL_TYPE_RDMA = 0,
+ PSEUDO_OVL_TYPE_MERGE,
+ PSEUDO_OVL_TYPE_NUM,
+};
+
+enum mtk_pseudo_ovl_comp_id {
+ PSEUDO_OVL_RDMA_BASE = 0,
+ PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
+ PSEUDO_OVL_MDP_RDMA1,
+ PSEUDO_OVL_MDP_RDMA2,
+ PSEUDO_OVL_MDP_RDMA3,
+ PSEUDO_OVL_MDP_RDMA4,
+ PSEUDO_OVL_MDP_RDMA5,
+ PSEUDO_OVL_MDP_RDMA6,
+ PSEUDO_OVL_MDP_RDMA7,
+ PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
+ PSEUDO_OVL_MERGE1,
+ PSEUDO_OVL_MERGE2,
+ PSEUDO_OVL_MERGE3,
+ PSEUDO_OVL_ID_MAX
+};
+
+struct pseudo_ovl_data {
+ unsigned int layer_nr;
+ struct mtk_mdp_rdma_fifo fifo;
+};
+
+struct pseudo_ovl_comp_match {
+ enum mtk_pseudo_ovl_comp_type type;
+ int alias_id;
+};
+
+struct pseudo_ovl_merge_config {
+ unsigned int fmt;
+ unsigned int merge_mode;
+ unsigned int in_w[2];
+ unsigned int out_w[2];
+ unsigned int in_h;
+};
+
+struct mtk_pseudo_ovl_comp {
+ struct device *dev;
+ struct clk *clks[2];
+ struct cmdq_client_reg cmdq_base;
+ void __iomem *regs;
+};
+
+struct mtk_disp_pseudo_ovl {
+ struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
+ struct cmdq_client_reg top_cmdq_base;
+ void __iomem *top_regs;
+ const struct pseudo_ovl_data *data;
+ struct device *next_dev;
+};
+
+static const char * const pseudo_ovl_comp_str[] = {
+ "PSEUDO_OVL_MDP_RDMA0",
+ "PSEUDO_OVL_MDP_RDMA1",
+ "PSEUDO_OVL_MDP_RDMA2",
+ "PSEUDO_OVL_MDP_RDMA3",
+ "PSEUDO_OVL_MDP_RDMA4",
+ "PSEUDO_OVL_MDP_RDMA5",
+ "PSEUDO_OVL_MDP_RDMA6",
+ "PSEUDO_OVL_MDP_RDMA7",
+ "PSEUDO_OVL_MERGE0",
+ "PSEUDO_OVL_MERGE1",
+ "PSEUDO_OVL_MERGE2",
+ "PSEUDO_OVL_MERGE3",
+ "PSEUDO_OVL_ID_MAX"
+};
+
+static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
+ [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
+ [PSEUDO_OVL_TYPE_MERGE] = "merge",
+};
+
+static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
+ [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
+ [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
+ [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
+ [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
+ [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
+ [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
+ [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
+ [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
+ [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
+ [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
+ [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
+ [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
+};
+
+static const unsigned int merge_async_offset[] = {
+ VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
+ VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
+};
+
+static const unsigned int merge_async_reset_bit[] = {
+ BIT(25), BIT(26), BIT(27), BIT(28)};
+
+static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
+ struct cmdq_pkt *handle)
+{
+ struct mtk_pseudo_ovl_comp *rdma = NULL;
+ const struct pseudo_ovl_data *data = pseudo_ovl->data;
+ const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
+ int i;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
+ rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
+ mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
+ }
+
+ return 0;
+}
+
+static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
+ struct pseudo_ovl_merge_config *merge_cfg,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ switch (merge_cfg->merge_mode) {
+ case 6:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ break;
+ case 18:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
+ break;
+ default:
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
+ &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
+ break;
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_12, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
+ comp->regs, DISP_MERGE_CFG_10, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
+ DISP_MERGE_ENABLE, ~0);
+}
+
+unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ return pseudo_ovl->data->layer_nr;
+}
+
+void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ struct pseudo_ovl_merge_config merge_cfg = {0};
+ struct mtk_mdp_rdma_cfg rdma_config = {0};
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ const struct drm_format_info *fmt_info = drm_format_info(pending->format);
+ bool use_dual_pipe = false;
+
+ dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
+ pending->enable, pending->format);
+ dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
+ pending->addr, (pending->pitch / fmt_info->cpp[0]),
+ pending->x, pending->y, pending->width, pending->height);
+
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
+
+ if (!pending->enable) {
+ mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ return;
+ }
+
+ if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
+ use_dual_pipe = true;
+
+ merge_cfg.out_w[0] = pending->width;
+ merge_cfg.in_h = pending->height;
+ merge_cfg.fmt = pending->format;
+ if (use_dual_pipe) {
+ merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
+ merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
+ merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
+ } else {
+ merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
+ merge_cfg.in_w[0] = pending->width;
+ }
+
+ mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
+ mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
+ &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
+ merge_async_offset[idx], ~0);
+
+ rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
+ rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
+ rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
+ rdma_config.encode_type = RDMA_ENCODE_NONE;
+ rdma_config.block_size = RDMA_BLOCK_NONE;
+ rdma_config.width = merge_cfg.in_w[0];
+ rdma_config.height = pending->height;
+ rdma_config.addr0 = pending->addr;
+ rdma_config.fmt = pending->format;
+ mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
+
+ rdma_config.x_left = merge_cfg.in_w[0];
+ rdma_config.width = merge_cfg.in_w[1];
+ mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_ENABLE, 0x1);
+ mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
+ DISP_MERGE_MUTE_0, 0x1);
+
+ mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
+ if (use_dual_pipe)
+ mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+ else
+ mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
+
+ mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
+ mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+
+ dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
+ mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
+}
+
+void mtk_pseudo_ovl_start(struct device *dev)
+{
+}
+
+void mtk_pseudo_ovl_stop(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *rdma_l;
+ struct mtk_pseudo_ovl_comp *rdma_r;
+ struct mtk_pseudo_ovl_comp *merge;
+ unsigned int reg;
+ u32 i;
+
+ for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
+ rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
+ rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
+ merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
+
+ mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
+ mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
+
+ reg = readl(merge->regs + DISP_MERGE_ENABLE);
+ reg = reg & ~MERGE_ENABLE;
+ writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
+
+ mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
+ &pseudo_ovl->top_cmdq_base,
+ pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
+ merge_async_reset_bit[i]);
+ }
+}
+
+int mtk_pseudo_ovl_clk_enable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ /* Need to power on for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_get_sync(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power on, err %d-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+
+ ret = clk_prepare_enable(comp->clks[j]);
+ if (ret)
+ dev_err(dev,
+ "Failed to enable clock %d, err %d-%s\n",
+ i, ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+
+ return ret;
+}
+
+void mtk_pseudo_ovl_clk_disable(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct mtk_pseudo_ovl_comp *comp;
+ int ret;
+ int i;
+ int j;
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
+ comp = &pseudo_ovl->pseudo_ovl_comp[i];
+ if (!comp->dev)
+ continue;
+
+ for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
+ if (IS_ERR(comp->clks[j]))
+ break;
+ clk_disable_unprepare(comp->clks[j]);
+ }
+
+ /* Need to power off for private rdma devices */
+ if (i < PSEUDO_OVL_MERGE_BASE) {
+ ret = pm_runtime_put(comp->dev);
+ if (ret < 0)
+ dev_err(dev,
+ "Failed to power off, err-%s\n",
+ ret, pseudo_ovl_comp_str[i]);
+ }
+ }
+}
+
+static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ struct mtk_drm_private *drm_private = drm_dev->dev_private;
+ struct device *mmsys_dev = drm_private->mmsys_dev;
+
+ pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
+
+ pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ return 0;
+}
+
+static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
+ .bind = mtk_disp_pseudo_ovl_bind,
+ .unbind = mtk_disp_pseudo_ovl_unbind,
+};
+
+static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
+ enum mtk_pseudo_ovl_comp_type type)
+{
+ int alias_id = of_alias_get_id(node, private_comp_stem[type]);
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
+ if (comp_matches[i].type == type &&
+ comp_matches[i].alias_id == alias_id)
+ return i;
+
+ dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
+ return -EINVAL;
+}
+
+static int private_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_pseudo_ovl_comp *comp,
+ enum mtk_pseudo_ovl_comp_id id)
+{
+ struct platform_device *comp_pdev;
+ int ret;
+ int i;
+
+ if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
+ dev_err(dev, "Invalid component id %d\n", id);
+ return -EINVAL;
+ }
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "can't find platform device of node:%s\n",
+ node->name);
+ return -ENODEV;
+ }
+ comp->dev = &comp_pdev->dev;
+ comp->regs = of_iomap(node, 0);
+
+ for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
+ comp->clks[i] = of_clk_get(node, i);
+ if (IS_ERR(comp->clks[i]))
+ break;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
+ if (ret)
+ dev_info(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ if (id < PSEUDO_OVL_MERGE_BASE)
+ pm_runtime_enable(comp->dev);
+
+ dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
+ {
+ .compatible = "mediatek,mt8195-vdo1-rdma",
+ .data = (void *)PSEUDO_OVL_TYPE_RDMA,
+ }, {
+ .compatible = "mediatek,mt8195-vdo1-merge",
+ .data = (void *)PSEUDO_OVL_TYPE_MERGE,
+ },
+ {},
+};
+
+static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
+ .probe = mtk_disp_pseudo_ovl_comp_probe,
+ .remove = mtk_disp_pseudo_ovl_comp_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl-comp",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
+ },
+};
+module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
+
+static int pseudo_ovl_comp_init(struct device *dev)
+{
+ struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
+ struct device_node *node, *parent;
+ int i, ret;
+
+ parent = dev->of_node->parent;
+
+ for_each_child_of_node(parent, node) {
+ const struct of_device_id *of_id;
+ enum mtk_pseudo_ovl_comp_type type;
+ struct mtk_pseudo_ovl_comp *comp;
+ int id;
+
+ of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
+ if (!of_id)
+ continue;
+
+ if (!of_device_is_available(node)) {
+ dev_info(dev, "Skipping disabled component %pOF\n",
+ node);
+ continue;
+ }
+
+ type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
+ id = pseudo_ovl_comp_get_id(dev, node, type);
+ if (id < 0) {
+ dev_warn(dev, "Skipping unknown component %pOF\n",
+ node);
+ continue;
+ }
+
+ ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *priv;
+ struct device *dev = &pdev->dev;
+ int ret;
+ int i;
+
+ dev_info(dev, "%s+\n", __func__);
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = pseudo_ovl_comp_init(dev);
+ if (ret) {
+ dev_notice(dev, "pseudo_ovl comp init fail\n");
+ return ret;
+ }
+
+ ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
+ if (ret != 0) {
+ dev_notice(dev, "Failed to add component: %d\n", ret);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
+ }
+ dev_info(dev, "%s-\n", __func__);
+ return ret;
+}
+
+static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
+{
+ struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
+
+ for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
+ pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
+
+ return 0;
+}
+
+static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
+ .layer_nr = 4,
+ .fifo.read_request_type = 7,
+ .fifo.command_div = 1,
+ .fifo.ext_preutra_en = 1,
+ .fifo.ultra_en = 0,
+ .fifo.pre_ultra_en = 1,
+ .fifo.ext_ultra_en = 1,
+ .fifo.extrd_arb_max_0 = 3,
+ .fifo.buf_resv_size_0 = 0,
+ .fifo.issue_req_th_0 = 0,
+ .fifo.ultra_h_con_0 = 156,
+ .fifo.ultra_l_con_0 = 104,
+};
+
+static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = &mt8195_pseudo_ovl_driver_data},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
+
+struct platform_driver mtk_disp_pseudo_ovl_driver = {
+ .probe = mtk_disp_pseudo_ovl_probe,
+ .remove = mtk_disp_pseudo_ovl_remove,
+ .driver = {
+ .name = "mediatek-disp-pseudo-ovl",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 3fa86f12feb4..64cbb9e1cc83 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.start = mtk_ufoe_start,
};
+static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
+ .clk_enable = mtk_pseudo_ovl_clk_enable,
+ .clk_disable = mtk_pseudo_ovl_clk_disable,
+ .config = mtk_pseudo_ovl_config,
+ .start = mtk_pseudo_ovl_start,
+ .stop = mtk_pseudo_ovl_stop,
+ .layer_nr = mtk_pseudo_ovl_layer_nr,
+ .layer_config = mtk_pseudo_ovl_layer_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ethdr = {
.clk_enable = mtk_ethdr_clk_enable,
.clk_disable = mtk_ethdr_clk_disable,
@@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_UFOE] = "ufoe",
[MTK_DSI] = "dsi",
[MTK_DPI] = "dpi",
+ [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
+ [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
@@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
return 0;
}
+struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
+{
+ struct mtk_drm_private *private = drm->dev_private;
+ const enum mtk_ddp_comp_id *path;
+ unsigned int path_len = 0;
+ int i;
+
+ if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
+ private->data->main_len,
+ private->ddp_comp)) {
+ path_len = private->data->main_len;
+ path = private->data->main_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
+ private->data->ext_len,
+ private->ddp_comp)) {
+ path_len = private->data->ext_len;
+ path = private->data->ext_path;
+ } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
+ private->data->third_len,
+ private->ddp_comp)) {
+ path_len = private->data->third_len;
+ path = private->data->third_path;
+ }
+
+ if (!path_len)
+ return NULL;
+
+ for (i = 0U; i < path_len; i++)
+ if (dev == private->ddp_comp[path[i]].dev)
+ break;
+
+ if (i < (path_len - 1))
+ return private->ddp_comp[path[i + 1]].dev;
+ else
+ return NULL;
+}
+
int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id)
{
@@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_PSEUDO_OVL ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index f55efba6e744..ec84dc258124 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DSC,
MTK_DISP_MERGE,
MTK_DISP_ETHDR,
+ MTK_DISP_PSEUDO_OVL,
MTK_DDP_COMP_TYPE_MAX,
};
@@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
struct device *dev);
+struct device *mtk_drm_find_next_comp(struct drm_device *drm,
+ struct device *dev);
int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
enum mtk_ddp_comp_id comp_id);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ace958a34bb5..ddc26160dea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
+ .data = (void *)MTK_DISP_PSEUDO_OVL },
{ .compatible = "mediatek,mt8195-disp-ethdr",
.data = (void *)MTK_DISP_ETHDR },
{ }
@@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_PSEUDO_OVL ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
+ &mtk_disp_pseudo_ovl_driver,
&mtk_ethdr_driver,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c87ebb5309d0..fc03cfda7601 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
+extern struct platform_driver mtk_disp_pseudo_ovl_driver;
extern struct platform_driver mtk_ethdr_driver;
#endif /* MTK_DRM_DRV_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
new file mode 100644
index 000000000000..81d3cc4872eb
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <drm/drm_fourcc.h>
+#include "mtk_drm_drv.h"
+#include "mtk_mdp_reg_rdma.h"
+#include "mtk_mdp_rdma.h"
+
+#define RDMA_INPUT_SWAP BIT(14)
+#define RDMA_INPUT_10BIT BIT(18)
+#define IRQ_INT_EN_ALL \
+ (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
+ REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
+ REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
+
+static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 2 * width;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 3 * width;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return 4 * width;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 2 * width;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1 * width;
+ }
+}
+
+static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 4 * width;
+ }
+}
+
+static unsigned int rdma_get_block_h(unsigned int mode)
+{
+ switch (mode) {
+ default:
+ return 0;
+ case RDMA_BLOCK_8x8:
+ case RDMA_BLOCK_16x8:
+ case RDMA_BLOCK_32x8:
+ return 8;
+ case RDMA_BLOCK_8x16:
+ case RDMA_BLOCK_16x16:
+ case RDMA_BLOCK_32x16:
+ return 16;
+ case RDMA_BLOCK_8x32:
+ case RDMA_BLOCK_16x32:
+ case RDMA_BLOCK_32x32:
+ return 32;
+ }
+}
+
+static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 1;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ return 16;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_BGR888:
+ return 24;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return 32;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YUYV:
+ return 16;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 8;
+ }
+}
+
+static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ return 0;
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV21:
+ return 16;
+ }
+}
+
+static bool with_alpha(uint32_t format)
+{
+ const struct drm_format_info *fmt_info = drm_format_info(format);
+
+ return fmt_info->has_alpha;
+}
+
+static unsigned int rdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return RDMA_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return RDMA_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888;
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return RDMA_INPUT_FORMAT_RGBA8888;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
+ case DRM_FORMAT_ABGR2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_ARGB2101010:
+ return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_RGBA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
+ RDMA_INPUT_10BIT;
+ case DRM_FORMAT_BGRA1010102:
+ return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
+ case DRM_FORMAT_UYVY:
+ return RDMA_INPUT_FORMAT_UYVY;
+ case DRM_FORMAT_YUYV:
+ return RDMA_INPUT_FORMAT_YUY2;
+ }
+}
+
+void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int inten = IRQ_INT_EN_ALL;
+
+ mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+}
+
+void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
+ base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
+ MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
+ mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
+}
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo)
+{
+ int reg;
+ int reg_val;
+ int reg_mask;
+
+ reg = MDP_RDMA_GMCIF_CON;
+ reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
+ REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
+ REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
+ REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
+ REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
+ REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
+ reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
+ REG_FLD_MASK(FLD_COMMAND_DIV) |
+ REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
+ REG_FLD_MASK(FLD_ULTRA_EN) |
+ REG_FLD_MASK(PRE_ULTRA_EN) |
+ REG_FLD_MASK(FLD_EXT_ULTRA_EN);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMA_CON_0;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_L_CON_0;
+ reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
+ reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_1;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_2;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_DMABUF_CON_3;
+ reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
+ REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
+ REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
+ REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
+ REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_UTRA_H_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+
+ reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
+ reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
+ reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
+ mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
+}
+
+void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base)
+{
+ unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
+ unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
+ unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
+ unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
+ unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
+ unsigned int block_h = rdma_get_block_h(cfg->block_size);
+ unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
+ unsigned int y_start_line = 0;
+ unsigned int offset_y = 0;
+ unsigned int offset_u = 0;
+ unsigned int offset_v = 0;
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_UNIFORM_CONFIG));
+ mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
+ base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
+ REG_FLD_MASK(FLD_SRC_FORMAT) |
+ REG_FLD_MASK(FLD_BIT_NUMBER));
+
+ if (!cfg->csc_enable && with_alpha(cfg->fmt))
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+ else
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
+ cmdq_base, base, MDP_RDMA_SRC_CON,
+ REG_FLD_MASK(FLD_OUTPUT_ARGB));
+
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
+ mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
+ MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
+
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
+ MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_MF_BKGD_WB));
+ mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
+ MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
+ REG_FLD_MASK(FLD_SF_BKGD_WB));
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_MF_BKGD_WP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
+ REG_FLD_MASK(FLD_BKGD_HP));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ } else {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
+ cmdq_base, base, MDP_RDMA_COMP_CON,
+ REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
+ base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
+ base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_TRANS_EN));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
+ cmdq_base, base, MDP_RDMA_TRANSFORM_0,
+ REG_FLD_MASK(FLD_INT_MATRIX_SEL));
+
+ if (cfg->block_size == RDMA_BLOCK_NONE) {
+ y_start_line = cfg->y_top;
+
+ offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
+ (y_start_line >> v_shift_uv) * src_pitch_uv;
+ } else {
+ offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
+ (cfg->y_top) * src_pitch_y;
+ offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
+ bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
+ }
+
+ if (cfg->encode_type == RDMA_ENCODE_AFBC) {
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_WP));
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
+ REG_FLD_MASK(FLD_SRC_OFFSET_HP));
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
+ REG_FLD_MASK(FLD_SRC_OFFSET_0));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
+ REG_FLD_MASK(FLD_SRC_OFFSET_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
+ cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
+ REG_FLD_MASK(FLD_SRC_OFFSET_2));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
+ REG_FLD_MASK(FLD_MF_SRC_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_W));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
+ cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
+ REG_FLD_MASK(FLD_MF_CLIP_H));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_W_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
+ cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
+ REG_FLD_MASK(FLD_MF_OFFSET_H_1));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_LINE_THRESHOLD));
+ mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
+ cmdq_base, base, MDP_RDMA_TARGET_LINE,
+ REG_FLD_MASK(FLD_TARGET_LINE_EN));
+}
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
new file mode 100644
index 000000000000..c16bfb716610
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_MDP_RDMA_H__
+#define __MTK_MDP_RDMA_H__
+
+enum rdma_format {
+ RDMA_INPUT_FORMAT_RGB565 = 0,
+ RDMA_INPUT_FORMAT_RGB888 = 1,
+ RDMA_INPUT_FORMAT_RGBA8888 = 2,
+ RDMA_INPUT_FORMAT_ARGB8888 = 3,
+ RDMA_INPUT_FORMAT_UYVY = 4,
+ RDMA_INPUT_FORMAT_YUY2 = 5,
+ RDMA_INPUT_FORMAT_Y8 = 7,
+ RDMA_INPUT_FORMAT_YV12 = 8,
+ RDMA_INPUT_FORMAT_UYVY_3PL = 9,
+ RDMA_INPUT_FORMAT_NV12 = 12,
+ RDMA_INPUT_FORMAT_UYVY_2PL = 13,
+ RDMA_INPUT_FORMAT_Y410 = 14
+};
+
+enum rdma_profile {
+ RDMA_CSC_RGB_TO_JPEG = 0,
+ RDMA_CSC_RGB_TO_FULL709 = 1,
+ RDMA_CSC_RGB_TO_BT601 = 2,
+ RDMA_CSC_RGB_TO_BT709 = 3,
+ RDMA_CSC_JPEG_TO_RGB = 4,
+ RDMA_CSC_FULL709_TO_RGB = 5,
+ RDMA_CSC_BT601_TO_RGB = 6,
+ RDMA_CSC_BT709_TO_RGB = 7,
+ RDMA_CSC_JPEG_TO_BT601 = 8,
+ RDMA_CSC_JPEG_TO_BT709 = 9,
+ RDMA_CSC_BT601_TO_JPEG = 10,
+ RDMA_CSC_BT709_TO_BT601 = 11,
+ RDMA_CSC_BT601_TO_BT709 = 12
+};
+
+enum rdma_encode {
+ RDMA_ENCODE_NONE = 0,
+ RDMA_ENCODE_AFBC = 1,
+ RDMA_ENCODE_HYFBC = 2,
+ RDMA_ENCODE_UFO_DCP = 3
+};
+
+enum rdma_block {
+ RDMA_BLOCK_NONE = 0,
+ RDMA_BLOCK_8x8 = 1,
+ RDMA_BLOCK_8x16 = 2,
+ RDMA_BLOCK_8x32 = 3,
+ RDMA_BLOCK_16x8 = 4,
+ RDMA_BLOCK_16x16 = 5,
+ RDMA_BLOCK_16x32 = 6,
+ RDMA_BLOCK_32x8 = 7,
+ RDMA_BLOCK_32x16 = 8,
+ RDMA_BLOCK_32x32 = 9
+};
+
+struct mtk_mdp_rdma_cfg {
+ enum rdma_encode encode_type;
+ enum rdma_block block_size;
+ enum rdma_profile profile;
+ unsigned int source_width;
+ unsigned int addr0;
+ unsigned int addr1;
+ unsigned int addr2;
+ unsigned int width;
+ unsigned int height;
+ unsigned int x_left;
+ unsigned int y_top;
+ bool csc_enable;
+ int fmt;
+};
+
+struct mtk_mdp_rdma_fifo {
+ int read_request_type;
+ int command_div;
+ int ext_preutra_en;
+ int ultra_en;
+ int pre_ultra_en;
+ int ext_ultra_en;
+ int extrd_arb_max_0;
+ int buf_resv_size_0;
+ int issue_req_th_0;
+ int ultra_h_con_0;
+ int ultra_l_con_0;
+};
+
+void mtk_mdp_rdma_start(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_stop(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+void mtk_mdp_rdma_fifo_config(void __iomem *base,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base,
+ const struct mtk_mdp_rdma_fifo *fifo);
+
+void mtk_mdp_rdma_config(void __iomem *base,
+ struct mtk_mdp_rdma_cfg *cfg,
+ struct cmdq_pkt *cmdq_pkt,
+ struct cmdq_client_reg *cmdq_base);
+
+#endif // __MTK_MDP_RDMA_H__
+
diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
new file mode 100644
index 000000000000..08abd9f39bd8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MDP_RDMA_REGS_H__
+#define __MDP_RDMA_REGS_H__
+
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
+#define MDP_RDMA_EN 0x000
+#define FLD_ROT_ENABLE REG_FLD(1, 0)
+
+#define MDP_RDMA_RESET 0x008
+
+#define MDP_RDMA_INTERRUPT_ENABLE 0x010
+#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
+#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
+#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
+
+#define MDP_RDMA_INTERRUPT_STATUS 0x018
+
+#define MDP_RDMA_CON 0x020
+#define FLD_OUTPUT_10B REG_FLD(1, 5)
+#define FLD_SIMPLE_MODE REG_FLD(1, 4)
+
+#define MDP_RDMA_GMCIF_CON 0x028
+#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
+#define PRE_ULTRA_EN REG_FLD(2, 16)
+#define FLD_ULTRA_EN REG_FLD(2, 12)
+#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
+#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
+#define FLD_COMMAND_DIV REG_FLD(1, 0)
+
+#define MDP_RDMA_SRC_CON 0x030
+#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
+#define FLD_BIT_NUMBER REG_FLD(2, 18)
+#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
+#define FLD_SWAP REG_FLD(1, 14)
+#define FLD_SRC_FORMAT REG_FLD(4, 0)
+
+#define MDP_RDMA_COMP_CON 0x038
+#define FLD_AFBC_EN REG_FLD(1, 22)
+#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
+#define FLD_UFBDC_EN REG_FLD(1, 12)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
+#define FLD_MF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
+#define FLD_MF_BKGD_WP REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_SRC_SIZE 0x070
+#define FLD_MF_SRC_H REG_FLD(15, 16)
+#define FLD_MF_SRC_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_CLIP_SIZE 0x078
+#define FLD_MF_CLIP_H REG_FLD(15, 16)
+#define FLD_MF_CLIP_W REG_FLD(15, 0)
+
+#define MDP_RDMA_MF_OFFSET_1 0x080
+#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
+#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
+
+#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
+#define FLD_SF_BKGD_WB REG_FLD(23, 0)
+
+#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
+#define FLD_BKGD_HP REG_FLD(23, 0)
+
+#define MDP_RDMA_TARGET_LINE 0x0a0
+#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
+#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_SRC_OFFSET_0 0x118
+#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_1 0x120
+#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_2 0x128
+#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_WP 0x148
+#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_OFFSET_HP 0x150
+#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
+
+#define MDP_RDMA_TRANSFORM_0 0x200
+#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
+#define FLD_TRANS_EN REG_FLD(1, 16)
+
+#define MDP_RDMA_DMA_CON_0 0x240
+#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
+#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
+
+#define MDP_RDMA_UTRA_H_CON_0 0x248
+#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_UTRA_L_CON_0 0x250
+#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_1 0x258
+#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
+#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
+
+#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
+#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_2 0x270
+#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_2 0x278
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
+#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
+
+#define MDP_RDMA_DMABUF_CON_3 0x288
+#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
+#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
+#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
+
+#define MDP_RDMA_UTRA_H_CON_3 0x290
+#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
+#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
+
+#define MDP_RDMA_SRC_BASE_0 0xf00
+#define FLD_SRC_BASE_0 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_1 0xf08
+#define FLD_SRC_BASE_1 REG_FLD(32, 0)
+
+#define MDP_RDMA_SRC_BASE_2 0xf10
+#define FLD_SRC_BASE_2 REG_FLD(32, 0)
+
+#endif /* __MDP_RDMA_REGS_H__ */
+
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add merge vblank support.
The vdosys1 go through the following component:
pseudo_ovl -> ethdr -> merge5 -> dp_intf1
The first comp is pseudo_ovl. This comp doesn't
have the whole CRTC timing vblank but only has vblank for each layer.
Merge5 comp gets all the mixed layers after the ETHDR module.
Use merge5 comp as the vblank source.
Change the mtk_drm_crtc_enable_vblank function: iterate over the path
comp from start to the end and find the first comp registered with vblank
function as the vblank source.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 ++++--
5 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f5d35007b84d..7f99ba525556 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -61,6 +61,10 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_merge_disable_vblank(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..6231087067e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -76,6 +76,8 @@
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+#define DISP_MERGE_CFG2_0 0x160
+#define DISP_MERGE_CFG2_2 0x168
struct mtk_merge_config_struct {
unsigned short width_right;
@@ -92,6 +94,9 @@ struct mtk_disp_merge {
void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
u32 fifo_en;
+ int irq;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
};
void mtk_merge_start(struct device *dev)
@@ -272,6 +277,44 @@ void mtk_merge_clk_disable(struct device *dev)
clk_disable_unprepare(priv->clk);
}
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ int irq_frame_done_en = BIT(16);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(irq_frame_done_en, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+void mtk_merge_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+static irqreturn_t mtk_disp_merge_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_disp_merge *priv = dev_id;
+
+ writel(0x1, priv->regs + DISP_MERGE_CFG2_2);
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_2);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
static int mtk_disp_merge_bind(struct device *dev, struct device *master,
void *data)
{
@@ -337,6 +380,19 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_disp_merge_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..f3addc200c97 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -501,19 +501,28 @@ static void mtk_crtc_ddp_irq(void *data)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
-
- mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
+ struct mtk_ddp_comp *comp;
+ int i;
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base))
+ break;
+ }
return 0;
}
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp;
+ int i;
- mtk_ddp_comp_disable_vblank(comp);
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_disable_vblank(comp))
+ break;
+ }
}
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 64cbb9e1cc83..5ecb16c2a8ad 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -347,6 +347,8 @@ static const struct mtk_ddp_comp_funcs ddp_merge = {
.start = mtk_merge_start,
.stop = mtk_merge_stop,
.config = mtk_merge_config,
+ .enable_vblank = mtk_merge_enable_vblank,
+ .disable_vblank = mtk_merge_disable_vblank,
};
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ec84dc258124..b2f01c93a268 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -114,18 +114,24 @@ static inline void mtk_ddp_comp_stop(struct mtk_ddp_comp *comp)
comp->funcs->stop(comp->dev);
}
-static inline void mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
void (*vblank_cb)(void *),
void *vblank_cb_data)
{
- if (comp->funcs && comp->funcs->enable_vblank)
+ if (comp->funcs && comp->funcs->enable_vblank) {
comp->funcs->enable_vblank(comp->dev, vblank_cb, vblank_cb_data);
+ return true;
+ }
+ return false;
}
-static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
+static inline bool mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
{
- if (comp->funcs && comp->funcs->disable_vblank)
+ if (comp->funcs && comp->funcs->disable_vblank) {
comp->funcs->disable_vblank(comp->dev);
+ return true;
+ }
+ return false;
}
static inline
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add merge vblank support.
The vdosys1 go through the following component:
pseudo_ovl -> ethdr -> merge5 -> dp_intf1
The first comp is pseudo_ovl. This comp doesn't
have the whole CRTC timing vblank but only has vblank for each layer.
Merge5 comp gets all the mixed layers after the ETHDR module.
Use merge5 comp as the vblank source.
Change the mtk_drm_crtc_enable_vblank function: iterate over the path
comp from start to the end and find the first comp registered with vblank
function as the vblank source.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 ++++--
5 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f5d35007b84d..7f99ba525556 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -61,6 +61,10 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_merge_disable_vblank(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..6231087067e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -76,6 +76,8 @@
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+#define DISP_MERGE_CFG2_0 0x160
+#define DISP_MERGE_CFG2_2 0x168
struct mtk_merge_config_struct {
unsigned short width_right;
@@ -92,6 +94,9 @@ struct mtk_disp_merge {
void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
u32 fifo_en;
+ int irq;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
};
void mtk_merge_start(struct device *dev)
@@ -272,6 +277,44 @@ void mtk_merge_clk_disable(struct device *dev)
clk_disable_unprepare(priv->clk);
}
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ int irq_frame_done_en = BIT(16);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(irq_frame_done_en, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+void mtk_merge_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+static irqreturn_t mtk_disp_merge_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_disp_merge *priv = dev_id;
+
+ writel(0x1, priv->regs + DISP_MERGE_CFG2_2);
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_2);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
static int mtk_disp_merge_bind(struct device *dev, struct device *master,
void *data)
{
@@ -337,6 +380,19 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_disp_merge_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..f3addc200c97 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -501,19 +501,28 @@ static void mtk_crtc_ddp_irq(void *data)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
-
- mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
+ struct mtk_ddp_comp *comp;
+ int i;
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base))
+ break;
+ }
return 0;
}
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp;
+ int i;
- mtk_ddp_comp_disable_vblank(comp);
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_disable_vblank(comp))
+ break;
+ }
}
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 64cbb9e1cc83..5ecb16c2a8ad 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -347,6 +347,8 @@ static const struct mtk_ddp_comp_funcs ddp_merge = {
.start = mtk_merge_start,
.stop = mtk_merge_stop,
.config = mtk_merge_config,
+ .enable_vblank = mtk_merge_enable_vblank,
+ .disable_vblank = mtk_merge_disable_vblank,
};
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ec84dc258124..b2f01c93a268 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -114,18 +114,24 @@ static inline void mtk_ddp_comp_stop(struct mtk_ddp_comp *comp)
comp->funcs->stop(comp->dev);
}
-static inline void mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
void (*vblank_cb)(void *),
void *vblank_cb_data)
{
- if (comp->funcs && comp->funcs->enable_vblank)
+ if (comp->funcs && comp->funcs->enable_vblank) {
comp->funcs->enable_vblank(comp->dev, vblank_cb, vblank_cb_data);
+ return true;
+ }
+ return false;
}
-static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
+static inline bool mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
{
- if (comp->funcs && comp->funcs->disable_vblank)
+ if (comp->funcs && comp->funcs->disable_vblank) {
comp->funcs->disable_vblank(comp->dev);
+ return true;
+ }
+ return false;
}
static inline
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 08/10] drm/mediatek: add merge vblank support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add merge vblank support.
The vdosys1 go through the following component:
pseudo_ovl -> ethdr -> merge5 -> dp_intf1
The first comp is pseudo_ovl. This comp doesn't
have the whole CRTC timing vblank but only has vblank for each layer.
Merge5 comp gets all the mixed layers after the ETHDR module.
Use merge5 comp as the vblank source.
Change the mtk_drm_crtc_enable_vblank function: iterate over the path
comp from start to the end and find the first comp registered with vblank
function as the vblank source.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 56 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 19 +++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 14 ++++--
5 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index f5d35007b84d..7f99ba525556 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -61,6 +61,10 @@ void mtk_merge_config(struct device *dev, unsigned int width,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void mtk_merge_start(struct device *dev);
void mtk_merge_stop(struct device *dev);
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_merge_disable_vblank(struct device *dev);
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
index 768c282d2d63..6231087067e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -76,6 +76,8 @@
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+#define DISP_MERGE_CFG2_0 0x160
+#define DISP_MERGE_CFG2_2 0x168
struct mtk_merge_config_struct {
unsigned short width_right;
@@ -92,6 +94,9 @@ struct mtk_disp_merge {
void __iomem *regs;
struct cmdq_client_reg cmdq_reg;
u32 fifo_en;
+ int irq;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
};
void mtk_merge_start(struct device *dev)
@@ -272,6 +277,44 @@ void mtk_merge_clk_disable(struct device *dev)
clk_disable_unprepare(priv->clk);
}
+void mtk_merge_enable_vblank(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ int irq_frame_done_en = BIT(16);
+
+ priv->vblank_cb = vblank_cb;
+ priv->vblank_cb_data = vblank_cb_data;
+
+ writel(irq_frame_done_en, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+void mtk_merge_disable_vblank(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ priv->vblank_cb = NULL;
+ priv->vblank_cb_data = NULL;
+
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_0);
+}
+
+static irqreturn_t mtk_disp_merge_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_disp_merge *priv = dev_id;
+
+ writel(0x1, priv->regs + DISP_MERGE_CFG2_2);
+ writel(0x0, priv->regs + DISP_MERGE_CFG2_2);
+
+ if (!priv->vblank_cb)
+ return IRQ_NONE;
+
+ priv->vblank_cb(priv->vblank_cb_data);
+
+ return IRQ_HANDLED;
+}
+
static int mtk_disp_merge_bind(struct device *dev, struct device *master,
void *data)
{
@@ -337,6 +380,19 @@ static int mtk_disp_merge_probe(struct platform_device *pdev)
priv->fifo_en = of_property_read_bool(dev->of_node,
"mediatek,merge-fifo-en");
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ priv->irq = 0;
+
+ if (priv->irq) {
+ ret = devm_request_irq(dev, priv->irq, mtk_disp_merge_irq_handler,
+ IRQF_TRIGGER_NONE, dev_name(dev), priv);
+ if (ret < 0) {
+ dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
+ return ret;
+ }
+ }
+
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_merge_component_ops);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 40df2c823187..f3addc200c97 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -501,19 +501,28 @@ static void mtk_crtc_ddp_irq(void *data)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
-
- mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base);
+ struct mtk_ddp_comp *comp;
+ int i;
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base))
+ break;
+ }
return 0;
}
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp;
+ int i;
- mtk_ddp_comp_disable_vblank(comp);
+ for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ comp = mtk_crtc->ddp_comp[i];
+ if (mtk_ddp_comp_disable_vblank(comp))
+ break;
+ }
}
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 64cbb9e1cc83..5ecb16c2a8ad 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -347,6 +347,8 @@ static const struct mtk_ddp_comp_funcs ddp_merge = {
.start = mtk_merge_start,
.stop = mtk_merge_stop,
.config = mtk_merge_config,
+ .enable_vblank = mtk_merge_enable_vblank,
+ .disable_vblank = mtk_merge_disable_vblank,
};
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ec84dc258124..b2f01c93a268 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -114,18 +114,24 @@ static inline void mtk_ddp_comp_stop(struct mtk_ddp_comp *comp)
comp->funcs->stop(comp->dev);
}
-static inline void mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp,
void (*vblank_cb)(void *),
void *vblank_cb_data)
{
- if (comp->funcs && comp->funcs->enable_vblank)
+ if (comp->funcs && comp->funcs->enable_vblank) {
comp->funcs->enable_vblank(comp->dev, vblank_cb, vblank_cb_data);
+ return true;
+ }
+ return false;
}
-static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
+static inline bool mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp)
{
- if (comp->funcs && comp->funcs->disable_vblank)
+ if (comp->funcs && comp->funcs->disable_vblank) {
comp->funcs->disable_vblank(comp->dev);
+ return true;
+ }
+ return false;
}
static inline
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..0cc52bd1cfcd 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -68,6 +68,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..0cc52bd1cfcd 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -68,6 +68,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data.
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
MT8195 support two display system: vdosys0 and vdosys1.
The two mmsys will bring up two drm drivers, only one drm
driver register as the drm device. Use the new mtk_mmsys struct
member for the two mmsys synchronization.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 9e31aad6c5c8..0cc52bd1cfcd 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -68,6 +68,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ void *drm_private;
};
void mtk_mmsys_ddp_connect(struct device *dev,
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
2021-07-17 9:03 ` Nancy.Lin
(?)
@ 2021-07-17 9:04 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 367 ++++++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 15 +-
4 files changed, 332 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index f3addc200c97..c79f76097aa9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -746,21 +746,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -769,7 +776,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -825,19 +832,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ddc26160dea1..6ccfc2d82b64 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -160,12 +160,21 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +443,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +532,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +602,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +641,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -487,49 +730,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -550,7 +786,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -561,6 +803,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index fc03cfda7601..241c134966a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,14 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
+};
+
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ void *data_reserved;
+ struct mtk_drm_private *drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Nancy . Lin,
Yongqiang Niu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, singo.chang, srv_heupstream
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 367 ++++++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 15 +-
4 files changed, 332 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index f3addc200c97..c79f76097aa9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -746,21 +746,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -769,7 +776,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -825,19 +832,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ddc26160dea1..6ccfc2d82b64 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -160,12 +160,21 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +443,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +532,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +602,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +641,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -487,49 +730,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -550,7 +786,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -561,6 +803,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index fc03cfda7601..241c134966a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,14 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
+};
+
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ void *data_reserved;
+ struct mtk_drm_private *drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195
@ 2021-07-17 9:04 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-17 9:04 UTC (permalink / raw)
To: CK Hu
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
Nancy . Lin, linux-arm-kernel
Add driver data of mt8195 vdosys1 to mediatek-drm and modify drm for
multi-mmsys support. The two mmsys (vdosys0 and vdosys1) will bring
up two drm drivers, only one drm driver register as the drm device.
Each drm driver binds its own component. The first bind drm driver
will allocate the drm device, and the last bind drm driver registers
the drm device to drm core. Each crtc path is created with the
corresponding drm driver data.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 3 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 367 ++++++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 15 +-
4 files changed, 332 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index f3addc200c97..c79f76097aa9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -746,21 +746,28 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
- const enum mtk_ddp_comp_id *path, unsigned int path_len)
+ const enum mtk_ddp_comp_id *path, unsigned int path_len,
+ int priv_data_index)
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
struct mtk_drm_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
- int pipe = priv->num_pipes;
int ret;
int i;
bool has_ctm = false;
uint gamma_lut_size = 0;
+ struct drm_crtc *tmp;
+ int crtc_i = 0;
if (!path)
return 0;
+ priv = priv->all_drm_private[priv_data_index];
+
+ drm_for_each_crtc(tmp, drm_dev)
+ crtc_i++;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
@@ -769,7 +776,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
if (!node) {
dev_info(dev,
"Not creating crtc %d because component %d is disabled or missing\n",
- pipe, comp_id);
+ crtc_i, comp_id);
return 0;
}
}
@@ -825,19 +832,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
- pipe);
+ crtc_i);
if (ret)
return ret;
}
- ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
+ ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
return ret;
if (gamma_lut_size)
drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
- priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 66d1cf03dfe8..0646fafffd8b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -31,7 +31,8 @@
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
- unsigned int path_len);
+ unsigned int path_len,
+ int priv_data_index);
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state);
void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index ddc26160dea1..6ccfc2d82b64 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -160,12 +160,21 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DP_INTF0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_ext[] = {
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DP_INTF1,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
.ext_path = mt2701_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
@@ -174,6 +183,8 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.ext_path = mt7623_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
.shadow_register = true,
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
@@ -183,6 +194,8 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
.third_path = mt2712_mtk_ddp_third,
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
@@ -190,6 +203,8 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
.ext_path = mt8173_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -197,32 +212,219 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
.ext_path = mt8183_mtk_ddp_ext,
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .mmsys_id = 0,
+ .mmsys_dev_num = 2,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .ext_path = mt8195_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
+ .mmsys_id = 1,
+ .mmsys_dev_num = 2,
+};
+
+static const struct of_device_id mtk_drm_of_ids[] = {
+ { .compatible = "mediatek,mt2701-mmsys",
+ .data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt7623-mmsys",
+ .data = &mt7623_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8173-mmsys",
+ .data = &mt8173_mmsys_driver_data},
+ { .compatible = "mediatek,mt8183-mmsys",
+ .data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
+ { .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data},
+ { }
};
+MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+
+static int mtk_drm_get_mmsys_priv(struct device *dev,
+ struct mtk_drm_private **all_drm_priv,
+ int num)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct device_node *phandle = dev->parent->of_node;
+ const struct of_device_id *of_id;
+ struct device_node *node;
+ int cnt = 0;
+
+ for_each_child_of_node(phandle->parent, node) {
+ struct platform_device *pdev;
+ struct mtk_mmsys_private *mmsys_priv;
+
+ of_id = of_match_node(mtk_drm_of_ids, node);
+ if (!of_id)
+ continue;
+
+ pdev = of_find_device_by_node(node);
+ if (!pdev)
+ continue;
+
+ mmsys_priv = dev_get_drvdata(&pdev->dev);
+ if (!mmsys_priv || !mmsys_priv->drm_private)
+ continue;
+
+ all_drm_priv[cnt++] = mmsys_priv->drm_private;
+ if (cnt == num)
+ break;
+ }
+
+ return 0;
+}
+
+static bool mtk_drm_check_last_drm_bind(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int cnt = 0;
+ int i;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++)
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound)
+ cnt++;
+
+ return (drm_priv->data->mmsys_dev_num == cnt);
+}
+
+static bool mtk_drm_find_drm_dev(struct device *dev, struct drm_device **drm)
+{
+ struct device_node *phandle = dev->parent->of_node;
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int i;
+
+ if (!drm_priv->data->mmsys_dev_num)
+ return false;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, drm_priv->data->mmsys_dev_num);
+
+ for (i = 0; i < MAX_CRTC; i++) {
+ if (all_drm_priv[i] && all_drm_priv[i]->mtk_drm_bound) {
+ *drm = all_drm_priv[i]->drm;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int mtk_drm_setup_all_drm_private(struct device *dev)
+{
+ struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
+ struct mtk_drm_private *all_drm_priv[MAX_CRTC];
+ int mmsys_dev_num = drm_priv->data->mmsys_dev_num;
+ int i;
+ int j;
+
+ mtk_drm_get_mmsys_priv(dev, all_drm_priv, mmsys_dev_num);
+
+ for (i = 0; i < mmsys_dev_num; i++)
+ for (j = 0; j < mmsys_dev_num; j++)
+ all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
+
+ return 0;
+}
+
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+{
+ const struct mtk_mmsys_driver_data *drv_data = private->data;
+ int ret = false;
+ int i;
+
+ if (drv_data->mmsys_dev_num == 1)
+ return true;
+
+ if (drv_data->main_path) {
+ for (i = 0; i < drv_data->main_len; i++)
+ if (drv_data->main_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->main_len)
+ ret |= false;
+ }
+
+ if (drv_data->ext_path) {
+ for (i = 0; i < drv_data->ext_len; i++)
+ if (drv_data->ext_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->ext_len)
+ ret |= false;
+ }
+
+ if (drv_data->third_path) {
+ for (i = 0; i < drv_data->third_len; i++)
+ if (drv_data->third_path[i] == comp_id)
+ ret |= true;
+
+ if (i == drv_data->third_len)
+ ret |= false;
+ }
+
+ return ret;
+}
+
+static int mtk_drm_check_mutex_dev(struct mtk_drm_private *private)
+{
+ struct platform_device *pdev;
+ struct mtk_drm_private *priv_i;
+ int ret;
+ int i;
+
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+
+ pdev = of_find_device_by_node(priv_i->mutex_node);
+ if (!pdev) {
+ dev_err(priv_i->dev, "Waiting for disp-mutex device %pOF\n",
+ priv_i->mutex_node);
+ ret = -EPROBE_DEFER;
+ goto err_put_mutex;
+ }
+ priv_i->mutex_dev = &pdev->dev;
+ }
+
+ return 0;
+
+err_put_mutex:
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ priv_i = private->all_drm_private[i];
+ of_node_put(priv_i->mutex_node);
+ }
+
+ return ret;
+}
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
+ struct mtk_drm_private *priv_n;
struct platform_device *pdev;
- struct device_node *np;
+ struct device_node *np = NULL;
struct device *dma_dev;
int ret;
+ int i;
+ int j;
if (!iommu_present(&platform_bus_type))
return -EPROBE_DEFER;
- pdev = of_find_device_by_node(private->mutex_node);
- if (!pdev) {
- dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
- private->mutex_node);
- of_node_put(private->mutex_node);
- return -EPROBE_DEFER;
- }
- private->mutex_dev = &pdev->dev;
+ ret = mtk_drm_check_mutex_dev(private);
+ if (ret)
+ return ret;
ret = drmm_mode_config_init(drm);
if (ret)
@@ -241,33 +443,57 @@ static int mtk_drm_kms_init(struct drm_device *drm)
drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
- ret = component_bind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++) {
+ drm->dev_private = private->all_drm_private[i];
+ ret = component_bind_all(private->all_drm_private[i]->dev, drm);
if (ret)
goto put_mutex_dev;
+ }
/*
* We currently support two fixed data streams, each optional,
* and each statically assigned to a crtc:
* OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
*/
- ret = mtk_drm_crtc_create(drm, private->data->main_path,
- private->data->main_len);
- if (ret < 0)
- goto err_component_unbind;
- /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
- ret = mtk_drm_crtc_create(drm, private->data->ext_path,
- private->data->ext_len);
- if (ret < 0)
- goto err_component_unbind;
-
- ret = mtk_drm_crtc_create(drm, private->data->third_path,
- private->data->third_len);
- if (ret < 0)
- goto err_component_unbind;
+ for (i = 0; i < MAX_CRTC; i++) {
+ for (j = 0; j < private->data->mmsys_dev_num; j++) {
+ priv_n = private->all_drm_private[j];
+
+ if (i == 0 && priv_n->data->main_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
+ priv_n->data->main_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->main_path[0]];
+
+ continue;
+ } else if (i == 1 && priv_n->data->ext_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->ext_path,
+ priv_n->data->ext_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->ext_path[0]];
+
+ continue;
+ } else if (i == 2 && priv_n->data->third_len) {
+ ret = mtk_drm_crtc_create(drm, priv_n->data->third_path,
+ priv_n->data->third_len, j);
+ if (ret)
+ goto err_component_unbind;
+
+ if (!np)
+ np = priv_n->comp_node[priv_n->data->third_path[0]];
+
+ continue;
+ }
+ }
+ }
/* Use OVL device for all DMA memory allocations */
- np = private->comp_node[private->data->main_path[0]] ?:
- private->comp_node[private->data->ext_path[0]];
pdev = of_find_device_by_node(np);
if (!pdev) {
ret = -ENODEV;
@@ -276,13 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
dma_dev = &pdev->dev;
- private->dma_dev = dma_dev;
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ private->all_drm_private[i]->dma_dev = dma_dev;
/*
* Configure the DMA segment size to make sure we get contiguous IOVA
* when importing PRIME buffers.
*/
ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
+
if (ret) {
dev_err(dma_dev, "Failed to set DMA segment size\n");
goto err_component_unbind;
@@ -304,9 +532,12 @@ static int mtk_drm_kms_init(struct drm_device *drm)
return 0;
err_component_unbind:
- component_unbind_all(drm->dev, drm);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ component_unbind_all(private->all_drm_private[i]->dev, drm);
put_mutex_dev:
- put_device(private->mutex_dev);
+ for (i = 0; i < private->data->mmsys_dev_num; i++)
+ put_device(private->all_drm_private[i]->mutex_dev);
+
return ret;
}
@@ -371,12 +602,21 @@ static int mtk_drm_bind(struct device *dev)
struct drm_device *drm;
int ret;
- drm = drm_dev_alloc(&mtk_drm_driver, dev);
- if (IS_ERR(drm))
- return PTR_ERR(drm);
+ if (!mtk_drm_find_drm_dev(dev, &drm)) {
+ drm = drm_dev_alloc(&mtk_drm_driver, dev);
+ if (IS_ERR(drm))
+ return PTR_ERR(drm);
+ drm->dev_private = private;
+ }
- drm->dev_private = private;
+ private->dev = dev;
private->drm = drm;
+ private->mtk_drm_bound = true;
+
+ if (!mtk_drm_check_last_drm_bind(dev))
+ return 0;
+
+ mtk_drm_setup_all_drm_private(dev);
ret = mtk_drm_kms_init(drm);
if (ret < 0)
@@ -401,10 +641,13 @@ static void mtk_drm_unbind(struct device *dev)
{
struct mtk_drm_private *private = dev_get_drvdata(dev);
- drm_dev_unregister(private->drm);
- mtk_drm_kms_deinit(private->drm);
- drm_dev_put(private->drm);
- private->num_pipes = 0;
+ /* for multi mmsys dev, unregister drm dev in mmsys master */
+ if (private->data->mmsys_id == 0) {
+ drm_dev_unregister(private->drm);
+ mtk_drm_kms_deinit(private->drm);
+ drm_dev_put(private->drm);
+ }
+ private->mtk_drm_bound = false;
private->drm = NULL;
}
@@ -487,49 +730,42 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ }
};
-static const struct of_device_id mtk_drm_of_ids[] = {
- { .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
- { .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
- { .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
- { .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
- { .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
- {.compatible = "mediatek,mt8195-vdosys0",
- .data = &mt8195_vdosys0_driver_data},
- { }
-};
-MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_driver_data *drv_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
+ struct mtk_mmsys_private *mmsys_priv;
int ret;
int i;
+ of_id = of_match_node(mtk_drm_of_ids, phandle);
+ if (!of_id)
+ return -ENODEV;
+
+ drv_data = of_id->data;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
return -ENOMEM;
+ private->all_drm_private = devm_kmalloc_array(dev, drv_data->mmsys_dev_num,
+ sizeof(*private->all_drm_private),
+ GFP_KERNEL);
+ if (!private->all_drm_private)
+ return -ENOMEM;
+
+ private->data = drv_data;
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
return -ENODEV;
}
-
- of_id = of_match_node(mtk_drm_of_ids, phandle);
- if (!of_id)
- return -ENODEV;
-
- private->data = of_id->data;
+ mmsys_priv = dev_get_drvdata(private->mmsys_dev);
+ mmsys_priv->drm_private = private;
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
@@ -550,7 +786,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type = (enum mtk_ddp_comp_type)of_id->data;
if (comp_type == MTK_DISP_MUTEX) {
- private->mutex_node = of_node_get(node);
+ int id;
+
+ id = of_alias_get_id(node, "mutex");
+ if (id < 0 || id == drv_data->mmsys_id) {
+ private->mutex_node = of_node_get(node);
+ dev_dbg(dev, "get mutex for mmsys %d", drv_data->mmsys_id);
+ }
continue;
}
@@ -561,6 +803,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
+ if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ continue;
+
private->comp_node[comp_id] = of_node_get(node);
/*
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index fc03cfda7601..241c134966a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -29,14 +29,15 @@ struct mtk_mmsys_driver_data {
unsigned int third_len;
bool shadow_register;
+ unsigned int mmsys_id;
+ unsigned int mmsys_dev_num;
};
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
-
- unsigned int num_pipes;
-
+ bool mtk_drm_bound;
+ struct device *dev;
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
@@ -44,6 +45,14 @@ struct mtk_drm_private {
struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX];
const struct mtk_mmsys_driver_data *data;
struct drm_atomic_state *suspend_state;
+ struct mtk_drm_private **all_drm_private;
+};
+
+/* duplicate with mmsys private data */
+struct mtk_mmsys_private {
+ void __iomem *regs_reserved;
+ void *data_reserved;
+ struct mtk_drm_private *drm_private;
};
extern struct platform_driver mtk_disp_ccorr_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
2021-07-17 9:03 ` Nancy.Lin
(?)
(?)
@ 2021-07-18 23:22 ` Chun-Kuang Hu
-1 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:22 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> 1. Add pseudo-ovl definition file for mt8195 display.
> 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,disp.yaml | 5 +
> .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> index aac1796e3f6b..bb6d28572b48 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> @@ -230,6 +230,11 @@ properties:
> - items:
> - const: mediatek,mt8173-disp-od
>
> + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> + # for details.
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> +
> reg:
> description: Physical base address and length of the function block register space.
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> new file mode 100644
> index 000000000000..9059d96ce70e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek pseudo ovl Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Nancy.Lin <nancy.lin@mediatek.com>
> +
> +description: |
> + The Mediatek pseudo ovl function block is composed of eight RDMA and
> + four MERGE devices. It's encapsulated as an overlay device, which supports
> + 4 layers.
> +
> +properties:
> + compatible:
> + oneOf:
> + # pseudo ovl controller
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> + # RDMA: read DMA
> + - items:
> + - const: mediatek,mt8195-vdo1-rdma
> + # MERGE: merge streams from two RDMA sources
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
> + reg:
> + maxItems: 1
> + interrupts:
> + maxItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + maxItems: 1
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> + power-domains:
> + maxItems: 1
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const:
> + - mediatek,mt8195-vdo1-merge
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: merge clock
> + - description: merge async clock
> + clock-names:
> + items:
> + - const: merge
> + - const: merge_async
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + vdo1_rdma@1c104000 {
> + compatible = "mediatek,mt8195-vdo1-rdma",
> + "mediatek,mt8195-disp-pseudo-ovl";
Do not create pseudo or virtual device, so just leave the
"mediatek,mt8195-vdo1-rdma".
Regards,
Chun-Kuang.
> + reg = <0 0x1c104000 0 0x1000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
> + };
> +
> + disp_vpp_merge@1c10c000 {
> + compatible = "mediatek,mt8195-vdo1-merge";
> + reg = <0 0x1c10c000 0 0x1000>;
> + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> + clock-names = "merge","merge_async";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
> + };
> +
> +...
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-18 23:22 ` Chun-Kuang Hu
0 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:22 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> 1. Add pseudo-ovl definition file for mt8195 display.
> 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,disp.yaml | 5 +
> .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> index aac1796e3f6b..bb6d28572b48 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> @@ -230,6 +230,11 @@ properties:
> - items:
> - const: mediatek,mt8173-disp-od
>
> + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> + # for details.
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> +
> reg:
> description: Physical base address and length of the function block register space.
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> new file mode 100644
> index 000000000000..9059d96ce70e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek pseudo ovl Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Nancy.Lin <nancy.lin@mediatek.com>
> +
> +description: |
> + The Mediatek pseudo ovl function block is composed of eight RDMA and
> + four MERGE devices. It's encapsulated as an overlay device, which supports
> + 4 layers.
> +
> +properties:
> + compatible:
> + oneOf:
> + # pseudo ovl controller
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> + # RDMA: read DMA
> + - items:
> + - const: mediatek,mt8195-vdo1-rdma
> + # MERGE: merge streams from two RDMA sources
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
> + reg:
> + maxItems: 1
> + interrupts:
> + maxItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + maxItems: 1
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> + power-domains:
> + maxItems: 1
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const:
> + - mediatek,mt8195-vdo1-merge
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: merge clock
> + - description: merge async clock
> + clock-names:
> + items:
> + - const: merge
> + - const: merge_async
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + vdo1_rdma@1c104000 {
> + compatible = "mediatek,mt8195-vdo1-rdma",
> + "mediatek,mt8195-disp-pseudo-ovl";
Do not create pseudo or virtual device, so just leave the
"mediatek,mt8195-vdo1-rdma".
Regards,
Chun-Kuang.
> + reg = <0 0x1c104000 0 0x1000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
> + };
> +
> + disp_vpp_merge@1c10c000 {
> + compatible = "mediatek,mt8195-vdo1-merge";
> + reg = <0 0x1c10c000 0 0x1000>;
> + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> + clock-names = "merge","merge_async";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
> + };
> +
> +...
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-18 23:22 ` Chun-Kuang Hu
0 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:22 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> 1. Add pseudo-ovl definition file for mt8195 display.
> 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,disp.yaml | 5 +
> .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> index aac1796e3f6b..bb6d28572b48 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> @@ -230,6 +230,11 @@ properties:
> - items:
> - const: mediatek,mt8173-disp-od
>
> + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> + # for details.
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> +
> reg:
> description: Physical base address and length of the function block register space.
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> new file mode 100644
> index 000000000000..9059d96ce70e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek pseudo ovl Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Nancy.Lin <nancy.lin@mediatek.com>
> +
> +description: |
> + The Mediatek pseudo ovl function block is composed of eight RDMA and
> + four MERGE devices. It's encapsulated as an overlay device, which supports
> + 4 layers.
> +
> +properties:
> + compatible:
> + oneOf:
> + # pseudo ovl controller
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> + # RDMA: read DMA
> + - items:
> + - const: mediatek,mt8195-vdo1-rdma
> + # MERGE: merge streams from two RDMA sources
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
> + reg:
> + maxItems: 1
> + interrupts:
> + maxItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + maxItems: 1
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> + power-domains:
> + maxItems: 1
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const:
> + - mediatek,mt8195-vdo1-merge
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: merge clock
> + - description: merge async clock
> + clock-names:
> + items:
> + - const: merge
> + - const: merge_async
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + vdo1_rdma@1c104000 {
> + compatible = "mediatek,mt8195-vdo1-rdma",
> + "mediatek,mt8195-disp-pseudo-ovl";
Do not create pseudo or virtual device, so just leave the
"mediatek,mt8195-vdo1-rdma".
Regards,
Chun-Kuang.
> + reg = <0 0x1c104000 0 0x1000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
> + };
> +
> + disp_vpp_merge@1c10c000 {
> + compatible = "mediatek,mt8195-vdo1-merge";
> + reg = <0 0x1c10c000 0 0x1000>;
> + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> + clock-names = "merge","merge_async";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
> + };
> +
> +...
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-18 23:22 ` Chun-Kuang Hu
0 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:22 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> 1. Add pseudo-ovl definition file for mt8195 display.
> 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,disp.yaml | 5 +
> .../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> index aac1796e3f6b..bb6d28572b48 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> @@ -230,6 +230,11 @@ properties:
> - items:
> - const: mediatek,mt8173-disp-od
>
> + # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> + # for details.
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> +
> reg:
> description: Physical base address and length of the function block register space.
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> new file mode 100644
> index 000000000000..9059d96ce70e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek pseudo ovl Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Nancy.Lin <nancy.lin@mediatek.com>
> +
> +description: |
> + The Mediatek pseudo ovl function block is composed of eight RDMA and
> + four MERGE devices. It's encapsulated as an overlay device, which supports
> + 4 layers.
> +
> +properties:
> + compatible:
> + oneOf:
> + # pseudo ovl controller
> + - items:
> + - const: mediatek,mt8195-disp-pseudo-ovl
> + # RDMA: read DMA
> + - items:
> + - const: mediatek,mt8195-vdo1-rdma
> + # MERGE: merge streams from two RDMA sources
> + - items:
> + - const: mediatek,mt8195-vdo1-merge
> + reg:
> + maxItems: 1
> + interrupts:
> + maxItems: 1
> + iommus:
> + description: The compatible property is DMA function blocks.
> + Should point to the respective IOMMU block with master port as argument,
> + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> + details.
> + maxItems: 1
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> + power-domains:
> + maxItems: 1
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: The register of display function block to be set by gce.
> + There are 4 arguments in this property, gce node, subsys id, offset and
> + register size. The subsys id is defined in the gce header of each chips
> + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
> + display function block.
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const:
> + - mediatek,mt8195-vdo1-merge
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: merge clock
> + - description: merge async clock
> + clock-names:
> + items:
> + - const: merge
> + - const: merge_async
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + vdo1_rdma@1c104000 {
> + compatible = "mediatek,mt8195-vdo1-rdma",
> + "mediatek,mt8195-disp-pseudo-ovl";
Do not create pseudo or virtual device, so just leave the
"mediatek,mt8195-vdo1-rdma".
Regards,
Chun-Kuang.
> + reg = <0 0x1c104000 0 0x1000>;
> + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
> + };
> +
> + disp_vpp_merge@1c10c000 {
> + compatible = "mediatek,mt8195-vdo1-merge";
> + reg = <0 0x1c10c000 0 0x1000>;
> + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> + clock-names = "merge","merge_async";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
> + };
> +
> +...
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
2021-07-17 9:04 ` Nancy.Lin
(?)
@ 2021-07-18 23:56 ` Chun-Kuang Hu
-1 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:56 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> 8 files changed, 584 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..fcce08710cef 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..7227ffbc3eae 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..3fa86f12feb4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> +};
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_COLOR] = "color",
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_AAL] = "aal",
> + [MTK_DISP_ETHDR] = "ethdr",
> [MTK_DISP_GAMMA] = "gamma",
> [MTK_DISP_DITHER] = "dither",
> [MTK_DISP_UFOE] = "ufoe",
> @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
> [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
> [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
> @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_CCORR ||
> type == MTK_DISP_COLOR ||
> type == MTK_DISP_DSC ||
> + type == MTK_DISP_ETHDR ||
> type == MTK_DISP_GAMMA ||
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f55efba6e744 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_ETHDR,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..ace958a34bb5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_ETHDR },
> { }
> };
>
> @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> if (comp_type == MTK_DISP_CCORR ||
> comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_DSC ||
> + comp_type == MTK_DISP_ETHDR ||
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> @@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..ceadb28169b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,537 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> +#define MIX_ROI_BGCLR 0x20
> +#define MIX_SRC_CON 0x24
> +#define MIX_L0_CON 0x28
> +#define MIX_L0_SRC_SIZE 0x30
> +#define MIX_L0_OFFSET 0x34
> +#define MIX_L1_CON 0x40
> +#define MIX_L1_SRC_SIZE 0x48
> +#define MIX_L1_OFFSET 0x4c
> +#define MIX_L2_CON 0x58
> +#define MIX_L2_SRC_SIZE 0x60
> +#define MIX_L2_OFFSET 0x64
> +#define MIX_L3_CON 0x70
> +#define MIX_L3_SRC_SIZE 0x78
> +#define MIX_L3_OFFSET 0x7c
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> +
> +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> +
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
> +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> +
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + void __iomem *top_regs;
> + struct cmdq_client_reg top_cmdq_base;
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +static const unsigned int alpha_source_sel[] = {
> + HDR_ALPHA_SEL_MIXER_IN1,
> + HDR_ALPHA_SEL_MIXER_IN2,
> + HDR_ALPHA_SEL_MIXER_IN3,
> + HDR_ALPHA_SEL_MIXER_IN4,
> +};
> +
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx < 4)
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> + mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
Why not just
mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
Because ethdr has layers and vblank interrupt, I think ethdr should be
part of pseudo ovl, so squash these two into one.
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + fmt = state->pending.format;
fmt is useless, so remove.
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
interface for this driver to use.
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
> + }
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
And you could get rid of this switch case.
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_CON, 0x1ff);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_CON, 0x1ff);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_CON, 0x1ff);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_CON, 0x1ff);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> + mixer->regs, MIX_ROI_SIZE, ~0);
mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
Explain what these value mean.
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM0, ~0);
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM1, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
> + MIX_DATAPATH_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
> + MIX_ROI_BGCLR, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
> + MIX_EN, ~0);
I think only the latest setting is about start, move other setting to config.
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
> + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> + HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
Make vdosys1 a reset controller like [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
Regards,
Chun-Kuang.
> +}
> +
> +int mtk_ethdr_clk_enable(struct device *dev)
> +{
> + int i, ret;
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + dev_err(dev,
> + "ethdr_clk prepare enable failed\n");
> + return ret;
> +}
> +
> +void mtk_ethdr_clk_disable(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + int i;
> +
> + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> +}
> +
> +static int mtk_ethdr_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + return 0;
> +}
> +
> +static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_ethdr_component_ops = {
> + .bind = mtk_ethdr_bind,
> + .unbind = mtk_ethdr_unbind,
> +};
> +
> +static int mtk_ethdr_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ethdr *priv;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + for (i = 0; i < ETHDR_ID_MAX; i++) {
> + priv->ethdr_comp[i].dev = dev;
> + priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev,
> + &priv->ethdr_comp[i].cmdq_base, i);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> + priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
> + }
> +
> + for (i = 0; i < ETHDR_CLK_NUM; i++)
> + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_ethdr_component_ops);
> + if (ret)
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + dev_info(dev, "%s-\n", __func__);
> +
> + return ret;
> +}
> +
> +static int mtk_ethdr_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> +
> +struct platform_driver mtk_ethdr_driver = {
> + .probe = mtk_ethdr_probe,
> + .remove = mtk_ethdr_remove,
> + .driver = {
> + .name = "mediatek-disp-ethdr",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ethdr_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> new file mode 100644
> index 000000000000..c8fc0581a632
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_ETHDR_H__
> +#define __MTK_DISP_ETHDR_H__
> +
> +#include <linux/uaccess.h>
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +#endif
> +
> --
> 2.18.0
>
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-18 23:56 ` Chun-Kuang Hu
0 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:56 UTC (permalink / raw)
To: Nancy.Lin
Cc: CK Hu, Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> 8 files changed, 584 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..fcce08710cef 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..7227ffbc3eae 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..3fa86f12feb4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> +};
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_COLOR] = "color",
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_AAL] = "aal",
> + [MTK_DISP_ETHDR] = "ethdr",
> [MTK_DISP_GAMMA] = "gamma",
> [MTK_DISP_DITHER] = "dither",
> [MTK_DISP_UFOE] = "ufoe",
> @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
> [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
> [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
> @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_CCORR ||
> type == MTK_DISP_COLOR ||
> type == MTK_DISP_DSC ||
> + type == MTK_DISP_ETHDR ||
> type == MTK_DISP_GAMMA ||
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f55efba6e744 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_ETHDR,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..ace958a34bb5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_ETHDR },
> { }
> };
>
> @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> if (comp_type == MTK_DISP_CCORR ||
> comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_DSC ||
> + comp_type == MTK_DISP_ETHDR ||
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> @@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..ceadb28169b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,537 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> +#define MIX_ROI_BGCLR 0x20
> +#define MIX_SRC_CON 0x24
> +#define MIX_L0_CON 0x28
> +#define MIX_L0_SRC_SIZE 0x30
> +#define MIX_L0_OFFSET 0x34
> +#define MIX_L1_CON 0x40
> +#define MIX_L1_SRC_SIZE 0x48
> +#define MIX_L1_OFFSET 0x4c
> +#define MIX_L2_CON 0x58
> +#define MIX_L2_SRC_SIZE 0x60
> +#define MIX_L2_OFFSET 0x64
> +#define MIX_L3_CON 0x70
> +#define MIX_L3_SRC_SIZE 0x78
> +#define MIX_L3_OFFSET 0x7c
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> +
> +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> +
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
> +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> +
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + void __iomem *top_regs;
> + struct cmdq_client_reg top_cmdq_base;
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +static const unsigned int alpha_source_sel[] = {
> + HDR_ALPHA_SEL_MIXER_IN1,
> + HDR_ALPHA_SEL_MIXER_IN2,
> + HDR_ALPHA_SEL_MIXER_IN3,
> + HDR_ALPHA_SEL_MIXER_IN4,
> +};
> +
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx < 4)
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> + mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
Why not just
mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
Because ethdr has layers and vblank interrupt, I think ethdr should be
part of pseudo ovl, so squash these two into one.
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + fmt = state->pending.format;
fmt is useless, so remove.
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
interface for this driver to use.
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
> + }
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
And you could get rid of this switch case.
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_CON, 0x1ff);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_CON, 0x1ff);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_CON, 0x1ff);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_CON, 0x1ff);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> + mixer->regs, MIX_ROI_SIZE, ~0);
mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
Explain what these value mean.
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM0, ~0);
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM1, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
> + MIX_DATAPATH_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
> + MIX_ROI_BGCLR, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
> + MIX_EN, ~0);
I think only the latest setting is about start, move other setting to config.
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
> + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> + HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
Make vdosys1 a reset controller like [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
Regards,
Chun-Kuang.
> +}
> +
> +int mtk_ethdr_clk_enable(struct device *dev)
> +{
> + int i, ret;
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + dev_err(dev,
> + "ethdr_clk prepare enable failed\n");
> + return ret;
> +}
> +
> +void mtk_ethdr_clk_disable(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + int i;
> +
> + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> +}
> +
> +static int mtk_ethdr_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + return 0;
> +}
> +
> +static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_ethdr_component_ops = {
> + .bind = mtk_ethdr_bind,
> + .unbind = mtk_ethdr_unbind,
> +};
> +
> +static int mtk_ethdr_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ethdr *priv;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + for (i = 0; i < ETHDR_ID_MAX; i++) {
> + priv->ethdr_comp[i].dev = dev;
> + priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev,
> + &priv->ethdr_comp[i].cmdq_base, i);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> + priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
> + }
> +
> + for (i = 0; i < ETHDR_CLK_NUM; i++)
> + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_ethdr_component_ops);
> + if (ret)
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + dev_info(dev, "%s-\n", __func__);
> +
> + return ret;
> +}
> +
> +static int mtk_ethdr_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> +
> +struct platform_driver mtk_ethdr_driver = {
> + .probe = mtk_ethdr_probe,
> + .remove = mtk_ethdr_remove,
> + .driver = {
> + .name = "mediatek-disp-ethdr",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ethdr_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> new file mode 100644
> index 000000000000..c8fc0581a632
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_ETHDR_H__
> +#define __MTK_DISP_ETHDR_H__
> +
> +#include <linux/uaccess.h>
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +#endif
> +
> --
> 2.18.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-18 23:56 ` Chun-Kuang Hu
0 siblings, 0 replies; 52+ messages in thread
From: Chun-Kuang Hu @ 2021-07-18 23:56 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Matthias Brugger, Rob Herring,
moderated list:ARM/Mediatek SoC support, Linux ARM
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
>
> Add ETHDR module files:
> ETHDR is designed for HDR video and graphics conversion in the external
> display path. It handles multiple HDR input types and performs tone
> mapping, color space/color format conversion, and then combines
> different layers, output the required HDR or SDR signal to the
> subsequent display path.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 537 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> 8 files changed, 584 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 27c89847d43b..fcce08710cef 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_gem.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> - mtk_dpi.o
> + mtk_dpi.o \
> + mtk_ethdr.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 3e27ce7fef57..7227ffbc3eae 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_ethdr_clk_enable(struct device *dev);
> +void mtk_ethdr_clk_disable(struct device *dev);
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_start(struct device *dev);
> +void mtk_ethdr_stop(struct device *dev);
> +
> #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 9125d0f6352f..3fa86f12feb4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> + .clk_enable = mtk_ethdr_clk_enable,
> + .clk_disable = mtk_ethdr_clk_disable,
> + .config = mtk_ethdr_config,
> + .start = mtk_ethdr_start,
> + .stop = mtk_ethdr_stop,
> +};
> +
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> [MTK_DISP_OVL_2L] = "ovl-2l",
> @@ -363,6 +371,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_COLOR] = "color",
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_AAL] = "aal",
> + [MTK_DISP_ETHDR] = "ethdr",
> [MTK_DISP_GAMMA] = "gamma",
> [MTK_DISP_DITHER] = "dither",
> [MTK_DISP_UFOE] = "ufoe",
> @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0, &ddp_ethdr},
> [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
> [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
> @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_CCORR ||
> type == MTK_DISP_COLOR ||
> type == MTK_DISP_DSC ||
> + type == MTK_DISP_ETHDR ||
> type == MTK_DISP_GAMMA ||
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0afd78c0bc92..f55efba6e744 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> + MTK_DISP_ETHDR,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 11c25daf05d8..ace958a34bb5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-ethdr",
> + .data = (void *)MTK_DISP_ETHDR },
> { }
> };
>
> @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> if (comp_type == MTK_DISP_CCORR ||
> comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_DSC ||
> + comp_type == MTK_DISP_ETHDR ||
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> @@ -676,6 +679,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_ethdr_driver,
> };
>
> static int __init mtk_drm_init(void)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c4d802a43531..c87ebb5309d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,5 +55,6 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> new file mode 100644
> index 000000000000..ceadb28169b8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -0,0 +1,537 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_ethdr.h"
> +
> +#define MIX_EN 0xc
> +#define MIX_RST 0x14
> +#define MIX_ROI_SIZE 0x18
> +#define MIX_DATAPATH_CON 0x1c
> +#define MIX_ROI_BGCLR 0x20
> +#define MIX_SRC_CON 0x24
> +#define MIX_L0_CON 0x28
> +#define MIX_L0_SRC_SIZE 0x30
> +#define MIX_L0_OFFSET 0x34
> +#define MIX_L1_CON 0x40
> +#define MIX_L1_SRC_SIZE 0x48
> +#define MIX_L1_OFFSET 0x4c
> +#define MIX_L2_CON 0x58
> +#define MIX_L2_SRC_SIZE 0x60
> +#define MIX_L2_OFFSET 0x64
> +#define MIX_L3_CON 0x70
> +#define MIX_L3_SRC_SIZE 0x78
> +#define MIX_L3_OFFSET 0x7c
> +#define MIX_FUNC_DCM0 0x120
> +#define MIX_FUNC_DCM1 0x124
> +
> +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> +
> +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> +
> +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23))
> +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> +
> +#define MIXER_ALPHA_AEN BIT(8)
> +#define MIXER_ALPHA 0xff
> +#define ETHDR_CLK_NUM 13
> +
> +enum mtk_ethdr_comp_id {
> + ETHDR_MIXER,
> + ETHDR_VDO_FE0,
> + ETHDR_VDO_FE1,
> + ETHDR_GFX_FE0,
> + ETHDR_GFX_FE1,
> + ETHDR_VDO_BE,
> + ETHDR_ADL_DS,
> + ETHDR_ID_MAX
> +};
> +
> +struct mtk_ethdr_comp {
> + struct device *dev;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_base;
> +};
> +
> +struct mtk_ethdr {
> + void __iomem *top_regs;
> + struct cmdq_client_reg top_cmdq_base;
> + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> +};
> +
> +static const char * const ethdr_comp_str[] = {
> + "ETHDR_MIXER",
> + "ETHDR_VDO_FE0",
> + "ETHDR_VDO_FE1",
> + "ETHDR_GFX_FE0",
> + "ETHDR_GFX_FE1",
> + "ETHDR_VDO_BE",
> + "ETHDR_ADL_DS",
> + "ETHDR_ID_MAX"
> +};
> +
> +static const char * const ethdr_clk_str[] = {
> + "ethdr_top",
> + "mixer",
> + "vdo_fe0",
> + "vdo_fe1",
> + "gfx_fe0",
> + "gfx_fe1",
> + "vdo_be",
> + "adl_ds",
> + "vdo_fe0_async",
> + "vdo_fe1_async",
> + "gfx_fe0_async",
> + "gfx_fe1_async",
> + "vdo_be_async",
> +};
> +
> +static const unsigned int alpha_source_sel[] = {
> + HDR_ALPHA_SEL_MIXER_IN1,
> + HDR_ALPHA_SEL_MIXER_IN2,
> + HDR_ALPHA_SEL_MIXER_IN3,
> + HDR_ALPHA_SEL_MIXER_IN4,
> +};
> +
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + if (idx < 4)
> + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
> + mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
Why not just
mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
mixer->regs, MIX_SRC_CON, BIT(idx));
> +}
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
Because ethdr has layers and vblank interrupt, I think ethdr should be
part of pseudo ovl, so squash these two into one.
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> + struct mtk_plane_pending_state *pending = &state->pending;
> + unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int offset = (pending->y << 16) | pending->x;
> + unsigned int alpha_con = 0;
> + unsigned int fmt = 0;
> +
> + fmt = state->pending.format;
fmt is useless, so remove.
> +
> + if (state->base.fb && state->base.fb->format->has_alpha) {
> + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
interface for this driver to use.
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_HDR_TOP_CFG, alpha_source_sel[idx]);
> + }
> +
> + switch (idx) {
> + case 0:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_SRC_SIZE, ~0);
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
And you could get rid of this switch case.
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L0_CON, 0x1ff);
> + break;
> + case 1:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L1_CON, 0x1ff);
> + break;
> + case 2:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L2_CON, 0x1ff);
> + break;
> + case 3:
> + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_OFFSET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
> + mixer->regs, MIX_L3_CON, 0x1ff);
> + break;
> + default:
> + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> + break;
> + }
> +}
> +
> +void mtk_ethdr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> + mixer->regs, MIX_ROI_SIZE, ~0);
mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
mixer->regs, MIX_ROI_SIZE);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> +}
> +
> +void mtk_ethdr_start(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
> + struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
> + struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
> + struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
> + struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base, vdo_fe0->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
Explain what these value mean.
> +
> + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base, vdo_fe1->regs,
> + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base, gfx_fe0->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base, gfx_fe1->regs,
> + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be->regs,
> + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> +
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM0, ~0);
> + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base, mixer->regs,
> + MIX_FUNC_DCM1, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base, mixer->regs,
> + MIX_DATAPATH_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L0_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L1_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L2_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer->regs,
> + MIX_L3_SRC_SIZE, ~0);
> + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base, mixer->regs,
> + MIX_SRC_CON, ~0);
> + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base, mixer->regs,
> + MIX_ROI_BGCLR, ~0);
> + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base, mixer->regs,
> + MIX_EN, ~0);
I think only the latest setting is about start, move other setting to config.
> +}
> +
> +void mtk_ethdr_stop(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
> +
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_EN, ~0);
> + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW1_RST_B, HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
> + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs, MIX_RST, ~0);
> + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv->top_cmdq_base,
> + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> + HDR_ASYNC_RESET_BIT);
> + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base, priv->top_regs,
> + VDO1_CONFIG_SW0_RST_B, BIT(29));
Make vdosys1 a reset controller like [1].
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355
Regards,
Chun-Kuang.
> +}
> +
> +int mtk_ethdr_clk_enable(struct device *dev)
> +{
> + int i, ret;
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> +
> + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + dev_err(dev,
> + "ethdr_clk prepare enable failed\n");
> + return ret;
> +}
> +
> +void mtk_ethdr_clk_disable(struct device *dev)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + int i;
> +
> + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> +}
> +
> +static int mtk_ethdr_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &priv->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + return 0;
> +}
> +
> +static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_ethdr_component_ops = {
> + .bind = mtk_ethdr_bind,
> + .unbind = mtk_ethdr_unbind,
> +};
> +
> +static int mtk_ethdr_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ethdr *priv;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + for (i = 0; i < ETHDR_ID_MAX; i++) {
> + priv->ethdr_comp[i].dev = dev;
> + priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev,
> + &priv->ethdr_comp[i].cmdq_base, i);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> + priv->ethdr_comp[i].regs, ethdr_comp_str[i]);
> + }
> +
> + for (i = 0; i < ETHDR_CLK_NUM; i++)
> + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_ethdr_component_ops);
> + if (ret)
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + dev_info(dev, "%s-\n", __func__);
> +
> + return ret;
> +}
> +
> +static int mtk_ethdr_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-ethdr"},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> +
> +struct platform_driver mtk_ethdr_driver = {
> + .probe = mtk_ethdr_probe,
> + .remove = mtk_ethdr_remove,
> + .driver = {
> + .name = "mediatek-disp-ethdr",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_ethdr_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> new file mode 100644
> index 000000000000..c8fc0581a632
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_ETHDR_H__
> +#define __MTK_DISP_ETHDR_H__
> +
> +#include <linux/uaccess.h>
> +#include <drm/mediatek_drm.h>
> +
> +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> + struct cmdq_pkt *cmdq_pkt);
> +#endif
> +
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
2021-07-17 9:04 ` Nancy.Lin
(?)
@ 2021-07-20 5:57 ` CK Hu
-1 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-20 5:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
> layers. The four layers are blending at the EHTDR module next to it.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
> 10 files changed, 1453 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fcce08710cef..70b53487ab0c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_ethdr.o
> + mtk_ethdr.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 7227ffbc3eae..f5d35007b84d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
> +
> int mtk_ethdr_clk_enable(struct device *dev);
> void mtk_ethdr_clk_disable(struct device *dev);
> void mtk_ethdr_config(struct device *dev, unsigned int w,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..8ec80e1887e0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,655 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_ethdr.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
> +#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
> +#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
> +#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + struct cmdq_client_reg top_cmdq_base;
> + void __iomem *top_regs;
> + const struct pseudo_ovl_data *data;
> + struct device *next_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static const unsigned int merge_async_offset[] = {
> + VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
> +};
> +
> +static const unsigned int merge_async_reset_bit[] = {
> + BIT(25), BIT(26), BIT(27), BIT(28)};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
case CFG12_10_10_1PI_2PO_BUF_MODE :
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
mtk_ddp_write(cmdq_pkt, merge_cfg->in_h << 16 |merge_cfg->in_w[0],
&comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + break;
> + case 18:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
> + break;
> + default:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
> + break;
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, ~0);
> +}
> +
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + return pseudo_ovl->data->layer_nr;
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
> + &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
> + merge_async_offset[idx], ~0);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
> + mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
> + &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
> +
> + pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + return 0;
> +}
> +
> +static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
> + .bind = mtk_disp_pseudo_ovl_bind,
> + .unbind = mtk_disp_pseudo_ovl_unbind,
> +};
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
> + if (ret != 0) {
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
> + }
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
Now only one SoC, so remove this driver data.
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
> +
> +static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 3fa86f12feb4..64cbb9e1cc83 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_pseudo_ovl_clk_enable,
> + .clk_disable = mtk_pseudo_ovl_clk_disable,
> + .config = mtk_pseudo_ovl_config,
> + .start = mtk_pseudo_ovl_start,
> + .stop = mtk_pseudo_ovl_stop,
> + .layer_nr = mtk_pseudo_ovl_layer_nr,
> + .layer_config = mtk_pseudo_ovl_layer_config,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> .clk_enable = mtk_ethdr_clk_enable,
> .clk_disable = mtk_ethdr_clk_disable,
> @@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
> return 0;
> }
>
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
> +{
> + struct mtk_drm_private *private = drm->dev_private;
> + const enum mtk_ddp_comp_id *path;
> + unsigned int path_len = 0;
> + int i;
> +
> + if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
> + private->data->main_len,
> + private->ddp_comp)) {
> + path_len = private->data->main_len;
> + path = private->data->main_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
> + private->data->ext_len,
> + private->ddp_comp)) {
> + path_len = private->data->ext_len;
> + path = private->data->ext_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
> + private->data->third_len,
> + private->ddp_comp)) {
> + path_len = private->data->third_len;
> + path = private->data->third_path;
> + }
> +
> + if (!path_len)
> + return NULL;
> +
> + for (i = 0U; i < path_len; i++)
> + if (dev == private->ddp_comp[path[i]].dev)
> + break;
> +
> + if (i < (path_len - 1))
> + return private->ddp_comp[path[i + 1]].dev;
> + else
> + return NULL;
> +}
> +
> int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id)
> {
> @@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index f55efba6e744..ec84dc258124 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> MTK_DISP_ETHDR,
> + MTK_DISP_PSEUDO_OVL,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> @@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
> struct device *dev);
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm,
> + struct device *dev);
> int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id);
> enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index ace958a34bb5..ddc26160dea1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { .compatible = "mediatek,mt8195-disp-ethdr",
> .data = (void *)MTK_DISP_ETHDR },
> { }
> @@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> @@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_disp_pseudo_ovl_driver,
> &mtk_ethdr_driver,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..fc03cfda7601 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_disp_pseudo_ovl_driver;
> extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
The pitch is got in mtk_plane_atomic_update(), isn't it?
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
mtk_ddp_write(cmdq_pkt, cfg->addr0, cmdq_base, base, MDP_RDMA_SRC_BASE_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
mtk_ddp_write(cmdq_pkt, offset_y, cmdq_base, base, MDP_RDMA_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
> +
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-20 5:57 ` CK Hu
0 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-20 5:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, singo.chang, srv_heupstream
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
> layers. The four layers are blending at the EHTDR module next to it.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
> 10 files changed, 1453 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fcce08710cef..70b53487ab0c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_ethdr.o
> + mtk_ethdr.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 7227ffbc3eae..f5d35007b84d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
> +
> int mtk_ethdr_clk_enable(struct device *dev);
> void mtk_ethdr_clk_disable(struct device *dev);
> void mtk_ethdr_config(struct device *dev, unsigned int w,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..8ec80e1887e0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,655 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_ethdr.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
> +#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
> +#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
> +#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + struct cmdq_client_reg top_cmdq_base;
> + void __iomem *top_regs;
> + const struct pseudo_ovl_data *data;
> + struct device *next_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static const unsigned int merge_async_offset[] = {
> + VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
> +};
> +
> +static const unsigned int merge_async_reset_bit[] = {
> + BIT(25), BIT(26), BIT(27), BIT(28)};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
case CFG12_10_10_1PI_2PO_BUF_MODE :
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
mtk_ddp_write(cmdq_pkt, merge_cfg->in_h << 16 |merge_cfg->in_w[0],
&comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + break;
> + case 18:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
> + break;
> + default:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
> + break;
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, ~0);
> +}
> +
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + return pseudo_ovl->data->layer_nr;
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
> + &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
> + merge_async_offset[idx], ~0);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
> + mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
> + &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
> +
> + pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + return 0;
> +}
> +
> +static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
> + .bind = mtk_disp_pseudo_ovl_bind,
> + .unbind = mtk_disp_pseudo_ovl_unbind,
> +};
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
> + if (ret != 0) {
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
> + }
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
Now only one SoC, so remove this driver data.
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
> +
> +static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 3fa86f12feb4..64cbb9e1cc83 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_pseudo_ovl_clk_enable,
> + .clk_disable = mtk_pseudo_ovl_clk_disable,
> + .config = mtk_pseudo_ovl_config,
> + .start = mtk_pseudo_ovl_start,
> + .stop = mtk_pseudo_ovl_stop,
> + .layer_nr = mtk_pseudo_ovl_layer_nr,
> + .layer_config = mtk_pseudo_ovl_layer_config,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> .clk_enable = mtk_ethdr_clk_enable,
> .clk_disable = mtk_ethdr_clk_disable,
> @@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
> return 0;
> }
>
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
> +{
> + struct mtk_drm_private *private = drm->dev_private;
> + const enum mtk_ddp_comp_id *path;
> + unsigned int path_len = 0;
> + int i;
> +
> + if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
> + private->data->main_len,
> + private->ddp_comp)) {
> + path_len = private->data->main_len;
> + path = private->data->main_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
> + private->data->ext_len,
> + private->ddp_comp)) {
> + path_len = private->data->ext_len;
> + path = private->data->ext_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
> + private->data->third_len,
> + private->ddp_comp)) {
> + path_len = private->data->third_len;
> + path = private->data->third_path;
> + }
> +
> + if (!path_len)
> + return NULL;
> +
> + for (i = 0U; i < path_len; i++)
> + if (dev == private->ddp_comp[path[i]].dev)
> + break;
> +
> + if (i < (path_len - 1))
> + return private->ddp_comp[path[i + 1]].dev;
> + else
> + return NULL;
> +}
> +
> int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id)
> {
> @@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index f55efba6e744..ec84dc258124 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> MTK_DISP_ETHDR,
> + MTK_DISP_PSEUDO_OVL,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> @@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
> struct device *dev);
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm,
> + struct device *dev);
> int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id);
> enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index ace958a34bb5..ddc26160dea1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { .compatible = "mediatek,mt8195-disp-ethdr",
> .data = (void *)MTK_DISP_ETHDR },
> { }
> @@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> @@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_disp_pseudo_ovl_driver,
> &mtk_ethdr_driver,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..fc03cfda7601 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_disp_pseudo_ovl_driver;
> extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
The pitch is got in mtk_plane_atomic_update(), isn't it?
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
mtk_ddp_write(cmdq_pkt, cfg->addr0, cmdq_base, base, MDP_RDMA_SRC_BASE_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
mtk_ddp_write(cmdq_pkt, offset_y, cmdq_base, base, MDP_RDMA_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
> +
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 07/10] drm/mediatek: add pseudo ovl support for MT8195
@ 2021-07-20 5:57 ` CK Hu
0 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-20 5:57 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, dri-devel,
Yongqiang Niu, Rob Herring, linux-mediatek, Matthias Brugger,
linux-arm-kernel
Hi, Nancy:
On Sat, 2021-07-17 at 17:04 +0800, Nancy.Lin wrote:
> Add pseudo ovl module files:
> Pseudo ovl is an encapsulated module and designed for simplified
> DRM control flow. This module is composed of 8 RDMAs and 4 MERGEs.
> Two RDMAs merge into one layer, so this module support 4
> layers. The four layers are blending at the EHTDR module next to it.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 4 +-
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +
> .../gpu/drm/mediatek/mtk_disp_pseudo_ovl.c | 655 ++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 50 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 456 ++++++++++++
> drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 109 +++
> drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h | 160 +++++
> 10 files changed, 1453 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index fcce08710cef..70b53487ab0c 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -14,7 +14,9 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_drm_plane.o \
> mtk_dsi.o \
> mtk_dpi.o \
> - mtk_ethdr.o
> + mtk_ethdr.o \
> + mtk_disp_pseudo_ovl.o \
> + mtk_mdp_rdma.o
>
> obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 7227ffbc3eae..f5d35007b84d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -105,6 +105,18 @@ void mtk_rdma_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_pseudo_ovl_clk_enable(struct device *dev);
> +void mtk_pseudo_ovl_clk_disable(struct device *dev);
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_pseudo_ovl_start(struct device *dev);
> +void mtk_pseudo_ovl_stop(struct device *dev);
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt);
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev);
> +
> int mtk_ethdr_clk_enable(struct device *dev);
> void mtk_ethdr_clk_disable(struct device *dev);
> void mtk_ethdr_config(struct device *dev, unsigned int w,
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> new file mode 100644
> index 000000000000..8ec80e1887e0
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_pseudo_ovl.c
> @@ -0,0 +1,655 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_mdp_rdma.h"
> +#include "mtk_ethdr.h"
> +
> +#define DISP_MERGE_ENABLE 0x0
> + #define MERGE_ENABLE BIT(0)
> +#define DISP_MERGE_CFG_0 0x10
> +#define DISP_MERGE_CFG_1 0x14
> +#define DISP_MERGE_CFG_4 0x20
> +#define DISP_MERGE_CFG_5 0x24
> +#define DISP_MERGE_CFG_10 0x38
> + #define CFG_10_NO_SWAP 0
> +#define DISP_MERGE_CFG_12 0x40
> + #define CFG12_10_10_1PI_2PO_BUF_MODE 6
> + #define CFG12_11_10_1PI_2PO_MERGE 18
> +#define DISP_MERGE_CFG_24 0x70
> +#define DISP_MERGE_CFG_25 0x74
> +#define DISP_MERGE_CFG_26 0x78
> +#define DISP_MERGE_CFG_27 0x7c
> +#define DISP_MERGE_MUTE_0 0xf00
> +
> +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> +#define VDO1_CONFIG_MERGE0_ASYNC_CFG_WD 0xe30
> +#define VDO1_CONFIG_MERGE1_ASYNC_CFG_WD 0xe40
> +#define VDO1_CONFIG_MERGE2_ASYNC_CFG_WD 0xe50
> +#define VDO1_CONFIG_MERGE3_ASYNC_CFG_WD 0xe60
> +
> +#define MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH 1920
> +
> +enum mtk_pseudo_ovl_comp_type {
> + PSEUDO_OVL_TYPE_RDMA = 0,
> + PSEUDO_OVL_TYPE_MERGE,
> + PSEUDO_OVL_TYPE_NUM,
> +};
> +
> +enum mtk_pseudo_ovl_comp_id {
> + PSEUDO_OVL_RDMA_BASE = 0,
> + PSEUDO_OVL_MDP_RDMA0 = PSEUDO_OVL_RDMA_BASE,
> + PSEUDO_OVL_MDP_RDMA1,
> + PSEUDO_OVL_MDP_RDMA2,
> + PSEUDO_OVL_MDP_RDMA3,
> + PSEUDO_OVL_MDP_RDMA4,
> + PSEUDO_OVL_MDP_RDMA5,
> + PSEUDO_OVL_MDP_RDMA6,
> + PSEUDO_OVL_MDP_RDMA7,
> + PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE0 = PSEUDO_OVL_MERGE_BASE,
> + PSEUDO_OVL_MERGE1,
> + PSEUDO_OVL_MERGE2,
> + PSEUDO_OVL_MERGE3,
> + PSEUDO_OVL_ID_MAX
> +};
> +
> +struct pseudo_ovl_data {
> + unsigned int layer_nr;
> + struct mtk_mdp_rdma_fifo fifo;
> +};
> +
> +struct pseudo_ovl_comp_match {
> + enum mtk_pseudo_ovl_comp_type type;
> + int alias_id;
> +};
> +
> +struct pseudo_ovl_merge_config {
> + unsigned int fmt;
> + unsigned int merge_mode;
> + unsigned int in_w[2];
> + unsigned int out_w[2];
> + unsigned int in_h;
> +};
> +
> +struct mtk_pseudo_ovl_comp {
> + struct device *dev;
> + struct clk *clks[2];
> + struct cmdq_client_reg cmdq_base;
> + void __iomem *regs;
> +};
> +
> +struct mtk_disp_pseudo_ovl {
> + struct mtk_pseudo_ovl_comp pseudo_ovl_comp[PSEUDO_OVL_ID_MAX];
> + struct cmdq_client_reg top_cmdq_base;
> + void __iomem *top_regs;
> + const struct pseudo_ovl_data *data;
> + struct device *next_dev;
> +};
> +
> +static const char * const pseudo_ovl_comp_str[] = {
> + "PSEUDO_OVL_MDP_RDMA0",
> + "PSEUDO_OVL_MDP_RDMA1",
> + "PSEUDO_OVL_MDP_RDMA2",
> + "PSEUDO_OVL_MDP_RDMA3",
> + "PSEUDO_OVL_MDP_RDMA4",
> + "PSEUDO_OVL_MDP_RDMA5",
> + "PSEUDO_OVL_MDP_RDMA6",
> + "PSEUDO_OVL_MDP_RDMA7",
> + "PSEUDO_OVL_MERGE0",
> + "PSEUDO_OVL_MERGE1",
> + "PSEUDO_OVL_MERGE2",
> + "PSEUDO_OVL_MERGE3",
> + "PSEUDO_OVL_ID_MAX"
> +};
> +
> +static const char * const private_comp_stem[PSEUDO_OVL_TYPE_NUM] = {
> + [PSEUDO_OVL_TYPE_RDMA] = "vdo1_rdma",
> + [PSEUDO_OVL_TYPE_MERGE] = "merge",
> +};
> +
> +static const struct pseudo_ovl_comp_match comp_matches[PSEUDO_OVL_ID_MAX] = {
> + [PSEUDO_OVL_MDP_RDMA0] = { PSEUDO_OVL_TYPE_RDMA, 0 },
> + [PSEUDO_OVL_MDP_RDMA1] = { PSEUDO_OVL_TYPE_RDMA, 1 },
> + [PSEUDO_OVL_MDP_RDMA2] = { PSEUDO_OVL_TYPE_RDMA, 2 },
> + [PSEUDO_OVL_MDP_RDMA3] = { PSEUDO_OVL_TYPE_RDMA, 3 },
> + [PSEUDO_OVL_MDP_RDMA4] = { PSEUDO_OVL_TYPE_RDMA, 4 },
> + [PSEUDO_OVL_MDP_RDMA5] = { PSEUDO_OVL_TYPE_RDMA, 5 },
> + [PSEUDO_OVL_MDP_RDMA6] = { PSEUDO_OVL_TYPE_RDMA, 6 },
> + [PSEUDO_OVL_MDP_RDMA7] = { PSEUDO_OVL_TYPE_RDMA, 7 },
> + [PSEUDO_OVL_MERGE0] = { PSEUDO_OVL_TYPE_MERGE, 1 },
> + [PSEUDO_OVL_MERGE1] = { PSEUDO_OVL_TYPE_MERGE, 2 },
> + [PSEUDO_OVL_MERGE2] = { PSEUDO_OVL_TYPE_MERGE, 3 },
> + [PSEUDO_OVL_MERGE3] = { PSEUDO_OVL_TYPE_MERGE, 4 },
> +};
> +
> +static const unsigned int merge_async_offset[] = {
> + VDO1_CONFIG_MERGE0_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE1_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE2_ASYNC_CFG_WD,
> + VDO1_CONFIG_MERGE3_ASYNC_CFG_WD,
> +};
> +
> +static const unsigned int merge_async_reset_bit[] = {
> + BIT(25), BIT(26), BIT(27), BIT(28)};
> +
> +static int mtk_pseudo_ovl_fifo_setting(struct mtk_disp_pseudo_ovl *pseudo_ovl,
> + struct cmdq_pkt *handle)
> +{
> + struct mtk_pseudo_ovl_comp *rdma = NULL;
> + const struct pseudo_ovl_data *data = pseudo_ovl->data;
> + const struct mtk_mdp_rdma_fifo *fifo = &data->fifo;
> + int i;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i <= PSEUDO_OVL_MDP_RDMA7; i++) {
> + rdma = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + i];
> + mtk_mdp_rdma_fifo_config(rdma->regs, handle, &rdma->cmdq_base, fifo);
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_pseudo_ovl_merge_config(struct mtk_pseudo_ovl_comp *comp,
> + struct pseudo_ovl_merge_config *merge_cfg,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + switch (merge_cfg->merge_mode) {
> + case 6:
case CFG12_10_10_1PI_2PO_BUF_MODE :
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
mtk_ddp_write(cmdq_pkt, merge_cfg->in_h << 16 |merge_cfg->in_w[0],
&comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + break;
> + case 18:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_24, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_25, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_26, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_27, ~0);
> + break;
> + default:
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_0, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->in_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_1, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[0]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_4, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, (merge_cfg->in_h << 16 | merge_cfg->out_w[1]),
> + &comp->cmdq_base, comp->regs, DISP_MERGE_CFG_5, ~0);
> + break;
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, merge_cfg->merge_mode, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_12, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, CFG_10_NO_SWAP, &comp->cmdq_base,
> + comp->regs, DISP_MERGE_CFG_10, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 1, &comp->cmdq_base, comp->regs,
> + DISP_MERGE_ENABLE, ~0);
> +}
> +
> +unsigned int mtk_pseudo_ovl_layer_nr(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + return pseudo_ovl->data->layer_nr;
> +}
> +
> +void mtk_pseudo_ovl_layer_config(struct device *dev, unsigned int idx,
> + struct mtk_plane_state *state,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_plane_pending_state *pending = &state->pending;
> + struct pseudo_ovl_merge_config merge_cfg = {0};
> + struct mtk_mdp_rdma_cfg rdma_config = {0};
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + const struct drm_format_info *fmt_info = drm_format_info(pending->format);
> + bool use_dual_pipe = false;
> +
> + dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
> + pending->enable, pending->format);
> + dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
> + pending->addr, (pending->pitch / fmt_info->cpp[0]),
> + pending->x, pending->y, pending->width, pending->height);
> +
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * idx + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + idx];
> +
> + if (!pending->enable) {
> + mtk_ethdr_layer_off(pseudo_ovl->next_dev, idx, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_mdp_rdma_stop(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + return;
> + }
> +
> + if (pending->width > MTK_PSEUDO_OVL_SINGLE_PIPE_MAX_WIDTH)
> + use_dual_pipe = true;
> +
> + merge_cfg.out_w[0] = pending->width;
> + merge_cfg.in_h = pending->height;
> + merge_cfg.fmt = pending->format;
> + if (use_dual_pipe) {
> + merge_cfg.merge_mode = CFG12_11_10_1PI_2PO_MERGE;
> + merge_cfg.in_w[0] = (pending->width / 2) + ((pending->width / 2) % 2);
> + merge_cfg.in_w[1] = (pending->width / 2) - ((pending->width / 2) % 2);
> + } else {
> + merge_cfg.merge_mode = CFG12_10_10_1PI_2PO_BUF_MODE;
> + merge_cfg.in_w[0] = pending->width;
> + }
> +
> + mtk_pseudo_ovl_merge_config(merge, &merge_cfg, cmdq_pkt);
> + mtk_ddp_write_mask(cmdq_pkt, (pending->height << 16 | (pending->width / 2)),
> + &pseudo_ovl->top_cmdq_base, pseudo_ovl->top_regs,
> + merge_async_offset[idx], ~0);
> +
> + rdma_config.source_width = pending->pitch / fmt_info->cpp[0];
> + rdma_config.csc_enable = fmt_info->is_yuv ? true : false;
> + rdma_config.profile = RDMA_CSC_FULL709_TO_RGB;
> + rdma_config.encode_type = RDMA_ENCODE_NONE;
> + rdma_config.block_size = RDMA_BLOCK_NONE;
> + rdma_config.width = merge_cfg.in_w[0];
> + rdma_config.height = pending->height;
> + rdma_config.addr0 = pending->addr;
> + rdma_config.fmt = pending->format;
> + mtk_mdp_rdma_config(rdma_l->regs, &rdma_config, cmdq_pkt, &rdma_l->cmdq_base);
> +
> + rdma_config.x_left = merge_cfg.in_w[0];
> + rdma_config.width = merge_cfg.in_w[1];
> + mtk_mdp_rdma_config(rdma_r->regs, &rdma_config, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ddp_write_mask(cmdq_pkt, 0x1, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_ENABLE, 0x1);
> + mtk_ddp_write_mask(cmdq_pkt, 0x0, &merge->cmdq_base, merge->regs,
> + DISP_MERGE_MUTE_0, 0x1);
> +
> + mtk_mdp_rdma_start(rdma_l->regs, cmdq_pkt, &rdma_l->cmdq_base);
> + if (use_dual_pipe)
> + mtk_mdp_rdma_start(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> + else
> + mtk_mdp_rdma_stop(rdma_r->regs, cmdq_pkt, &rdma_r->cmdq_base);
> +
> + mtk_ethdr_layer_config(pseudo_ovl->next_dev, idx, state, cmdq_pkt);
> + mtk_ethdr_layer_on(pseudo_ovl->next_dev, idx, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_config(struct device *dev, unsigned int w, unsigned int h,
> + unsigned int vrefresh, unsigned int bpc,
> + struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> +
> + dev_info(dev, "%s w:%d, h:%d\n", __func__, w, h);
> + mtk_pseudo_ovl_fifo_setting(pseudo_ovl, cmdq_pkt);
> +}
> +
> +void mtk_pseudo_ovl_start(struct device *dev)
> +{
> +}
> +
> +void mtk_pseudo_ovl_stop(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *rdma_l;
> + struct mtk_pseudo_ovl_comp *rdma_r;
> + struct mtk_pseudo_ovl_comp *merge;
> + unsigned int reg;
> + u32 i;
> +
> + for (i = 0; i < pseudo_ovl->data->layer_nr; i++) {
> + rdma_l = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i];
> + rdma_r = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_RDMA_BASE + 2 * i + 1];
> + merge = &pseudo_ovl->pseudo_ovl_comp[PSEUDO_OVL_MERGE_BASE + i];
> +
> + mtk_mdp_rdma_stop(rdma_l->regs, NULL, &rdma_l->cmdq_base);
> + mtk_mdp_rdma_stop(rdma_r->regs, NULL, &rdma_r->cmdq_base);
> +
> + reg = readl(merge->regs + DISP_MERGE_ENABLE);
> + reg = reg & ~MERGE_ENABLE;
> + writel_relaxed(reg, merge->regs + DISP_MERGE_ENABLE);
> +
> + mtk_ddp_write_mask(NULL, 0, &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + mtk_ddp_write_mask(NULL, merge_async_reset_bit[i],
> + &pseudo_ovl->top_cmdq_base,
> + pseudo_ovl->top_regs, VDO1_CONFIG_SW0_RST_B,
> + merge_async_reset_bit[i]);
> + }
> +}
> +
> +int mtk_pseudo_ovl_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + /* Need to power on for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_get_sync(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power on, err %d-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> +
> + for (j = 0; j < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> +
> + ret = clk_prepare_enable(comp->clks[j]);
> + if (ret)
> + dev_err(dev,
> + "Failed to enable clock %d, err %d-%s\n",
> + i, ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +
> + return ret;
> +}
> +
> +void mtk_pseudo_ovl_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct mtk_pseudo_ovl_comp *comp;
> + int ret;
> + int i;
> + int j;
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_ID_MAX; i++) {
> + comp = &pseudo_ovl->pseudo_ovl_comp[i];
> + if (!comp->dev)
> + continue;
> +
> + for (j = 0; i < ARRAY_SIZE(comp->clks); j++) {
> + if (IS_ERR(comp->clks[j]))
> + break;
> + clk_disable_unprepare(comp->clks[j]);
> + }
> +
> + /* Need to power off for private rdma devices */
> + if (i < PSEUDO_OVL_MERGE_BASE) {
> + ret = pm_runtime_put(comp->dev);
> + if (ret < 0)
> + dev_err(dev,
> + "Failed to power off, err-%s\n",
> + ret, pseudo_ovl_comp_str[i]);
> + }
> + }
> +}
> +
> +static int mtk_disp_pseudo_ovl_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> + struct device *mmsys_dev = drm_private->mmsys_dev;
> +
> + pseudo_ovl->next_dev = mtk_drm_find_next_comp(drm_dev, dev);
> +
> + pseudo_ovl->top_regs = of_iomap(mmsys_dev->of_node, 0);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_dev_get_client_reg(mmsys_dev, &pseudo_ovl->top_cmdq_base, 0))
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + return 0;
> +}
> +
> +static void mtk_disp_pseudo_ovl_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_pseudo_ovl_component_ops = {
> + .bind = mtk_disp_pseudo_ovl_bind,
> + .unbind = mtk_disp_pseudo_ovl_unbind,
> +};
> +
> +static int pseudo_ovl_comp_get_id(struct device *dev, struct device_node *node,
> + enum mtk_pseudo_ovl_comp_type type)
> +{
> + int alias_id = of_alias_get_id(node, private_comp_stem[type]);
> + int ret;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(comp_matches); i++)
> + if (comp_matches[i].type == type &&
> + comp_matches[i].alias_id == alias_id)
> + return i;
> +
> + dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
> + return -EINVAL;
> +}
> +
> +static int private_comp_init(struct device *dev, struct device_node *node,
> + struct mtk_pseudo_ovl_comp *comp,
> + enum mtk_pseudo_ovl_comp_id id)
> +{
> + struct platform_device *comp_pdev;
> + int ret;
> + int i;
> +
> + if (id < 0 || id >= PSEUDO_OVL_ID_MAX) {
> + dev_err(dev, "Invalid component id %d\n", id);
> + return -EINVAL;
> + }
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "can't find platform device of node:%s\n",
> + node->name);
> + return -ENODEV;
> + }
> + comp->dev = &comp_pdev->dev;
> + comp->regs = of_iomap(node, 0);
> +
> + for (i = 0; i < ARRAY_SIZE(comp->clks); i++) {
> + comp->clks[i] = of_clk_get(node, i);
> + if (IS_ERR(comp->clks[i]))
> + break;
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_base, 0);
> + if (ret)
> + dev_info(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + if (id < PSEUDO_OVL_MERGE_BASE)
> + pm_runtime_enable(comp->dev);
> +
> + dev_info(dev, "[DRM]regs:0x%p, node:%s\n", comp->regs, pseudo_ovl_comp_str[id]);
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_probe(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_comp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_pseudo_ovl_comp_dt_ids[] = {
> + {
> + .compatible = "mediatek,mt8195-vdo1-rdma",
> + .data = (void *)PSEUDO_OVL_TYPE_RDMA,
> + }, {
> + .compatible = "mediatek,mt8195-vdo1-merge",
> + .data = (void *)PSEUDO_OVL_TYPE_MERGE,
> + },
> + {},
> +};
> +
> +static struct platform_driver mtk_disp_pseudo_ovl_comp_driver = {
> + .probe = mtk_disp_pseudo_ovl_comp_probe,
> + .remove = mtk_disp_pseudo_ovl_comp_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl-comp",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_pseudo_ovl_comp_dt_ids,
> + },
> +};
> +module_platform_driver(mtk_disp_pseudo_ovl_comp_driver);
> +
> +static int pseudo_ovl_comp_init(struct device *dev)
> +{
> + struct mtk_disp_pseudo_ovl *priv = dev_get_drvdata(dev);
> + struct device_node *node, *parent;
> + int i, ret;
> +
> + parent = dev->of_node->parent;
> +
> + for_each_child_of_node(parent, node) {
> + const struct of_device_id *of_id;
> + enum mtk_pseudo_ovl_comp_type type;
> + struct mtk_pseudo_ovl_comp *comp;
> + int id;
> +
> + of_id = of_match_node(mtk_pseudo_ovl_comp_dt_ids, node);
> + if (!of_id)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_info(dev, "Skipping disabled component %pOF\n",
> + node);
> + continue;
> + }
> +
> + type = (enum mtk_pseudo_ovl_comp_type)of_id->data;
> + id = pseudo_ovl_comp_get_id(dev, node, type);
> + if (id < 0) {
> + dev_warn(dev, "Skipping unknown component %pOF\n",
> + node);
> + continue;
> + }
> +
> + ret = private_comp_init(dev, node, &priv->pseudo_ovl_comp[id], id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_disp_pseudo_ovl_probe(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *priv;
> + struct device *dev = &pdev->dev;
> + int ret;
> + int i;
> +
> + dev_info(dev, "%s+\n", __func__);
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = pseudo_ovl_comp_init(dev);
> + if (ret) {
> + dev_notice(dev, "pseudo_ovl comp init fail\n");
> + return ret;
> + }
> +
> + ret = component_add(dev, &mtk_disp_pseudo_ovl_component_ops);
> + if (ret != 0) {
> + dev_notice(dev, "Failed to add component: %d\n", ret);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(priv->pseudo_ovl_comp[i].dev);
> + }
> + dev_info(dev, "%s-\n", __func__);
> + return ret;
> +}
> +
> +static int mtk_disp_pseudo_ovl_remove(struct platform_device *pdev)
> +{
> + struct mtk_disp_pseudo_ovl *pseudo_ovl = dev_get_drvdata(&pdev->dev);
> + int i;
> +
> + component_del(&pdev->dev, &mtk_disp_pseudo_ovl_component_ops);
> +
> + for (i = PSEUDO_OVL_MDP_RDMA0; i < PSEUDO_OVL_MERGE_BASE; i++)
> + pm_runtime_disable(pseudo_ovl->pseudo_ovl_comp[i].dev);
> +
> + return 0;
> +}
> +
> +static const struct pseudo_ovl_data mt8195_pseudo_ovl_driver_data = {
Now only one SoC, so remove this driver data.
> + .layer_nr = 4,
> + .fifo.read_request_type = 7,
> + .fifo.command_div = 1,
> + .fifo.ext_preutra_en = 1,
> + .fifo.ultra_en = 0,
> + .fifo.pre_ultra_en = 1,
> + .fifo.ext_ultra_en = 1,
> + .fifo.extrd_arb_max_0 = 3,
> + .fifo.buf_resv_size_0 = 0,
> + .fifo.issue_req_th_0 = 0,
> + .fifo.ultra_h_con_0 = 156,
> + .fifo.ultra_l_con_0 = 104,
> +};
> +
> +static const struct of_device_id mtk_disp_pseudo_ovl_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = &mt8195_pseudo_ovl_driver_data},
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_pseudo_ovl_driver_dt_match);
> +
> +struct platform_driver mtk_disp_pseudo_ovl_driver = {
> + .probe = mtk_disp_pseudo_ovl_probe,
> + .remove = mtk_disp_pseudo_ovl_remove,
> + .driver = {
> + .name = "mediatek-disp-pseudo-ovl",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_pseudo_ovl_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 3fa86f12feb4..64cbb9e1cc83 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -355,6 +355,16 @@ static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .start = mtk_ufoe_start,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_pseudo_ovl = {
> + .clk_enable = mtk_pseudo_ovl_clk_enable,
> + .clk_disable = mtk_pseudo_ovl_clk_disable,
> + .config = mtk_pseudo_ovl_config,
> + .start = mtk_pseudo_ovl_start,
> + .stop = mtk_pseudo_ovl_stop,
> + .layer_nr = mtk_pseudo_ovl_layer_nr,
> + .layer_config = mtk_pseudo_ovl_layer_config,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> .clk_enable = mtk_ethdr_clk_enable,
> .clk_disable = mtk_ethdr_clk_disable,
> @@ -377,6 +387,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> + [MTK_DISP_PSEUDO_OVL] = "pseudo_ovl",
> [MTK_DISP_PWM] = "pwm",
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> @@ -422,6 +433,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
> + [DDP_COMPONENT_PSEUDO_OVL] = { MTK_DISP_PSEUDO_OVL, 0, &ddp_pseudo_ovl },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> @@ -510,6 +522,43 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c
> return 0;
> }
>
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm, struct device *dev)
> +{
> + struct mtk_drm_private *private = drm->dev_private;
> + const enum mtk_ddp_comp_id *path;
> + unsigned int path_len = 0;
> + int i;
> +
> + if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
> + private->data->main_len,
> + private->ddp_comp)) {
> + path_len = private->data->main_len;
> + path = private->data->main_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
> + private->data->ext_len,
> + private->ddp_comp)) {
> + path_len = private->data->ext_len;
> + path = private->data->ext_path;
> + } else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
> + private->data->third_len,
> + private->ddp_comp)) {
> + path_len = private->data->third_len;
> + path = private->data->third_path;
> + }
> +
> + if (!path_len)
> + return NULL;
> +
> + for (i = 0U; i < path_len; i++)
> + if (dev == private->ddp_comp[path[i]].dev)
> + break;
> +
> + if (i < (path_len - 1))
> + return private->ddp_comp[path[i + 1]].dev;
> + else
> + return NULL;
> +}
> +
> int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id)
> {
> @@ -551,6 +600,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> + type == MTK_DISP_PSEUDO_OVL ||
> type == MTK_DISP_PWM ||
> type == MTK_DISP_RDMA ||
> type == MTK_DPI ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index f55efba6e744..ec84dc258124 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -37,6 +37,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_DSC,
> MTK_DISP_MERGE,
> MTK_DISP_ETHDR,
> + MTK_DISP_PSEUDO_OVL,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> @@ -192,6 +193,8 @@ int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
> struct device *dev);
> +struct device *mtk_drm_find_next_comp(struct drm_device *drm,
> + struct device *dev);
> int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
> enum mtk_ddp_comp_id comp_id);
> enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index ace958a34bb5..ddc26160dea1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -480,6 +480,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> + { .compatible = "mediatek,mt8195-disp-pseudo-ovl",
> + .data = (void *)MTK_DISP_PSEUDO_OVL },
> { .compatible = "mediatek,mt8195-disp-ethdr",
> .data = (void *)MTK_DISP_ETHDR },
> { }
> @@ -574,6 +576,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_PSEUDO_OVL ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DPI ||
> comp_type == MTK_DSI) {
> @@ -679,6 +682,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> &mtk_dsi_driver,
> + &mtk_disp_pseudo_ovl_driver,
> &mtk_ethdr_driver,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c87ebb5309d0..fc03cfda7601 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -55,6 +55,7 @@ extern struct platform_driver mtk_disp_dsc_driver;
> extern struct platform_driver mtk_disp_merge_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> +extern struct platform_driver mtk_disp_pseudo_ovl_driver;
> extern struct platform_driver mtk_ethdr_driver;
>
> #endif /* MTK_DRM_DRV_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> new file mode 100644
> index 000000000000..81d3cc4872eb
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include "mtk_drm_drv.h"
> +#include "mtk_mdp_reg_rdma.h"
> +#include "mtk_mdp_rdma.h"
> +
> +#define RDMA_INPUT_SWAP BIT(14)
> +#define RDMA_INPUT_10BIT BIT(18)
> +#define IRQ_INT_EN_ALL \
> + (REG_FLD_MASK(FLD_UNDERRUN_INT_EN) |\
> + REG_FLD_MASK(FLD_REG_UPDATE_INT_EN) |\
> + REG_FLD_MASK(FLD_FRAME_COMPLETE_INT_EN))
> +
> +static unsigned int rdma_get_y_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 2 * width;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 3 * width;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return 4 * width;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 2 * width;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_uv_pitch(unsigned int fmt, unsigned int width)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 4 * width;
> + }
> +}
> +
> +static unsigned int rdma_get_block_h(unsigned int mode)
> +{
> + switch (mode) {
> + default:
> + return 0;
> + case RDMA_BLOCK_8x8:
> + case RDMA_BLOCK_16x8:
> + case RDMA_BLOCK_32x8:
> + return 8;
> + case RDMA_BLOCK_8x16:
> + case RDMA_BLOCK_16x16:
> + case RDMA_BLOCK_32x16:
> + return 16;
> + case RDMA_BLOCK_8x32:
> + case RDMA_BLOCK_16x32:
> + case RDMA_BLOCK_32x32:
> + return 32;
> + }
> +}
> +
> +static unsigned int rdma_get_horizontal_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_vertical_shift_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 1;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_y(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + return 16;
> + case DRM_FORMAT_RGB888:
> + case DRM_FORMAT_BGR888:
> + return 24;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return 32;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_YUYV:
> + return 16;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 8;
> + }
> +}
> +
> +static unsigned int rdma_get_bits_per_pixel_uv(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + return 0;
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_NV21:
> + return 16;
> + }
> +}
> +
> +static bool with_alpha(uint32_t format)
> +{
> + const struct drm_format_info *fmt_info = drm_format_info(format);
> +
> + return fmt_info->has_alpha;
> +}
> +
> +static unsigned int rdma_fmt_convert(unsigned int fmt)
> +{
> + switch (fmt) {
> + default:
> + case DRM_FORMAT_RGB565:
> + return RDMA_INPUT_FORMAT_RGB565;
> + case DRM_FORMAT_BGR565:
> + return RDMA_INPUT_FORMAT_RGB565 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGB888:
> + return RDMA_INPUT_FORMAT_RGB888;
> + case DRM_FORMAT_BGR888:
> + return RDMA_INPUT_FORMAT_RGB888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888;
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_ARGB8888:
> + return RDMA_INPUT_FORMAT_RGBA8888;
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP;
> + case DRM_FORMAT_ABGR2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_ARGB2101010:
> + return RDMA_INPUT_FORMAT_RGBA8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_RGBA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_SWAP |
> + RDMA_INPUT_10BIT;
> + case DRM_FORMAT_BGRA1010102:
> + return RDMA_INPUT_FORMAT_ARGB8888 | RDMA_INPUT_10BIT;
> + case DRM_FORMAT_UYVY:
> + return RDMA_INPUT_FORMAT_UYVY;
> + case DRM_FORMAT_YUYV:
> + return RDMA_INPUT_FORMAT_YUY2;
> + }
> +}
> +
> +void mtk_mdp_rdma_start(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int inten = IRQ_INT_EN_ALL;
> +
> + mtk_ddp_write_mask(cmdq_pkt, inten, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 1), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> +}
> +
> +void mtk_mdp_rdma_stop(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_ROT_ENABLE, 0), cmdq_base,
> + base, MDP_RDMA_EN, REG_FLD_MASK(FLD_ROT_ENABLE));
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_ENABLE, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base,
> + MDP_RDMA_INTERRUPT_STATUS, IRQ_INT_EN_ALL);
> + mtk_ddp_write_mask(cmdq_pkt, 1, cmdq_base, base, MDP_RDMA_RESET, ~0);
> + mtk_ddp_write_mask(cmdq_pkt, 0, cmdq_base, base, MDP_RDMA_RESET, ~0);
> +}
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base, struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo)
> +{
> + int reg;
> + int reg_val;
> + int reg_mask;
> +
> + reg = MDP_RDMA_GMCIF_CON;
> + reg_val = REG_FLD_VAL(FLD_RD_REQ_TYPE, fifo->read_request_type) |
> + REG_FLD_VAL(FLD_COMMAND_DIV, fifo->command_div) |
> + REG_FLD_VAL(FLD_EXT_PREULTRA_EN, fifo->ext_preutra_en) |
> + REG_FLD_VAL(FLD_ULTRA_EN, fifo->ultra_en) |
> + REG_FLD_VAL(PRE_ULTRA_EN, fifo->pre_ultra_en) |
> + REG_FLD_VAL(FLD_EXT_ULTRA_EN, fifo->ext_ultra_en);
> + reg_mask = REG_FLD_MASK(FLD_RD_REQ_TYPE) |
> + REG_FLD_MASK(FLD_COMMAND_DIV) |
> + REG_FLD_MASK(FLD_EXT_PREULTRA_EN) |
> + REG_FLD_MASK(FLD_ULTRA_EN) |
> + REG_FLD_MASK(PRE_ULTRA_EN) |
> + REG_FLD_MASK(FLD_EXT_ULTRA_EN);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMA_CON_0;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX, fifo->extrd_arb_max_0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE, fifo->buf_resv_size_0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH, fifo->issue_req_th_0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_H_OFS_0, fifo->ultra_h_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_H_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_L_CON_0;
> + reg_val = REG_FLD_VAL(FLD_PREUTRA_L_OFS_0, fifo->ultra_l_con_0);
> + reg_mask = REG_FLD_MASK(FLD_PREUTRA_L_OFS_0);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_1;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_1, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_1, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_1) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_1) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_HIGH_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_1;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_1, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_1);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_2;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_2, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_2, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_2) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_2) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_2;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_2, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_2);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_DMABUF_CON_3;
> + reg_val = REG_FLD_VAL(FLD_EXTRD_ARB_MAX_3, 0) |
> + REG_FLD_VAL(FLD_BUF_RESV_SIZE_3, 0) |
> + REG_FLD_VAL(FLD_ISSUE_REQ_TH_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_EXTRD_ARB_MAX_3) |
> + REG_FLD_MASK(FLD_BUF_RESV_SIZE_3) |
> + REG_FLD_MASK(FLD_ISSUE_REQ_TH_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_UTRA_H_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_HIGH_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_HIGH_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +
> + reg = MDP_RDMA_ULTRA_TH_LOW_CON_3;
> + reg_val = REG_FLD_VAL(FLD_PRE_ULTRA_TH_LOW_OFS_3, 0);
> + reg_mask = REG_FLD_MASK(FLD_PRE_ULTRA_TH_LOW_OFS_3);
> + mtk_ddp_write_mask(cmdq_pkt, reg_val, cmdq_base, base, reg, reg_mask);
> +}
> +
> +void mtk_mdp_rdma_config(void __iomem *base, struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base)
> +{
> + unsigned int src_pitch_uv = rdma_get_uv_pitch(cfg->fmt, cfg->source_width);
> + unsigned int src_pitch_y = rdma_get_y_pitch(cfg->fmt, cfg->source_width);
The pitch is got in mtk_plane_atomic_update(), isn't it?
> + unsigned int h_shift_uv = rdma_get_horizontal_shift_uv(cfg->fmt);
> + unsigned int v_shift_uv = rdma_get_vertical_shift_uv(cfg->fmt);
> + unsigned int bpp_uv = rdma_get_bits_per_pixel_uv(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int block_h = rdma_get_block_h(cfg->block_size);
block_h = 0;
> + unsigned int bpp_y = rdma_get_bits_per_pixel_y(cfg->fmt);
I think drm_format_info() could get this info.
> + unsigned int y_start_line = 0;
> + unsigned int offset_y = 0;
> + unsigned int offset_u = 0;
> + unsigned int offset_v = 0;
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UNIFORM_CONFIG, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_UNIFORM_CONFIG));
> + mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), cmdq_base,
> + base, MDP_RDMA_SRC_CON, REG_FLD_MASK(FLD_SWAP) |
> + REG_FLD_MASK(FLD_SRC_FORMAT) |
> + REG_FLD_MASK(FLD_BIT_NUMBER));
> +
> + if (!cfg->csc_enable && with_alpha(cfg->fmt))
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 1),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> + else
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_ARGB, 0),
> + cmdq_base, base, MDP_RDMA_SRC_CON,
> + REG_FLD_MASK(FLD_OUTPUT_ARGB));
> +
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_0, REG_FLD_MASK(FLD_SRC_BASE_0));
mtk_ddp_write(cmdq_pkt, cfg->addr0, cmdq_base, base, MDP_RDMA_SRC_BASE_0);
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr1, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_1, REG_FLD_MASK(FLD_SRC_BASE_1));
> + mtk_ddp_write_mask(cmdq_pkt, cfg->addr2, cmdq_base, base,
> + MDP_RDMA_SRC_BASE_2, REG_FLD_MASK(FLD_SRC_BASE_2));
> +
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, cmdq_base, base,
> + MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_MF_BKGD_WB));
> + mtk_ddp_write_mask(cmdq_pkt, src_pitch_uv, cmdq_base, base,
> + MDP_RDMA_SF_BKGD_SIZE_IN_BYTE,
> + REG_FLD_MASK(FLD_SF_BKGD_WB));
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_BKGD_WP, cfg->source_width),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_MF_BKGD_WP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_BKGD_HP, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL,
> + REG_FLD_MASK(FLD_BKGD_HP));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 1),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 1), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + } else {
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_YUV_TRANSFORM, 0),
> + cmdq_base, base, MDP_RDMA_COMP_CON,
> + REG_FLD_MASK(FLD_AFBC_YUV_TRANSFORM));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_UFBDC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_UFBDC_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_AFBC_EN, 0), cmdq_base,
> + base, MDP_RDMA_COMP_CON, REG_FLD_MASK(FLD_AFBC_EN));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_OUTPUT_10B, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_OUTPUT_10B));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SIMPLE_MODE, 1), cmdq_base,
> + base, MDP_RDMA_CON, REG_FLD_MASK(FLD_SIMPLE_MODE));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TRANS_EN, cfg->csc_enable),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_TRANS_EN));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_INT_MATRIX_SEL, cfg->profile),
> + cmdq_base, base, MDP_RDMA_TRANSFORM_0,
> + REG_FLD_MASK(FLD_INT_MATRIX_SEL));
> +
> + if (cfg->block_size == RDMA_BLOCK_NONE) {
> + y_start_line = cfg->y_top;
> +
> + offset_y = (cfg->x_left * bpp_y >> 3) + y_start_line * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * bpp_uv >> 3) +
> + (y_start_line >> v_shift_uv) * src_pitch_uv;
> + } else {
Never be here, so remove.
> + offset_y = (cfg->x_left * block_h * bpp_y >> 3) +
> + (cfg->y_top) * src_pitch_y;
> + offset_u = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + offset_v = ((cfg->x_left >> h_shift_uv) * (block_h >> v_shift_uv) *
> + bpp_uv >> 3) + (cfg->y_top) * src_pitch_uv;
> + }
> +
> + if (cfg->encode_type == RDMA_ENCODE_AFBC) {
Never be here, so remove.
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_WP, cfg->x_left),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_WP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_WP));
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_HP, cfg->y_top),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_HP,
> + REG_FLD_MASK(FLD_SRC_OFFSET_HP));
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_0, offset_y),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_0,
> + REG_FLD_MASK(FLD_SRC_OFFSET_0));
mtk_ddp_write(cmdq_pkt, offset_y, cmdq_base, base, MDP_RDMA_SRC_OFFSET_0);
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_1, offset_u),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_1,
> + REG_FLD_MASK(FLD_SRC_OFFSET_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_SRC_OFFSET_2, offset_v),
> + cmdq_base, base, MDP_RDMA_SRC_OFFSET_2,
> + REG_FLD_MASK(FLD_SRC_OFFSET_2));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_SRC_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_SRC_SIZE,
> + REG_FLD_MASK(FLD_MF_SRC_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_W, cfg->width),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_W));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_CLIP_H, cfg->height),
> + cmdq_base, base, MDP_RDMA_MF_CLIP_SIZE,
> + REG_FLD_MASK(FLD_MF_CLIP_H));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_W_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_W_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_MF_OFFSET_H_1, 0),
> + cmdq_base, base, MDP_RDMA_MF_OFFSET_1,
> + REG_FLD_MASK(FLD_MF_OFFSET_H_1));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_LINE_THRESHOLD, cfg->height),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_LINE_THRESHOLD));
> + mtk_ddp_write_mask(cmdq_pkt, REG_FLD_VAL(FLD_TARGET_LINE_EN, 1),
> + cmdq_base, base, MDP_RDMA_TARGET_LINE,
> + REG_FLD_MASK(FLD_TARGET_LINE_EN));
> +}
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> new file mode 100644
> index 000000000000..c16bfb716610
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h
> @@ -0,0 +1,109 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MDP_RDMA_H__
> +#define __MTK_MDP_RDMA_H__
> +
> +enum rdma_format {
> + RDMA_INPUT_FORMAT_RGB565 = 0,
> + RDMA_INPUT_FORMAT_RGB888 = 1,
> + RDMA_INPUT_FORMAT_RGBA8888 = 2,
> + RDMA_INPUT_FORMAT_ARGB8888 = 3,
> + RDMA_INPUT_FORMAT_UYVY = 4,
> + RDMA_INPUT_FORMAT_YUY2 = 5,
> + RDMA_INPUT_FORMAT_Y8 = 7,
> + RDMA_INPUT_FORMAT_YV12 = 8,
> + RDMA_INPUT_FORMAT_UYVY_3PL = 9,
> + RDMA_INPUT_FORMAT_NV12 = 12,
> + RDMA_INPUT_FORMAT_UYVY_2PL = 13,
> + RDMA_INPUT_FORMAT_Y410 = 14
> +};
> +
> +enum rdma_profile {
> + RDMA_CSC_RGB_TO_JPEG = 0,
> + RDMA_CSC_RGB_TO_FULL709 = 1,
> + RDMA_CSC_RGB_TO_BT601 = 2,
> + RDMA_CSC_RGB_TO_BT709 = 3,
> + RDMA_CSC_JPEG_TO_RGB = 4,
> + RDMA_CSC_FULL709_TO_RGB = 5,
> + RDMA_CSC_BT601_TO_RGB = 6,
> + RDMA_CSC_BT709_TO_RGB = 7,
> + RDMA_CSC_JPEG_TO_BT601 = 8,
> + RDMA_CSC_JPEG_TO_BT709 = 9,
> + RDMA_CSC_BT601_TO_JPEG = 10,
> + RDMA_CSC_BT709_TO_BT601 = 11,
> + RDMA_CSC_BT601_TO_BT709 = 12
> +};
> +
> +enum rdma_encode {
> + RDMA_ENCODE_NONE = 0,
> + RDMA_ENCODE_AFBC = 1,
> + RDMA_ENCODE_HYFBC = 2,
> + RDMA_ENCODE_UFO_DCP = 3
> +};
> +
> +enum rdma_block {
> + RDMA_BLOCK_NONE = 0,
> + RDMA_BLOCK_8x8 = 1,
> + RDMA_BLOCK_8x16 = 2,
> + RDMA_BLOCK_8x32 = 3,
> + RDMA_BLOCK_16x8 = 4,
> + RDMA_BLOCK_16x16 = 5,
> + RDMA_BLOCK_16x32 = 6,
> + RDMA_BLOCK_32x8 = 7,
> + RDMA_BLOCK_32x16 = 8,
> + RDMA_BLOCK_32x32 = 9
> +};
> +
> +struct mtk_mdp_rdma_cfg {
> + enum rdma_encode encode_type;
> + enum rdma_block block_size;
> + enum rdma_profile profile;
> + unsigned int source_width;
> + unsigned int addr0;
> + unsigned int addr1;
> + unsigned int addr2;
> + unsigned int width;
> + unsigned int height;
> + unsigned int x_left;
> + unsigned int y_top;
> + bool csc_enable;
> + int fmt;
> +};
> +
> +struct mtk_mdp_rdma_fifo {
> + int read_request_type;
> + int command_div;
> + int ext_preutra_en;
> + int ultra_en;
> + int pre_ultra_en;
> + int ext_ultra_en;
> + int extrd_arb_max_0;
> + int buf_resv_size_0;
> + int issue_req_th_0;
> + int ultra_h_con_0;
> + int ultra_l_con_0;
> +};
> +
> +void mtk_mdp_rdma_start(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_stop(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +void mtk_mdp_rdma_fifo_config(void __iomem *base,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base,
> + const struct mtk_mdp_rdma_fifo *fifo);
> +
> +void mtk_mdp_rdma_config(void __iomem *base,
> + struct mtk_mdp_rdma_cfg *cfg,
> + struct cmdq_pkt *cmdq_pkt,
> + struct cmdq_client_reg *cmdq_base);
> +
> +#endif // __MTK_MDP_RDMA_H__
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> new file mode 100644
> index 000000000000..08abd9f39bd8
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_mdp_reg_rdma.h
> @@ -0,0 +1,160 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __MDP_RDMA_REGS_H__
> +#define __MDP_RDMA_REGS_H__
> +
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> +#define MDP_RDMA_EN 0x000
> +#define FLD_ROT_ENABLE REG_FLD(1, 0)
> +
> +#define MDP_RDMA_RESET 0x008
> +
> +#define MDP_RDMA_INTERRUPT_ENABLE 0x010
> +#define FLD_UNDERRUN_INT_EN REG_FLD(1, 2)
> +#define FLD_REG_UPDATE_INT_EN REG_FLD(1, 1)
> +#define FLD_FRAME_COMPLETE_INT_EN REG_FLD(1, 0)
> +
> +#define MDP_RDMA_INTERRUPT_STATUS 0x018
> +
> +#define MDP_RDMA_CON 0x020
> +#define FLD_OUTPUT_10B REG_FLD(1, 5)
> +#define FLD_SIMPLE_MODE REG_FLD(1, 4)
> +
> +#define MDP_RDMA_GMCIF_CON 0x028
> +#define FLD_EXT_ULTRA_EN REG_FLD(1, 18)
> +#define PRE_ULTRA_EN REG_FLD(2, 16)
> +#define FLD_ULTRA_EN REG_FLD(2, 12)
> +#define FLD_RD_REQ_TYPE REG_FLD(4, 4)
> +#define FLD_EXT_PREULTRA_EN REG_FLD(1, 3)
> +#define FLD_COMMAND_DIV REG_FLD(1, 0)
> +
> +#define MDP_RDMA_SRC_CON 0x030
> +#define FLD_OUTPUT_ARGB REG_FLD(1, 25)
> +#define FLD_BIT_NUMBER REG_FLD(2, 18)
> +#define FLD_UNIFORM_CONFIG REG_FLD(1, 17)
> +#define FLD_SWAP REG_FLD(1, 14)
> +#define FLD_SRC_FORMAT REG_FLD(4, 0)
> +
> +#define MDP_RDMA_COMP_CON 0x038
> +#define FLD_AFBC_EN REG_FLD(1, 22)
> +#define FLD_AFBC_YUV_TRANSFORM REG_FLD(1, 21)
> +#define FLD_UFBDC_EN REG_FLD(1, 12)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
> +#define FLD_MF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_SIZE_IN_PIXEL 0x068
> +#define FLD_MF_BKGD_WP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_SRC_SIZE 0x070
> +#define FLD_MF_SRC_H REG_FLD(15, 16)
> +#define FLD_MF_SRC_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_CLIP_SIZE 0x078
> +#define FLD_MF_CLIP_H REG_FLD(15, 16)
> +#define FLD_MF_CLIP_W REG_FLD(15, 0)
> +
> +#define MDP_RDMA_MF_OFFSET_1 0x080
> +#define FLD_MF_OFFSET_H_1 REG_FLD(6, 16)
> +#define FLD_MF_OFFSET_W_1 REG_FLD(5, 0)
> +
> +#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
> +#define FLD_SF_BKGD_WB REG_FLD(23, 0)
> +
> +#define MDP_RDMA_MF_BKGD_H_SIZE_IN_PIXEL 0x098
> +#define FLD_BKGD_HP REG_FLD(23, 0)
> +
> +#define MDP_RDMA_TARGET_LINE 0x0a0
> +#define FLD_LINE_THRESHOLD REG_FLD(15, 17)
> +#define FLD_TARGET_LINE_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_SRC_OFFSET_0 0x118
> +#define FLD_SRC_OFFSET_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_1 0x120
> +#define FLD_SRC_OFFSET_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_2 0x128
> +#define FLD_SRC_OFFSET_2 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_WP 0x148
> +#define FLD_SRC_OFFSET_WP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_OFFSET_HP 0x150
> +#define FLD_SRC_OFFSET_HP REG_FLD(32, 0)
> +
> +#define MDP_RDMA_TRANSFORM_0 0x200
> +#define FLD_INT_MATRIX_SEL REG_FLD(5, 23)
> +#define FLD_TRANS_EN REG_FLD(1, 16)
> +
> +#define MDP_RDMA_DMA_CON_0 0x240
> +#define FLD_EXTRD_ARB_MAX REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE REG_FLD(8, 16)
> +#define FLD_ISSUE_REQ_TH REG_FLD(8, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_0 0x248
> +#define FLD_PREUTRA_H_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_UTRA_L_CON_0 0x250
> +#define FLD_PREUTRA_L_OFS_0 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_1 0x258
> +#define FLD_EXTRD_ARB_MAX_1 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_1 REG_FLD(7, 16)
> +#define FLD_ISSUE_REQ_TH_1 REG_FLD(7, 0)
> +
> +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_1 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_2 0x270
> +#define FLD_EXTRD_ARB_MAX_2 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_2 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_2 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_2 0x278
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_2 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_DMABUF_CON_3 0x288
> +#define FLD_EXTRD_ARB_MAX_3 REG_FLD(4, 24)
> +#define FLD_BUF_RESV_SIZE_3 REG_FLD(6, 16)
> +#define FLD_ISSUE_REQ_TH_3 REG_FLD(6, 0)
> +
> +#define MDP_RDMA_UTRA_H_CON_3 0x290
> +#define FLD_PRE_ULTRA_TH_HIGH_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298
> +#define FLD_PRE_ULTRA_TH_LOW_OFS_3 REG_FLD(10, 10)
> +
> +#define MDP_RDMA_SRC_BASE_0 0xf00
> +#define FLD_SRC_BASE_0 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_1 0xf08
> +#define FLD_SRC_BASE_1 REG_FLD(32, 0)
> +
> +#define MDP_RDMA_SRC_BASE_2 0xf10
> +#define FLD_SRC_BASE_2 REG_FLD(32, 0)
> +
> +#endif /* __MDP_RDMA_REGS_H__ */
> +
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
2021-07-18 23:22 ` Chun-Kuang Hu
(?)
@ 2021-07-22 0:59 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 0:59 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:22 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > 1. Add pseudo-ovl definition file for mt8195 display.
> > 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in
> > details.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,disp.yaml | 5 +
> > .../display/mediatek/mediatek,pseudo-ovl.yaml | 105
> > ++++++++++++++++++
> > 2 files changed, 110 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > index aac1796e3f6b..bb6d28572b48 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > @@ -230,6 +230,11 @@ properties:
> > - items:
> > - const: mediatek,mt8173-disp-od
> >
> > + # PSEUDO-OVL: see
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> > + # for details.
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > +
> > reg:
> > description: Physical base address and length of the function
> > block register space.
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > new file mode 100644
> > index 000000000000..9059d96ce70e
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > @@ -0,0 +1,105 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZuPFSKBk$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZgMaVN_K$
> >
> > +
> > +title: mediatek pseudo ovl Device Tree Bindings
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
> > + - Nancy.Lin <nancy.lin@mediatek.com>
> > +
> > +description: |
> > + The Mediatek pseudo ovl function block is composed of eight RDMA
> > and
> > + four MERGE devices. It's encapsulated as an overlay device,
> > which supports
> > + 4 layers.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + # pseudo ovl controller
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > + # RDMA: read DMA
> > + - items:
> > + - const: mediatek,mt8195-vdo1-rdma
> > + # MERGE: merge streams from two RDMA sources
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
> > + reg:
> > + maxItems: 1
> > + interrupts:
> > + maxItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
> > + maxItems: 1
> > + clocks:
> > + maxItems: 2
> > + clock-names:
> > + maxItems: 2
> > + power-domains:
> > + maxItems: 1
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const:
> > + - mediatek,mt8195-vdo1-merge
> > +
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: merge clock
> > + - description: merge async clock
> > + clock-names:
> > + items:
> > + - const: merge
> > + - const: merge_async
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + vdo1_rdma@1c104000 {
> > + compatible = "mediatek,mt8195-vdo1-rdma",
> > + "mediatek,mt8195-disp-pseudo-ovl";
>
> Do not create pseudo or virtual device, so just leave the
> "mediatek,mt8195-vdo1-rdma".
>
> Regards,
> Chun-Kuang.
>
OK, I will remove it.
> > + reg = <0 0x1c104000 0 0x1000>;
> > + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0x4000 0x1000>;
> > + };
> > +
> > + disp_vpp_merge@1c10c000 {
> > + compatible = "mediatek,mt8195-vdo1-merge";
> > + reg = <0 0x1c10c000 0 0x1000>;
> > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> > + clock-names = "merge","merge_async";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0xc000 0x1000>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
Regards,
Nancy Lin
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-22 0:59 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 0:59 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:22 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > 1. Add pseudo-ovl definition file for mt8195 display.
> > 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in
> > details.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,disp.yaml | 5 +
> > .../display/mediatek/mediatek,pseudo-ovl.yaml | 105
> > ++++++++++++++++++
> > 2 files changed, 110 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > index aac1796e3f6b..bb6d28572b48 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > @@ -230,6 +230,11 @@ properties:
> > - items:
> > - const: mediatek,mt8173-disp-od
> >
> > + # PSEUDO-OVL: see
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> > + # for details.
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > +
> > reg:
> > description: Physical base address and length of the function
> > block register space.
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > new file mode 100644
> > index 000000000000..9059d96ce70e
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > @@ -0,0 +1,105 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZuPFSKBk$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZgMaVN_K$
> >
> > +
> > +title: mediatek pseudo ovl Device Tree Bindings
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
> > + - Nancy.Lin <nancy.lin@mediatek.com>
> > +
> > +description: |
> > + The Mediatek pseudo ovl function block is composed of eight RDMA
> > and
> > + four MERGE devices. It's encapsulated as an overlay device,
> > which supports
> > + 4 layers.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + # pseudo ovl controller
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > + # RDMA: read DMA
> > + - items:
> > + - const: mediatek,mt8195-vdo1-rdma
> > + # MERGE: merge streams from two RDMA sources
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
> > + reg:
> > + maxItems: 1
> > + interrupts:
> > + maxItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
> > + maxItems: 1
> > + clocks:
> > + maxItems: 2
> > + clock-names:
> > + maxItems: 2
> > + power-domains:
> > + maxItems: 1
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const:
> > + - mediatek,mt8195-vdo1-merge
> > +
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: merge clock
> > + - description: merge async clock
> > + clock-names:
> > + items:
> > + - const: merge
> > + - const: merge_async
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + vdo1_rdma@1c104000 {
> > + compatible = "mediatek,mt8195-vdo1-rdma",
> > + "mediatek,mt8195-disp-pseudo-ovl";
>
> Do not create pseudo or virtual device, so just leave the
> "mediatek,mt8195-vdo1-rdma".
>
> Regards,
> Chun-Kuang.
>
OK, I will remove it.
> > + reg = <0 0x1c104000 0 0x1000>;
> > + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0x4000 0x1000>;
> > + };
> > +
> > + disp_vpp_merge@1c10c000 {
> > + compatible = "mediatek,mt8195-vdo1-merge";
> > + reg = <0 0x1c10c000 0 0x1000>;
> > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> > + clock-names = "merge","merge_async";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0xc000 0x1000>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
Regards,
Nancy Lin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
@ 2021-07-22 0:59 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 0:59 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, srv_heupstream, David Airlie, jason-jh . lin, singo.chang,
linux-kernel, DRI Development, Yongqiang Niu, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:22 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > 1. Add pseudo-ovl definition file for mt8195 display.
> > 2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in
> > details.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > .../display/mediatek/mediatek,disp.yaml | 5 +
> > .../display/mediatek/mediatek,pseudo-ovl.yaml | 105
> > ++++++++++++++++++
> > 2 files changed, 110 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > index aac1796e3f6b..bb6d28572b48 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > yaml
> > @@ -230,6 +230,11 @@ properties:
> > - items:
> > - const: mediatek,mt8173-disp-od
> >
> > + # PSEUDO-OVL: see
> > Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-
> > ovl.yaml
> > + # for details.
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > +
> > reg:
> > description: Physical base address and length of the function
> > block register space.
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > new file mode 100644
> > index 000000000000..9059d96ce70e
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseud
> > o-ovl.yaml
> > @@ -0,0 +1,105 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZuPFSKBk$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1_1k5jdZ0VK46IctSjt63iq1UMWSrAw8cV97W1BmonfuqPnYWBg8R_-BZgMaVN_K$
> >
> > +
> > +title: mediatek pseudo ovl Device Tree Bindings
> > +
> > +maintainers:
> > + - CK Hu <ck.hu@mediatek.com>
> > + - Nancy.Lin <nancy.lin@mediatek.com>
> > +
> > +description: |
> > + The Mediatek pseudo ovl function block is composed of eight RDMA
> > and
> > + four MERGE devices. It's encapsulated as an overlay device,
> > which supports
> > + 4 layers.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + # pseudo ovl controller
> > + - items:
> > + - const: mediatek,mt8195-disp-pseudo-ovl
> > + # RDMA: read DMA
> > + - items:
> > + - const: mediatek,mt8195-vdo1-rdma
> > + # MERGE: merge streams from two RDMA sources
> > + - items:
> > + - const: mediatek,mt8195-vdo1-merge
> > + reg:
> > + maxItems: 1
> > + interrupts:
> > + maxItems: 1
> > + iommus:
> > + description: The compatible property is DMA function blocks.
> > + Should point to the respective IOMMU block with master port
> > as argument,
> > + see
> > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > + details.
> > + maxItems: 1
> > + clocks:
> > + maxItems: 2
> > + clock-names:
> > + maxItems: 2
> > + power-domains:
> > + maxItems: 1
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: The register of display function block to be set
> > by gce.
> > + There are 4 arguments in this property, gce node, subsys id,
> > offset and
> > + register size. The subsys id is defined in the gce header of
> > each chips
> > + include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
> > register of
> > + display function block.
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const:
> > + - mediatek,mt8195-vdo1-merge
> > +
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: merge clock
> > + - description: merge async clock
> > + clock-names:
> > + items:
> > + - const: merge
> > + - const: merge_async
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +
> > + vdo1_rdma@1c104000 {
> > + compatible = "mediatek,mt8195-vdo1-rdma",
> > + "mediatek,mt8195-disp-pseudo-ovl";
>
> Do not create pseudo or virtual device, so just leave the
> "mediatek,mt8195-vdo1-rdma".
>
> Regards,
> Chun-Kuang.
>
OK, I will remove it.
> > + reg = <0 0x1c104000 0 0x1000>;
> > + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0x4000 0x1000>;
> > + };
> > +
> > + disp_vpp_merge@1c10c000 {
> > + compatible = "mediatek,mt8195-vdo1-merge";
> > + reg = <0 0x1c10c000 0 0x1000>;
> > + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> > + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
> > + clock-names = "merge","merge_async";
> > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX
> > 0xc000 0x1000>;
> > + };
> > +
> > +...
> > --
> > 2.18.0
> >
Regards,
Nancy Lin
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
2021-07-18 23:56 ` Chun-Kuang Hu
(?)
@ 2021-07-22 1:32 ` Nancy.Lin
-1 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 1:32 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream, nancy.lin
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > 8 files changed, 584 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..fcce08710cef 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..7227ffbc3eae 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 9125d0f6352f..3fa86f12feb4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > .start = mtk_ufoe_start,
> > };
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > +};
> > +
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > @@ -363,6 +371,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > [MTK_DISP_COLOR] = "color",
> > [MTK_DISP_CCORR] = "ccorr",
> > [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_ETHDR] = "ethdr",
> > [MTK_DISP_GAMMA] = "gamma",
> > [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi
> > },
> > + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0,
> > &ddp_ethdr},
> > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0,
> > &ddp_gamma },
> > [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0,
> > &ddp_merge },
> > [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1,
> > &ddp_merge },
> > @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_DSC ||
> > + type == MTK_DISP_ETHDR ||
> > type == MTK_DISP_GAMMA ||
> > type == MTK_DISP_MERGE ||
> > type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0afd78c0bc92..f55efba6e744 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_BLS,
> > MTK_DISP_DSC,
> > MTK_DISP_MERGE,
> > + MTK_DISP_ETHDR,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..ace958a34bb5 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_ETHDR },
> > { }
> > };
> >
> > @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_DSC ||
> > + comp_type == MTK_DISP_ETHDR ||
> > comp_type == MTK_DISP_GAMMA ||
> > comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > @@ -676,6 +679,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..ceadb28169b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,537 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > +#define MIX_ROI_BGCLR 0x20
> > +#define MIX_SRC_CON 0x24
> > +#define MIX_L0_CON 0x28
> > +#define MIX_L0_SRC_SIZE 0x30
> > +#define MIX_L0_OFFSET 0x34
> > +#define MIX_L1_CON 0x40
> > +#define MIX_L1_SRC_SIZE 0x48
> > +#define MIX_L1_OFFSET 0x4c
> > +#define MIX_L2_CON 0x58
> > +#define MIX_L2_SRC_SIZE 0x60
> > +#define MIX_L2_OFFSET 0x64
> > +#define MIX_L3_CON 0x70
> > +#define MIX_L3_SRC_SIZE 0x78
> > +#define MIX_L3_OFFSET 0x7c
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> > +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> > +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> > +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> > +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> > +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> > +
> > +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> > +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> > +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> > +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> > +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> > +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> > +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> > +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> > +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> > +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> > +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> > +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> > +
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> > +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> > +
> > +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> > +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> > + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) |
> > BIT(22) | BIT(23))
> > +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> > +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> > + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> > + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> > + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> > + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> > +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> > +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> > +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> > +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> > +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> > +
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + void __iomem *top_regs;
> > + struct cmdq_client_reg top_cmdq_base;
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +static const unsigned int alpha_source_sel[] = {
> > + HDR_ALPHA_SEL_MIXER_IN1,
> > + HDR_ALPHA_SEL_MIXER_IN2,
> > + HDR_ALPHA_SEL_MIXER_IN3,
> > + HDR_ALPHA_SEL_MIXER_IN4,
> > +};
> > +
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx < 4)
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
>
> Why not just
>
> mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> mixer->regs, MIX_SRC_CON,
> BIT(idx));
>
There are two modes in Mixer.
1. Background relay mode: all layers off
2. Normal mix mode: at least one layer on
The timing of the two modes is different, so keep using the normal mix
mode.
Just set the layer region to 0 when the layer off.
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
>
> Because ethdr has layers and vblank interrupt, I think ethdr should
> be
> part of pseudo ovl, so squash these two into one.
>
OK, I will merge the pseudo_ovl and ethdr components into one.
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + fmt = state->pending.format;
>
> fmt is useless, so remove.
>
OK, I will remove it.
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
>
> Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
> interface for this driver to use.
>
OK, I will add a new mmsys API for the config.
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
> > + }
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
>
> #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
>
> And you could get rid of this switch case.
OK, I will modify it.
>
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_CON, 0x1ff);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_CON, 0x1ff);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_CON, 0x1ff);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_CON, 0x1ff);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_ROI_SIZE, ~0);
>
> mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> mixer->regs, MIX_ROI_SIZE);
>
OK, I will modify it.
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
>
> Explain what these value mean.
>
OK, I will explain these settings.
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM0, ~0);
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM1, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_DATAPATH_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L0_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L1_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L2_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L3_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L0_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L1_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L2_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L3_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_SRC_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_ROI_BGCLR, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_EN, ~0);
>
> I think only the latest setting is about start, move other setting to
> config.
>
OK, I will move it.
>
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN, ~0);
> > + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW1_RST_B,
> > HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv-
> > >top_cmdq_base,
> > + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> > + HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base,
> > priv->top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
>
> Make vdosys1 a reset controller like [1].
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!2eXsbwb3k-IvGimKXZxCCXGJiGQowmNyxuwHetN4Jr6jhe8Bgu4aHuLTYcvgVrxy$
>
OK, I will change to use the reset framework.
>
>
> Regards,
> Chun-Kuang.
>
> > +}
> > +
> > +int mtk_ethdr_clk_enable(struct device *dev)
> > +{
> > + int i, ret;
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + dev_err(dev,
> > + "ethdr_clk prepare enable failed\n");
> > + return ret;
> > +}
> > +
> > +void mtk_ethdr_clk_disable(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + int i;
> > +
> > + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> > +}
> > +
> > +static int mtk_ethdr_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct drm_device *drm_dev = data;
> > + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> > + struct device *mmsys_dev = drm_private->mmsys_dev;
> > +
> > + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_dev_get_client_reg(mmsys_dev, &priv-
> > >top_cmdq_base, 0))
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + return 0;
> > +}
> > +
> > +static void mtk_ethdr_unbind(struct device *dev, struct device
> > *master, void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_ethdr_component_ops = {
> > + .bind = mtk_ethdr_bind,
> > + .unbind = mtk_ethdr_unbind,
> > +};
> > +
> > +static int mtk_ethdr_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ethdr *priv;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < ETHDR_ID_MAX; i++) {
> > + priv->ethdr_comp[i].dev = dev;
> > + priv->ethdr_comp[i].regs = of_iomap(dev->of_node,
> > i);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev,
> > + &priv-
> > >ethdr_comp[i].cmdq_base, i);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> > + priv->ethdr_comp[i].regs,
> > ethdr_comp_str[i]);
> > + }
> > +
> > + for (i = 0; i < ETHDR_CLK_NUM; i++)
> > + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> > + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + return ret;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = component_add(dev, &mtk_ethdr_component_ops);
> > + if (ret)
> > + dev_notice(dev, "Failed to add component: %d\n",
> > ret);
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ethdr_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> > +
> > +struct platform_driver mtk_ethdr_driver = {
> > + .probe = mtk_ethdr_probe,
> > + .remove = mtk_ethdr_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ethdr",
> > + .owner = THIS_MODULE,
> > + .of_match_table =
> > mtk_ethdr_driver_dt_match,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > new file mode 100644
> > index 000000000000..c8fc0581a632
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_ETHDR_H__
> > +#define __MTK_DISP_ETHDR_H__
> > +
> > +#include <linux/uaccess.h>
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +#endif
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 1:32 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 1:32 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, David Airlie, Daniel Vetter, Rob Herring,
Matthias Brugger, jason-jh . lin, Yongqiang Niu, DRI Development,
moderated list:ARM/Mediatek SoC support, DTML, linux-kernel,
Linux ARM, singo.chang, srv_heupstream, nancy.lin
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > 8 files changed, 584 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..fcce08710cef 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..7227ffbc3eae 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 9125d0f6352f..3fa86f12feb4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > .start = mtk_ufoe_start,
> > };
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > +};
> > +
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > @@ -363,6 +371,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > [MTK_DISP_COLOR] = "color",
> > [MTK_DISP_CCORR] = "ccorr",
> > [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_ETHDR] = "ethdr",
> > [MTK_DISP_GAMMA] = "gamma",
> > [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi
> > },
> > + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0,
> > &ddp_ethdr},
> > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0,
> > &ddp_gamma },
> > [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0,
> > &ddp_merge },
> > [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1,
> > &ddp_merge },
> > @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_DSC ||
> > + type == MTK_DISP_ETHDR ||
> > type == MTK_DISP_GAMMA ||
> > type == MTK_DISP_MERGE ||
> > type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0afd78c0bc92..f55efba6e744 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_BLS,
> > MTK_DISP_DSC,
> > MTK_DISP_MERGE,
> > + MTK_DISP_ETHDR,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..ace958a34bb5 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_ETHDR },
> > { }
> > };
> >
> > @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_DSC ||
> > + comp_type == MTK_DISP_ETHDR ||
> > comp_type == MTK_DISP_GAMMA ||
> > comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > @@ -676,6 +679,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..ceadb28169b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,537 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > +#define MIX_ROI_BGCLR 0x20
> > +#define MIX_SRC_CON 0x24
> > +#define MIX_L0_CON 0x28
> > +#define MIX_L0_SRC_SIZE 0x30
> > +#define MIX_L0_OFFSET 0x34
> > +#define MIX_L1_CON 0x40
> > +#define MIX_L1_SRC_SIZE 0x48
> > +#define MIX_L1_OFFSET 0x4c
> > +#define MIX_L2_CON 0x58
> > +#define MIX_L2_SRC_SIZE 0x60
> > +#define MIX_L2_OFFSET 0x64
> > +#define MIX_L3_CON 0x70
> > +#define MIX_L3_SRC_SIZE 0x78
> > +#define MIX_L3_OFFSET 0x7c
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> > +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> > +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> > +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> > +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> > +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> > +
> > +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> > +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> > +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> > +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> > +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> > +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> > +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> > +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> > +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> > +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> > +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> > +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> > +
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> > +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> > +
> > +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> > +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> > + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) |
> > BIT(22) | BIT(23))
> > +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> > +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> > + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> > + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> > + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> > + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> > +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> > +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> > +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> > +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> > +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> > +
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + void __iomem *top_regs;
> > + struct cmdq_client_reg top_cmdq_base;
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +static const unsigned int alpha_source_sel[] = {
> > + HDR_ALPHA_SEL_MIXER_IN1,
> > + HDR_ALPHA_SEL_MIXER_IN2,
> > + HDR_ALPHA_SEL_MIXER_IN3,
> > + HDR_ALPHA_SEL_MIXER_IN4,
> > +};
> > +
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx < 4)
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
>
> Why not just
>
> mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> mixer->regs, MIX_SRC_CON,
> BIT(idx));
>
There are two modes in Mixer.
1. Background relay mode: all layers off
2. Normal mix mode: at least one layer on
The timing of the two modes is different, so keep using the normal mix
mode.
Just set the layer region to 0 when the layer off.
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
>
> Because ethdr has layers and vblank interrupt, I think ethdr should
> be
> part of pseudo ovl, so squash these two into one.
>
OK, I will merge the pseudo_ovl and ethdr components into one.
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + fmt = state->pending.format;
>
> fmt is useless, so remove.
>
OK, I will remove it.
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
>
> Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
> interface for this driver to use.
>
OK, I will add a new mmsys API for the config.
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
> > + }
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
>
> #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
>
> And you could get rid of this switch case.
OK, I will modify it.
>
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_CON, 0x1ff);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_CON, 0x1ff);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_CON, 0x1ff);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_CON, 0x1ff);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_ROI_SIZE, ~0);
>
> mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> mixer->regs, MIX_ROI_SIZE);
>
OK, I will modify it.
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
>
> Explain what these value mean.
>
OK, I will explain these settings.
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM0, ~0);
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM1, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_DATAPATH_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L0_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L1_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L2_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L3_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L0_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L1_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L2_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L3_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_SRC_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_ROI_BGCLR, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_EN, ~0);
>
> I think only the latest setting is about start, move other setting to
> config.
>
OK, I will move it.
>
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN, ~0);
> > + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW1_RST_B,
> > HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv-
> > >top_cmdq_base,
> > + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> > + HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base,
> > priv->top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
>
> Make vdosys1 a reset controller like [1].
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!2eXsbwb3k-IvGimKXZxCCXGJiGQowmNyxuwHetN4Jr6jhe8Bgu4aHuLTYcvgVrxy$
>
OK, I will change to use the reset framework.
>
>
> Regards,
> Chun-Kuang.
>
> > +}
> > +
> > +int mtk_ethdr_clk_enable(struct device *dev)
> > +{
> > + int i, ret;
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + dev_err(dev,
> > + "ethdr_clk prepare enable failed\n");
> > + return ret;
> > +}
> > +
> > +void mtk_ethdr_clk_disable(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + int i;
> > +
> > + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> > +}
> > +
> > +static int mtk_ethdr_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct drm_device *drm_dev = data;
> > + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> > + struct device *mmsys_dev = drm_private->mmsys_dev;
> > +
> > + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_dev_get_client_reg(mmsys_dev, &priv-
> > >top_cmdq_base, 0))
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + return 0;
> > +}
> > +
> > +static void mtk_ethdr_unbind(struct device *dev, struct device
> > *master, void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_ethdr_component_ops = {
> > + .bind = mtk_ethdr_bind,
> > + .unbind = mtk_ethdr_unbind,
> > +};
> > +
> > +static int mtk_ethdr_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ethdr *priv;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < ETHDR_ID_MAX; i++) {
> > + priv->ethdr_comp[i].dev = dev;
> > + priv->ethdr_comp[i].regs = of_iomap(dev->of_node,
> > i);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev,
> > + &priv-
> > >ethdr_comp[i].cmdq_base, i);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> > + priv->ethdr_comp[i].regs,
> > ethdr_comp_str[i]);
> > + }
> > +
> > + for (i = 0; i < ETHDR_CLK_NUM; i++)
> > + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> > + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + return ret;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = component_add(dev, &mtk_ethdr_component_ops);
> > + if (ret)
> > + dev_notice(dev, "Failed to add component: %d\n",
> > ret);
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ethdr_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> > +
> > +struct platform_driver mtk_ethdr_driver = {
> > + .probe = mtk_ethdr_probe,
> > + .remove = mtk_ethdr_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ethdr",
> > + .owner = THIS_MODULE,
> > + .of_match_table =
> > mtk_ethdr_driver_dt_match,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > new file mode 100644
> > index 000000000000..c8fc0581a632
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_ETHDR_H__
> > +#define __MTK_DISP_ETHDR_H__
> > +
> > +#include <linux/uaccess.h>
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +#endif
> > +
> > --
> > 2.18.0
> >
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^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 1:32 ` Nancy.Lin
0 siblings, 0 replies; 52+ messages in thread
From: Nancy.Lin @ 2021-07-22 1:32 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, srv_heupstream, David Airlie, jason-jh . lin, singo.chang,
linux-kernel, DRI Development, Yongqiang Niu, Matthias Brugger,
Rob Herring, moderated list:ARM/Mediatek SoC support, nancy.lin,
Linux ARM
Hi Chun-Kuang,
On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> >
> > Add ETHDR module files:
> > ETHDR is designed for HDR video and graphics conversion in the
> > external
> > display path. It handles multiple HDR input types and performs tone
> > mapping, color space/color format conversion, and then combines
> > different layers, output the required HDR or SDR signal to the
> > subsequent display path.
> >
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > 8 files changed, 584 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 27c89847d43b..fcce08710cef 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_drm_gem.o \
> > mtk_drm_plane.o \
> > mtk_dsi.o \
> > - mtk_dpi.o
> > + mtk_dpi.o \
> > + mtk_ethdr.o
> >
> > obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 3e27ce7fef57..7227ffbc3eae 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -105,4 +105,12 @@ void mtk_rdma_enable_vblank(struct device
> > *dev,
> > void *vblank_cb_data);
> > void mtk_rdma_disable_vblank(struct device *dev);
> >
> > +int mtk_ethdr_clk_enable(struct device *dev);
> > +void mtk_ethdr_clk_disable(struct device *dev);
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_start(struct device *dev);
> > +void mtk_ethdr_stop(struct device *dev);
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 9125d0f6352f..3fa86f12feb4 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -355,6 +355,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > .start = mtk_ufoe_start,
> > };
> >
> > +static const struct mtk_ddp_comp_funcs ddp_ethdr = {
> > + .clk_enable = mtk_ethdr_clk_enable,
> > + .clk_disable = mtk_ethdr_clk_disable,
> > + .config = mtk_ethdr_config,
> > + .start = mtk_ethdr_start,
> > + .stop = mtk_ethdr_stop,
> > +};
> > +
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > @@ -363,6 +371,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > [MTK_DISP_COLOR] = "color",
> > [MTK_DISP_CCORR] = "ccorr",
> > [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_ETHDR] = "ethdr",
> > [MTK_DISP_GAMMA] = "gamma",
> > [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > @@ -399,6 +408,7 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi
> > },
> > + [DDP_COMPONENT_ETHDR] = { MTK_DISP_ETHDR, 0,
> > &ddp_ethdr},
> > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0,
> > &ddp_gamma },
> > [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0,
> > &ddp_merge },
> > [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1,
> > &ddp_merge },
> > @@ -536,6 +546,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_DSC ||
> > + type == MTK_DISP_ETHDR ||
> > type == MTK_DISP_GAMMA ||
> > type == MTK_DISP_MERGE ||
> > type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0afd78c0bc92..f55efba6e744 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_BLS,
> > MTK_DISP_DSC,
> > MTK_DISP_MERGE,
> > + MTK_DISP_ETHDR,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 11c25daf05d8..ace958a34bb5 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -480,6 +480,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_PWM },
> > { .compatible = "mediatek,mt8173-disp-od",
> > .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt8195-disp-ethdr",
> > + .data = (void *)MTK_DISP_ETHDR },
> > { }
> > };
> >
> > @@ -567,6 +569,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_DSC ||
> > + comp_type == MTK_DISP_ETHDR ||
> > comp_type == MTK_DISP_GAMMA ||
> > comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > @@ -676,6 +679,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_dpi_driver,
> > &mtk_drm_platform_driver,
> > &mtk_dsi_driver,
> > + &mtk_ethdr_driver,
> > };
> >
> > static int __init mtk_drm_init(void)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index c4d802a43531..c87ebb5309d0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -55,5 +55,6 @@ extern struct platform_driver
> > mtk_disp_dsc_driver;
> > extern struct platform_driver mtk_disp_merge_driver;
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> > +extern struct platform_driver mtk_ethdr_driver;
> >
> > #endif /* MTK_DRM_DRV_H */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > new file mode 100644
> > index 000000000000..ceadb28169b8
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> > @@ -0,0 +1,537 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <drm/drm_fourcc.h>
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_ethdr.h"
> > +
> > +#define MIX_EN 0xc
> > +#define MIX_RST 0x14
> > +#define MIX_ROI_SIZE 0x18
> > +#define MIX_DATAPATH_CON 0x1c
> > +#define MIX_ROI_BGCLR 0x20
> > +#define MIX_SRC_CON 0x24
> > +#define MIX_L0_CON 0x28
> > +#define MIX_L0_SRC_SIZE 0x30
> > +#define MIX_L0_OFFSET 0x34
> > +#define MIX_L1_CON 0x40
> > +#define MIX_L1_SRC_SIZE 0x48
> > +#define MIX_L1_OFFSET 0x4c
> > +#define MIX_L2_CON 0x58
> > +#define MIX_L2_SRC_SIZE 0x60
> > +#define MIX_L2_OFFSET 0x64
> > +#define MIX_L3_CON 0x70
> > +#define MIX_L3_SRC_SIZE 0x78
> > +#define MIX_L3_OFFSET 0x7c
> > +#define MIX_FUNC_DCM0 0x120
> > +#define MIX_FUNC_DCM1 0x124
> > +
> > +#define HDR_VDO_FE_0804_HDR_DM_FE 0x804
> > +#define HDR_VDO_FE_081C_HDR_DM_FE 0x81c
> > +#define HDR_VDO_FE_09EC_HDR_DM_FE 0x9ec
> > +#define HDR_VDO_FE_0618_HDR_TOP_FE 0x618
> > +#define HDR_VDO_FE_061C_HDR_TOP_FE 0x61c
> > +#define HDR_VDO_FE_06D0_HDR_TOP_FE 0x6d0
> > +#define HDR_VDO_FE_0634_HDR_TOP_FE 0x634
> > +
> > +#define HDR_GFX_FE_0100_GFX_DV_WP 0x100
> > +#define HDR_GFX_FE_012C_GFX_DV_WP 0x12c
> > +#define HDR_GFX_FE_0134_GFX_DV_WP 0x134
> > +#define HDR_GFX_FE_0138_GFX_DV_WP 0x138
> > +#define HDR_GFX_FE_013C_GFX_DV_WP 0x13c
> > +#define HDR_GFX_FE_0140_GFX_DV_WP 0x140
> > +#define HDR_GFX_FE_0144_GFX_DV_WP 0x144
> > +#define HDR_GFX_FE_0148_GFX_DV_WP 0x148
> > +#define HDR_GFX_FE_014C_GFX_DV_WP 0x14c
> > +#define HDR_GFX_FE_0150_GFX_DV_WP 0x150
> > +#define HDR_GFX_FE_0154_GFX_DV_WP 0x154
> > +#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
> > +#define HDR_GFX_FE_021C_GFX_HDR_FE 0x21c
> > +#define HDR_GFX_FE_03EC_GFX_HDR_FE 0x3ec
> > +
> > +#define HDR_VDO_BE_0204_VDO_DM_BE 0x204
> > +#define HDR_VDO_BE_0320_VDO_DM_BE 0x320
> > +#define HDR_VDO_BE_03C8_VDO_DM_BE 0x3c8
> > +
> > +#define VDO1_CONFIG_SW0_RST_B 0x1d0
> > +#define VDO1_CONFIG_SW1_RST_B 0x1d4
> > + #define HDR_ASYNC_RESET_BIT (BIT(19) | BIT(20) | BIT(21) |
> > BIT(22) | BIT(23))
> > +#define VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD 0xe70
> > +#define VDO1_CONFIG_HDR_TOP_CFG 0xd00
> > + #define HDR_ALPHA_SEL_MIXER_IN1 BIT(20)
> > + #define HDR_ALPHA_SEL_MIXER_IN2 BIT(21)
> > + #define HDR_ALPHA_SEL_MIXER_IN3 BIT(22)
> > + #define HDR_ALPHA_SEL_MIXER_IN4 BIT(23)
> > +#define VDO1_CONFIG_MIXER_IN1_ALPHA 0xd30
> > +#define VDO1_CONFIG_MIXER_IN2_ALPHA 0xd34
> > +#define VDO1_CONFIG_MIXER_IN3_ALPHA 0xd38
> > +#define VDO1_CONFIG_MIXER_IN4_ALPHA 0xd3c
> > +#define VDO1_CONFIG_MIXER_IN4_PAD 0xd4c
> > +
> > +#define MIXER_ALPHA_AEN BIT(8)
> > +#define MIXER_ALPHA 0xff
> > +#define ETHDR_CLK_NUM 13
> > +
> > +enum mtk_ethdr_comp_id {
> > + ETHDR_MIXER,
> > + ETHDR_VDO_FE0,
> > + ETHDR_VDO_FE1,
> > + ETHDR_GFX_FE0,
> > + ETHDR_GFX_FE1,
> > + ETHDR_VDO_BE,
> > + ETHDR_ADL_DS,
> > + ETHDR_ID_MAX
> > +};
> > +
> > +struct mtk_ethdr_comp {
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_base;
> > +};
> > +
> > +struct mtk_ethdr {
> > + void __iomem *top_regs;
> > + struct cmdq_client_reg top_cmdq_base;
> > + struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
> > + struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
> > +};
> > +
> > +static const char * const ethdr_comp_str[] = {
> > + "ETHDR_MIXER",
> > + "ETHDR_VDO_FE0",
> > + "ETHDR_VDO_FE1",
> > + "ETHDR_GFX_FE0",
> > + "ETHDR_GFX_FE1",
> > + "ETHDR_VDO_BE",
> > + "ETHDR_ADL_DS",
> > + "ETHDR_ID_MAX"
> > +};
> > +
> > +static const char * const ethdr_clk_str[] = {
> > + "ethdr_top",
> > + "mixer",
> > + "vdo_fe0",
> > + "vdo_fe1",
> > + "gfx_fe0",
> > + "gfx_fe1",
> > + "vdo_be",
> > + "adl_ds",
> > + "vdo_fe0_async",
> > + "vdo_fe1_async",
> > + "gfx_fe0_async",
> > + "gfx_fe1_async",
> > + "vdo_be_async",
> > +};
> > +
> > +static const unsigned int alpha_source_sel[] = {
> > + HDR_ALPHA_SEL_MIXER_IN1,
> > + HDR_ALPHA_SEL_MIXER_IN2,
> > + HDR_ALPHA_SEL_MIXER_IN3,
> > + HDR_ALPHA_SEL_MIXER_IN4,
> > +};
> > +
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + if (idx < 4)
> > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> > +}
> > +
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
>
> Why not just
>
> mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> mixer->regs, MIX_SRC_CON,
> BIT(idx));
>
There are two modes in Mixer.
1. Background relay mode: all layers off
2. Normal mix mode: at least one layer on
The timing of the two modes is different, so keep using the normal mix
mode.
Just set the layer region to 0 when the layer off.
> > +}
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt)
>
> Because ethdr has layers and vblank interrupt, I think ethdr should
> be
> part of pseudo ovl, so squash these two into one.
>
OK, I will merge the pseudo_ovl and ethdr components into one.
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > + struct mtk_plane_pending_state *pending = &state->pending;
> > + unsigned int src_size = (pending->height << 16) | pending-
> > >width;
> > + unsigned int offset = (pending->y << 16) | pending->x;
> > + unsigned int alpha_con = 0;
> > + unsigned int fmt = 0;
> > +
> > + fmt = state->pending.format;
>
> fmt is useless, so remove.
>
OK, I will remove it.
> > +
> > + if (state->base.fb && state->base.fb->format->has_alpha) {
> > + alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
>
> Set vdosys1 register in vdosys1 driver, and vdosys1 driver provide
> interface for this driver to use.
>
OK, I will add a new mmsys API for the config.
> > + } else {
> > + mtk_ddp_write_mask(cmdq_pkt, ~0, &priv-
> > >top_cmdq_base, priv->top_regs,
> > + VDO1_CONFIG_HDR_TOP_CFG,
> > alpha_source_sel[idx]);
> > + }
> > +
> > + switch (idx) {
> > + case 0:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_SRC_SIZE,
> > ~0);
>
> #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
>
> And you could get rid of this switch case.
OK, I will modify it.
>
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L0_CON, 0x1ff);
> > + break;
> > + case 1:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L1_CON, 0x1ff);
> > + break;
> > + case 2:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L2_CON, 0x1ff);
> > + break;
> > + case 3:
> > + mtk_ddp_write_mask(cmdq_pkt, src_size, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_SRC_SIZE,
> > ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, offset, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_OFFSET, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_L3_CON, 0x1ff);
> > + break;
> > + default:
> > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > + break;
> > + }
> > +}
> > +
> > +void mtk_ethdr_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16) | (w / 2), &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_HDR_BE_ASYNC_CFG_WD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0, &priv->top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_PAD, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, (h << 16 | w), &mixer-
> > >cmdq_base,
> > + mixer->regs, MIX_ROI_SIZE, ~0);
>
> mtk_ddp_write(cmdq_pkt, (h << 16 | w), &mixer->cmdq_base,
> mixer->regs, MIX_ROI_SIZE);
>
OK, I will modify it.
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN1_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN2_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN3_ALPHA, ~0);
> > + mtk_ddp_write_mask(cmdq_pkt, 0x01000100, &priv-
> > >top_cmdq_base,
> > + priv->top_regs,
> > VDO1_CONFIG_MIXER_IN4_ALPHA, ~0);
> > +}
> > +
> > +void mtk_ethdr_start(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *vdo_fe0 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE0];
> > + struct mtk_ethdr_comp *vdo_fe1 = &priv-
> > >ethdr_comp[ETHDR_VDO_FE1];
> > + struct mtk_ethdr_comp *gfx_fe0 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE0];
> > + struct mtk_ethdr_comp *gfx_fe1 = &priv-
> > >ethdr_comp[ETHDR_GFX_FE1];
> > + struct mtk_ethdr_comp *vdo_be = &priv-
> > >ethdr_comp[ETHDR_VDO_BE];
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe0->cmdq_base, vdo_fe0-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe0->cmdq_base,
> > vdo_fe0->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
>
> Explain what these value mean.
>
OK, I will explain these settings.
> > +
> > + mtk_ddp_write_mask(NULL, 0xfd, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0804_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_09EC_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x12e, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_081C_HDR_DM_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_0618_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x2, &vdo_fe1->cmdq_base, vdo_fe1-
> > >regs,
> > + HDR_VDO_FE_061C_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8001, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_06D0_HDR_TOP_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x8000, &vdo_fe1->cmdq_base,
> > vdo_fe1->regs,
> > + HDR_VDO_FE_0634_HDR_TOP_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe0->cmdq_base,
> > gfx_fe0->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x8001, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0100_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xe030, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_012C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c0, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0134_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1e69, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0138_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1fd7, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_013C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xba, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0140_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x275, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0144_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x3f, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0148_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1f99, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_014C_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1ea6, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0150_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0x1c2, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0154_GFX_DV_WP, ~0);
> > + mtk_ddp_write_mask(NULL, 0xfd, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_0204_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x80, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_03EC_GFX_HDR_FE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x20, &gfx_fe1->cmdq_base,
> > gfx_fe1->regs,
> > + HDR_GFX_FE_021C_GFX_HDR_FE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0x7e, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0204_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_0320_VDO_DM_BE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x01, &vdo_be->cmdq_base, vdo_be-
> > >regs,
> > + HDR_VDO_BE_03C8_VDO_DM_BE, ~0);
> > +
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM0, ~0);
> > + mtk_ddp_write_mask(NULL, 0xffffffff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_FUNC_DCM1, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000888, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_DATAPATH_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L0_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L1_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L2_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x000021ff, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_L3_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L0_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L1_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L2_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0, &mixer->cmdq_base, mixer-
> > >regs,
> > + MIX_L3_SRC_SIZE, ~0);
> > + mtk_ddp_write_mask(NULL, 0x0fa50001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_SRC_CON, ~0);
> > + mtk_ddp_write_mask(NULL, 0xFF000000, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_ROI_BGCLR, ~0);
> > + mtk_ddp_write_mask(NULL, 0x00000001, &mixer->cmdq_base,
> > mixer->regs,
> > + MIX_EN, ~0);
>
> I think only the latest setting is about start, move other setting to
> config.
>
OK, I will move it.
>
> > +}
> > +
> > +void mtk_ethdr_stop(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct mtk_ethdr_comp *mixer = &priv-
> > >ethdr_comp[ETHDR_MIXER];
> > +
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_EN, ~0);
> > + mtk_ddp_write_mask(NULL, 1, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW1_RST_B,
> > HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, 0, &priv->top_cmdq_base, priv-
> > >top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
> > + mtk_ddp_write_mask(NULL, 0, &mixer->cmdq_base, mixer->regs,
> > MIX_RST, ~0);
> > + mtk_ddp_write_mask(NULL, HDR_ASYNC_RESET_BIT, &priv-
> > >top_cmdq_base,
> > + priv->top_regs, VDO1_CONFIG_SW1_RST_B,
> > + HDR_ASYNC_RESET_BIT);
> > + mtk_ddp_write_mask(NULL, BIT(29), &priv->top_cmdq_base,
> > priv->top_regs,
> > + VDO1_CONFIG_SW0_RST_B, BIT(29));
>
> Make vdosys1 a reset controller like [1].
>
> [1]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!2eXsbwb3k-IvGimKXZxCCXGJiGQowmNyxuwHetN4Jr6jhe8Bgu4aHuLTYcvgVrxy$
>
OK, I will change to use the reset framework.
>
>
> Regards,
> Chun-Kuang.
>
> > +}
> > +
> > +int mtk_ethdr_clk_enable(struct device *dev)
> > +{
> > + int i, ret;
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > +
> > + ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + dev_err(dev,
> > + "ethdr_clk prepare enable failed\n");
> > + return ret;
> > +}
> > +
> > +void mtk_ethdr_clk_disable(struct device *dev)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + int i;
> > +
> > + clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
> > +}
> > +
> > +static int mtk_ethdr_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > + struct drm_device *drm_dev = data;
> > + struct mtk_drm_private *drm_private = drm_dev->dev_private;
> > + struct device *mmsys_dev = drm_private->mmsys_dev;
> > +
> > + priv->top_regs = of_iomap(mmsys_dev->of_node, 0);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + if (cmdq_dev_get_client_reg(mmsys_dev, &priv-
> > >top_cmdq_base, 0))
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + return 0;
> > +}
> > +
> > +static void mtk_ethdr_unbind(struct device *dev, struct device
> > *master, void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_ethdr_component_ops = {
> > + .bind = mtk_ethdr_bind,
> > + .unbind = mtk_ethdr_unbind,
> > +};
> > +
> > +static int mtk_ethdr_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ethdr *priv;
> > + int ret;
> > + int i;
> > +
> > + dev_info(dev, "%s+\n", __func__);
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < ETHDR_ID_MAX; i++) {
> > + priv->ethdr_comp[i].dev = dev;
> > + priv->ethdr_comp[i].regs = of_iomap(dev->of_node,
> > i);
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev,
> > + &priv-
> > >ethdr_comp[i].cmdq_base, i);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > + dev_info(dev, "[DRM]regs:0x%x, node:%s\n",
> > + priv->ethdr_comp[i].regs,
> > ethdr_comp_str[i]);
> > + }
> > +
> > + for (i = 0; i < ETHDR_CLK_NUM; i++)
> > + priv->ethdr_clk[i].id = ethdr_clk_str[i];
> > + ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv-
> > >ethdr_clk);
> > + if (ret)
> > + return ret;
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = component_add(dev, &mtk_ethdr_component_ops);
> > + if (ret)
> > + dev_notice(dev, "Failed to add component: %d\n",
> > ret);
> > +
> > + dev_info(dev, "%s-\n", __func__);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ethdr_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_ethdr_component_ops);
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
> > + { .compatible = "mediatek,mt8195-disp-ethdr"},
> > + {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
> > +
> > +struct platform_driver mtk_ethdr_driver = {
> > + .probe = mtk_ethdr_probe,
> > + .remove = mtk_ethdr_remove,
> > + .driver = {
> > + .name = "mediatek-disp-ethdr",
> > + .owner = THIS_MODULE,
> > + .of_match_table =
> > mtk_ethdr_driver_dt_match,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > new file mode 100644
> > index 000000000000..c8fc0581a632
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_DISP_ETHDR_H__
> > +#define __MTK_DISP_ETHDR_H__
> > +
> > +#include <linux/uaccess.h>
> > +#include <drm/mediatek_drm.h>
> > +
> > +void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> > + struct mtk_plane_state *state,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > + struct cmdq_pkt *cmdq_pkt);
> > +#endif
> > +
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
2021-07-22 1:32 ` Nancy.Lin
(?)
@ 2021-07-22 5:25 ` CK Hu
-1 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-22 5:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics conversion in the
> > > external
> > > display path. It handles multiple HDR input types and performs tone
> > > mapping, color space/color format conversion, and then combines
> > > different layers, output the required HDR or SDR signal to the
> > > subsequent display path.
> > >
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > > ++++++++++++++++++++
> > > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > > 8 files changed, 584 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> > >
> > > +
> > > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + if (idx < 4)
> > > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > > >cmdq_base,
> > > + mixer->regs, MIX_SRC_CON,
> > > BIT(idx));
> > > +}
> > > +
> > > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + switch (idx) {
> > > + case 0:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L0_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 1:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L1_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 2:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L2_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 3:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L3_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + default:
> > > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > > + break;
> > > + }
> >
> > Why not just
> >
> > mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> >
>
> There are two modes in Mixer.
> 1. Background relay mode: all layers off
> 2. Normal mix mode: at least one layer on
> The timing of the two modes is different, so keep using the normal mix
> mode.
> Just set the layer region to 0 when the layer off.
layer_on() and layer_off() does different things. Comparing before turn
on a layer with after turn on->off a layer, the register setting are
different. I would like just restore the register.
Regards,
CK
>
> > > +}
> > > +
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 5:25 ` CK Hu
0 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-22 5:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
Rob Herring, Matthias Brugger, jason-jh . lin, Yongqiang Niu,
DRI Development, moderated list:ARM/Mediatek SoC support, DTML,
linux-kernel, Linux ARM, singo.chang, srv_heupstream
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics conversion in the
> > > external
> > > display path. It handles multiple HDR input types and performs tone
> > > mapping, color space/color format conversion, and then combines
> > > different layers, output the required HDR or SDR signal to the
> > > subsequent display path.
> > >
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > > ++++++++++++++++++++
> > > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > > 8 files changed, 584 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> > >
> > > +
> > > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + if (idx < 4)
> > > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > > >cmdq_base,
> > > + mixer->regs, MIX_SRC_CON,
> > > BIT(idx));
> > > +}
> > > +
> > > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + switch (idx) {
> > > + case 0:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L0_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 1:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L1_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 2:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L2_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 3:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L3_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + default:
> > > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > > + break;
> > > + }
> >
> > Why not just
> >
> > mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> >
>
> There are two modes in Mixer.
> 1. Background relay mode: all layers off
> 2. Normal mix mode: at least one layer on
> The timing of the two modes is different, so keep using the normal mix
> mode.
> Just set the layer region to 0 when the layer off.
layer_on() and layer_off() does different things. Comparing before turn
on a layer with after turn on->off a layer, the register setting are
different. I would like just restore the register.
Regards,
CK
>
> > > +}
> > > +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195
@ 2021-07-22 5:25 ` CK Hu
0 siblings, 0 replies; 52+ messages in thread
From: CK Hu @ 2021-07-22 5:25 UTC (permalink / raw)
To: Nancy.Lin
Cc: Chun-Kuang Hu, srv_heupstream, DTML, David Airlie,
jason-jh . lin, singo.chang, linux-kernel, DRI Development,
Yongqiang Niu, Rob Herring,
moderated list:ARM/Mediatek SoC support, Matthias Brugger,
Linux ARM
Hi, Nancy:
On Thu, 2021-07-22 at 09:32 +0800, Nancy.Lin wrote:
> Hi Chun-Kuang,
>
> On Mon, 2021-07-19 at 07:56 +0800, Chun-Kuang Hu wrote:
> > Hi, Nancy:
> >
> > Nancy.Lin <nancy.lin@mediatek.com> 於 2021年7月17日 週六 下午5:04寫道：
> > >
> > > Add ETHDR module files:
> > > ETHDR is designed for HDR video and graphics conversion in the
> > > external
> > > display path. It handles multiple HDR input types and performs tone
> > > mapping, color space/color format conversion, and then combines
> > > different layers, output the required HDR or SDR signal to the
> > > subsequent display path.
> > >
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/Makefile | 3 +-
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 +
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > > drivers/gpu/drm/mediatek/mtk_ethdr.c | 537
> > > ++++++++++++++++++++
> > > drivers/gpu/drm/mediatek/mtk_ethdr.h | 20 +
> > > 8 files changed, 584 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c
> > > create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h
> > >
> > > +
> > > +void mtk_ethdr_layer_on(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + if (idx < 4)
> > > + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer-
> > > >cmdq_base,
> > > + mixer->regs, MIX_SRC_CON,
> > > BIT(idx));
> > > +}
> > > +
> > > +void mtk_ethdr_layer_off(struct device *dev, unsigned int idx,
> > > + struct cmdq_pkt *cmdq_pkt)
> > > +{
> > > + struct mtk_ethdr *priv = dev_get_drvdata(dev);
> > > + struct mtk_ethdr_comp *mixer = &priv-
> > > >ethdr_comp[ETHDR_MIXER];
> > > +
> > > + dev_dbg(dev, "%s+ idx:%d", __func__, idx);
> > > +
> > > + switch (idx) {
> > > + case 0:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L0_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 1:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L1_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 2:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L2_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + case 3:
> > > + mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > > + mixer->regs, MIX_L3_SRC_SIZE,
> > > ~0);
> > > + break;
> > > + default:
> > > + dev_dbg(dev, "%s Wrong layer ID\n", __func__);
> > > + break;
> > > + }
> >
> > Why not just
> >
> > mtk_ddp_write_mask(cmdq_pkt, 0, &mixer->cmdq_base,
> > mixer->regs, MIX_SRC_CON,
> > BIT(idx));
> >
>
> There are two modes in Mixer.
> 1. Background relay mode: all layers off
> 2. Normal mix mode: at least one layer on
> The timing of the two modes is different, so keep using the normal mix
> mode.
> Just set the layer region to 0 when the layer off.
layer_on() and layer_off() does different things. Comparing before turn
on a layer with after turn on->off a layer, the register setting are
different. I would like just restore the register.
Regards,
CK
>
> > > +}
> > > +
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2021-07-22 6:54 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-17 9:03 [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-07-17 9:03 ` Nancy.Lin
2021-07-17 9:03 ` Nancy.Lin
2021-07-17 9:03 ` [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition " Nancy.Lin
2021-07-17 9:03 ` Nancy.Lin
2021-07-17 9:03 ` Nancy.Lin
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-22 0:59 ` Nancy.Lin
2021-07-22 0:59 ` Nancy.Lin
2021-07-22 0:59 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 02/10] dt-bindings: mediatek: add ethdr " Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 05/10] soc: mediatek: add mtk-mutex " Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 5:25 ` CK Hu
2021-07-22 5:25 ` CK Hu
2021-07-22 5:25 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 07/10] drm/mediatek: add pseudo ovl " Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-20 5:57 ` CK Hu
2021-07-20 5:57 ` CK Hu
2021-07-20 5:57 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 08/10] drm/mediatek: add merge vblank " Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin
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