From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DB0C432BE for ; Tue, 3 Aug 2021 05:37:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B5E460F48 for ; Tue, 3 Aug 2021 05:37:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233813AbhHCFhY (ORCPT ); Tue, 3 Aug 2021 01:37:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233784AbhHCFhW (ORCPT ); Tue, 3 Aug 2021 01:37:22 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DE3BC06175F for ; Mon, 2 Aug 2021 22:37:12 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id e21so22339952pla.5 for ; Mon, 02 Aug 2021 22:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=TzgmYchbci/zhvlgXLAGmYsl7UzG8nnyQecH+/1YGbQ=; b=ES55ynagZ88pg0GPjV6f9YmdPOu1QNR8D/oRa8bNQ/T4u9Nxk+qPpJ5UcbEoQilUyZ u3+F/HwsLgeupDpIDbgs1unBMYXyLlltf0CudKw6Ac1QXWjntXx+kNos74b2LiMtNEcv es9C9D3nxwbVWjEvI1IPePrzDYu2Oqq5AJMmU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=TzgmYchbci/zhvlgXLAGmYsl7UzG8nnyQecH+/1YGbQ=; b=KKpV9YzMF7WExpyuu5ORRKSRQoScdKv+ZqjniKk6AKfLrzkeH8IL4dCcs7BhtJK7Tg nq4WXBgeLgVlpc23ZQUec6+RY5mswWjCNlZ9J+2PzTurRtoBaCOkstW5mN6/KRfBU2Xs cjHAFZvsMk5kHr7aN09te7WmqutgfmQL3pSBOwljkGhobT30vLeIlwPX/g0ZKkxQC56D EdFRZZy0vPRKr/ilB87NDmEKtaKxaUVxEEQn6JfDcIUlFmTjLhg3rgdw8UuQxCpnBEkd J/0Mm/wHEsE9irloKO4hnESmLoCwYfsuZwGmCMiLdCvoLratKi1TzZCOV45JMrpnU/Et QGBA== X-Gm-Message-State: AOAM533BfcXvnuiM8/V4Jar8GjZR+OG1UooiZgtoN/79YlooHu2JUJTx ytB+wgSBmcuTKDSENCp5iGBEmXZyw0DJlznpQw2Wqw== X-Google-Smtp-Source: ABdhPJwy22hM/0nLperLTs7oqlOkW3eLaO6jLCVztbfyp37svS9AhfV/dPAYrDNKRL8a0yAc2zvp451Ro7v8cSdVagE= X-Received: by 2002:a17:902:b788:b029:12c:2888:9589 with SMTP id e8-20020a170902b788b029012c28889589mr17319543pls.60.1627969031860; Mon, 02 Aug 2021 22:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210715121209.31024-1-yong.wu@mediatek.com> <20210715121209.31024-12-yong.wu@mediatek.com> <1626935902.27875.7.camel@mhfsdcap03> <1627540902.13818.3.camel@mhfsdcap03> In-Reply-To: <1627540902.13818.3.camel@mhfsdcap03> From: Ikjoon Jang Date: Tue, 3 Aug 2021 13:37:01 +0800 Message-ID: Subject: Re: [PATCH v2 11/11] memory: mtk-smi: mt8195: Add initial setting for smi-larb To: Yong Wu Cc: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Will Deacon , Robin Murphy , Tomasz Figa , "moderated list:ARM/Mediatek SoC support" , srv_heupstream , open list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Mediatek SoC support" , iommu@lists.linux-foundation.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Jul 29, 2021 at 2:41 PM Yong Wu wrote: > > Hi Ikjoon, > > Just a ping. > > On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu wrote: > > > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > > there are two part: > > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > > 2), Two general setting for each larb. Honestly, I think nobody outside Mediatek will understand this. Can you please update this to be more generic? Like "Apply default bus settings for mt8195, without this, XXX problems can happen.. "? Or for example, adding brief descriptions on what MTK_SMI_FLAG_LARB_THRT_EN, MTK_SMI_FLAG_LARB_SW_FLAG, and MTK_SMI_FLAG_LARB_SW_FLAG[] are for would be better if it's available. > > > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > > like 4K, and this initial setting is enough in mt8195. > > > > > > > > Signed-off-by: Yong Wu > > > > --- > > [...] > > > > struct mtk_smi { > > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > { > > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > > - u32 reg; > > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > > int i; > > > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > > return; > > > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > > + > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > > + > > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > > registers at the same offset? or is this unique feature for mt8195? > > > > All the other Platform's larbs have the same format at the same offset. > > In this case, Do you have some other further comment? If no, I will keep > the current solution for this. Sorry for the late response, I have no further comments or any objections on here. Please go ahead for v3. I just had no idea on the register definitions and wanted to be sure that newly added register definitions are common to all MTK platforms. Thanks! > > Thanks. > > > > > > > > > > + > > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > > reg |= F_MMU_EN; > > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > } > > > > } > > > > > > > > [...] > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_RED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E129AC4338F for ; Tue, 3 Aug 2021 05:37:16 +0000 (UTC) Received: from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8114260EBD for ; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=TzgmYchbci/zhvlgXLAGmYsl7UzG8nnyQecH+/1YGbQ=; b=lCzJwSBArGZbsaNLojo2VFNtORg2r+ve3riQk7yt95YgHBvhivC8xBzVBKdkjnkDhW WYeQNCJflml0M2j4wLt1GkK3mKg7LgT6yW5vrIVr3NhlGeEuvvDdikI6O2+0c8h2RFDv +npRxOgdI7c2aLcDG8sWe/EAl+pya6bu///zHuIhqbUTcm8W+VOF5Ce4rICnZmN6lJnZ VcSQ11zk8NqLuXRbnswtMeMequum8+57C2BGrmYcSjWmmfuO463tBY/AbTTclSnJMfMm omntoyJ+/aWlGIZInJkvM0zX9aRMdN7lnFzm/+DMWzwHRzJblAIyaKBn+BLDJuHFkxM+ N8uA== X-Gm-Message-State: AOAM532rVLJPFYGGXxGDAZQnmTrojChWSHc2i7Ci9z5oV/Red7nNEPQU 8iM78wIW/pcRmGyvDS2791kkdNCZPtsQDu/6Xl/l/A== X-Google-Smtp-Source: ABdhPJwy22hM/0nLperLTs7oqlOkW3eLaO6jLCVztbfyp37svS9AhfV/dPAYrDNKRL8a0yAc2zvp451Ro7v8cSdVagE= X-Received: by 2002:a17:902:b788:b029:12c:2888:9589 with SMTP id e8-20020a170902b788b029012c28889589mr17319543pls.60.1627969031860; Mon, 02 Aug 2021 22:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210715121209.31024-1-yong.wu@mediatek.com> <20210715121209.31024-12-yong.wu@mediatek.com> <1626935902.27875.7.camel@mhfsdcap03> <1627540902.13818.3.camel@mhfsdcap03> In-Reply-To: <1627540902.13818.3.camel@mhfsdcap03> From: Ikjoon Jang Date: Tue, 3 Aug 2021 13:37:01 +0800 Message-ID: Subject: Re: [PATCH v2 11/11] memory: mtk-smi: mt8195: Add initial setting for smi-larb To: Yong Wu Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , srv_heupstream , Krzysztof Kozlowski , Robin Murphy , open list , Krzysztof Kozlowski , iommu@lists.linux-foundation.org, Rob Herring , "moderated list:ARM/Mediatek SoC support" , Matthias Brugger , Will Deacon , "moderated list:ARM/Mediatek SoC support" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi, On Thu, Jul 29, 2021 at 2:41 PM Yong Wu wrote: > > Hi Ikjoon, > > Just a ping. > > On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu wrote: > > > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > > there are two part: > > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > > 2), Two general setting for each larb. Honestly, I think nobody outside Mediatek will understand this. Can you please update this to be more generic? Like "Apply default bus settings for mt8195, without this, XXX problems can happen.. "? Or for example, adding brief descriptions on what MTK_SMI_FLAG_LARB_THRT_EN, MTK_SMI_FLAG_LARB_SW_FLAG, and MTK_SMI_FLAG_LARB_SW_FLAG[] are for would be better if it's available. > > > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > > like 4K, and this initial setting is enough in mt8195. > > > > > > > > Signed-off-by: Yong Wu > > > > --- > > [...] > > > > struct mtk_smi { > > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > { > > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > > - u32 reg; > > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > > int i; > > > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > > return; > > > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > > + > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > > + > > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > > registers at the same offset? or is this unique feature for mt8195? > > > > All the other Platform's larbs have the same format at the same offset. > > In this case, Do you have some other further comment? If no, I will keep > the current solution for this. Sorry for the late response, I have no further comments or any objections on here. Please go ahead for v3. I just had no idea on the register definitions and wanted to be sure that newly added register definitions are common to all MTK platforms. Thanks! > > Thanks. > > > > > > > > > > + > > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > > reg |= F_MMU_EN; > > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > } > > > > } > > > > > > > > [...] > > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCB15C4338F for ; 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Mon, 02 Aug 2021 22:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210715121209.31024-1-yong.wu@mediatek.com> <20210715121209.31024-12-yong.wu@mediatek.com> <1626935902.27875.7.camel@mhfsdcap03> <1627540902.13818.3.camel@mhfsdcap03> In-Reply-To: <1627540902.13818.3.camel@mhfsdcap03> From: Ikjoon Jang Date: Tue, 3 Aug 2021 13:37:01 +0800 Message-ID: Subject: Re: [PATCH v2 11/11] memory: mtk-smi: mt8195: Add initial setting for smi-larb To: Yong Wu Cc: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Will Deacon , Robin Murphy , Tomasz Figa , "moderated list:ARM/Mediatek SoC support" , srv_heupstream , open list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Mediatek SoC support" , iommu@lists.linux-foundation.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210802_223713_526718_2F32D030 X-CRM114-Status: GOOD ( 29.71 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, On Thu, Jul 29, 2021 at 2:41 PM Yong Wu wrote: > > Hi Ikjoon, > > Just a ping. > > On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu wrote: > > > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > > there are two part: > > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > > 2), Two general setting for each larb. Honestly, I think nobody outside Mediatek will understand this. Can you please update this to be more generic? Like "Apply default bus settings for mt8195, without this, XXX problems can happen.. "? Or for example, adding brief descriptions on what MTK_SMI_FLAG_LARB_THRT_EN, MTK_SMI_FLAG_LARB_SW_FLAG, and MTK_SMI_FLAG_LARB_SW_FLAG[] are for would be better if it's available. > > > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > > like 4K, and this initial setting is enough in mt8195. > > > > > > > > Signed-off-by: Yong Wu > > > > --- > > [...] > > > > struct mtk_smi { > > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > { > > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > > - u32 reg; > > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > > int i; > > > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > > return; > > > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > > + > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > > + > > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > > registers at the same offset? or is this unique feature for mt8195? > > > > All the other Platform's larbs have the same format at the same offset. > > In this case, Do you have some other further comment? If no, I will keep > the current solution for this. Sorry for the late response, I have no further comments or any objections on here. Please go ahead for v3. I just had no idea on the register definitions and wanted to be sure that newly added register definitions are common to all MTK platforms. Thanks! > > Thanks. > > > > > > > > > > + > > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > > reg |= F_MMU_EN; > > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > } > > > > } > > > > > > > > [...] > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49845C4320A for ; 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Mon, 02 Aug 2021 22:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210715121209.31024-1-yong.wu@mediatek.com> <20210715121209.31024-12-yong.wu@mediatek.com> <1626935902.27875.7.camel@mhfsdcap03> <1627540902.13818.3.camel@mhfsdcap03> In-Reply-To: <1627540902.13818.3.camel@mhfsdcap03> From: Ikjoon Jang Date: Tue, 3 Aug 2021 13:37:01 +0800 Message-ID: Subject: Re: [PATCH v2 11/11] memory: mtk-smi: mt8195: Add initial setting for smi-larb To: Yong Wu Cc: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Krzysztof Kozlowski , Joerg Roedel , Will Deacon , Robin Murphy , Tomasz Figa , "moderated list:ARM/Mediatek SoC support" , srv_heupstream , open list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Mediatek SoC support" , iommu@lists.linux-foundation.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210802_223713_526527_C42230B3 X-CRM114-Status: GOOD ( 31.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Thu, Jul 29, 2021 at 2:41 PM Yong Wu wrote: > > Hi Ikjoon, > > Just a ping. > > On Thu, 2021-07-22 at 14:38 +0800, Yong Wu wrote: > > On Wed, 2021-07-21 at 21:40 +0800, Ikjoon Jang wrote: > > > On Thu, Jul 15, 2021 at 8:23 PM Yong Wu wrote: > > > > > > > > To improve the performance, We add some initial setting for smi larbs. > > > > there are two part: > > > > 1), Each port has the special ostd(outstanding) value in each larb. > > > > 2), Two general setting for each larb. Honestly, I think nobody outside Mediatek will understand this. Can you please update this to be more generic? Like "Apply default bus settings for mt8195, without this, XXX problems can happen.. "? Or for example, adding brief descriptions on what MTK_SMI_FLAG_LARB_THRT_EN, MTK_SMI_FLAG_LARB_SW_FLAG, and MTK_SMI_FLAG_LARB_SW_FLAG[] are for would be better if it's available. > > > > > > > > In some SoC, this setting maybe changed dynamically for some special case > > > > like 4K, and this initial setting is enough in mt8195. > > > > > > > > Signed-off-by: Yong Wu > > > > --- > > [...] > > > > struct mtk_smi { > > > > @@ -213,12 +228,22 @@ static void mtk_smi_larb_config_port_mt8173(struct device *dev) > > > > static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > { > > > > struct mtk_smi_larb *larb = dev_get_drvdata(dev); > > > > - u32 reg; > > > > + u32 reg, flags_general = larb->larb_gen->flags_general; > > > > + const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; > > > > int i; > > > > > > > > if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) > > > > return; > > > > > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_THRT_EN)) > > > > + writel_relaxed(SMI_LARB_THRT_EN, larb->base + SMI_LARB_CMD_THRT_CON); > > > > + > > > > + if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_LARB_SW_FLAG)) > > > > + writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); > > > > + > > > > + for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) > > > > + writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); > > > > > > All other mtk platform's larbs have the same format for SMI_LARB_OSTDL_PORTx() > > > registers at the same offset? or is this unique feature for mt8195? > > > > All the other Platform's larbs have the same format at the same offset. > > In this case, Do you have some other further comment? If no, I will keep > the current solution for this. Sorry for the late response, I have no further comments or any objections on here. Please go ahead for v3. I just had no idea on the register definitions and wanted to be sure that newly added register definitions are common to all MTK platforms. Thanks! > > Thanks. > > > > > > > > > > + > > > > for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { > > > > reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); > > > > reg |= F_MMU_EN; > > > > @@ -227,6 +252,51 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) > > > > } > > > > } > > > > > > > > [...] > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel