From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21AADC74A5B for ; Wed, 29 Mar 2023 04:29:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229659AbjC2E3i (ORCPT ); Wed, 29 Mar 2023 00:29:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbjC2E3h (ORCPT ); Wed, 29 Mar 2023 00:29:37 -0400 Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A54392127 for ; Tue, 28 Mar 2023 21:29:34 -0700 (PDT) Received: by mail-ot1-x333.google.com with SMTP id r17-20020a05683002f100b006a131458abfso5022909ote.2 for ; Tue, 28 Mar 2023 21:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680064174; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=hHiUbEmnrd1nFCCqx2M3YMHCicrSJZXlbSpyBMomdOk=; b=KsmaC16QBzSHNXRqBdFrH0RtYihBW139YYX86wQCYhhFfeFlBBBxF4y0nKIWI8l8w8 kk5diBMfKiZGhERhWDRXvMPWdi1yo+e9wG9gXdtpQDRxa+W4uS8FMTcirR+IzlwXYgEW gR8EHLTmv5h/bvpWig9I0WteXF9O3ORLuvdp+CoM2OemEXSWvlsJJU/qhhJqrDbpPrqB 16c4OQzIerYKLQmq7TlvmsXuCwIwXBbu9Zces4TTPVsrrYV3drSVnS4zs1cAphHID/Tx mZHmLXiBeq4WQMEROgoNJO3xJNaH4R1PAbn0dcd0s3MJcFn9eOb6dUlHkV/ymDFBEdaT fQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680064174; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hHiUbEmnrd1nFCCqx2M3YMHCicrSJZXlbSpyBMomdOk=; b=2g/+lDvLFzEoaMU4ZF9JlJR+iDWAHOrK4JBmd7SOLJIaZ3S3xJR6VJobvO4zwXxNKo EXQzs6kyI1YKT0Sl485hv0nqA8XhPjPBT18QqxCcNuXa69gH1QRCxZGVe/nwqRIx4tcB 6PrfZzIuoHEcjrpVBoP46fRLh8g1I7APpYRL/v9TbIjOxTa5rhXNdolu56Sn67a3aDmC dld3BHOFUkC7fdlL4ZCe2sihns7Q1KyRvoXZqnnEH9pf9IKiPOf0DgSZaWsk6cygi61j GzstgAxvlpqzi9KM/vI1MSq7zDUYl28Cqbd9B010o6hpp6jOapPLNDUISVdvBWCGnKje +VEQ== X-Gm-Message-State: AO0yUKW0bQca6/MZE2PlIjZvRyE3Jw35FLijjTd0A7gSHaAxm/bEPBX4 5n+dkyoG+/Eu4HbM3z0SLdxbnrsMSSqtYUWSW6byZA== X-Google-Smtp-Source: AK7set/8RfUS9YEx/ISpCCVphMGNUlhdJPVR+2aDQkAPuiZyC4NhdQAqaYBLOS5gwPZl7zeg4mqoRSNc1RZNc/v6rdA= X-Received: by 2002:a9d:634a:0:b0:699:9baa:e545 with SMTP id y10-20020a9d634a000000b006999baae545mr5587158otk.0.1680064173660; Tue, 28 Mar 2023 21:29:33 -0700 (PDT) MIME-Version: 1.0 References: <20230317050637.766317-1-jingzhangos@google.com> <20230317050637.766317-7-jingzhangos@google.com> <86tty6wc67.wl-maz@kernel.org> In-Reply-To: <86tty6wc67.wl-maz@kernel.org> From: Jing Zhang Date: Tue, 28 Mar 2023 21:29:21 -0700 Message-ID: Subject: Re: [PATCH v4 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 To: Marc Zyngier Cc: KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, On Mon, Mar 27, 2023 at 6:34=E2=80=AFAM Marc Zyngier wrote= : > > On Fri, 17 Mar 2023 05:06:37 +0000, > Jing Zhang wrote: > > > > Save KVM sanitised ID register value in ID descriptor (kvm_sys_val). > > Why do we need to store a separate value *beside* the sanitised value > the kernel already holds? > > > Add an init callback for every ID register to setup kvm_sys_val. > > Same question. It is used to store the value further sanitised by KVM, which might be different from the one held by kernel. But as you suggested later, this isn't necessary, we can create KVM sanitised value on the fly since it is cheap. > > > All per VCPU sanitizations are still handled on the fly during ID > > register read and write from userspace. > > An arm64_ftr_bits array is used to indicate writable feature fields. > > > > Refactor writings for ID_AA64PFR0_EL1.[CSV2|CSV3], > > ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon based on utilities > > introduced by ID register descriptor. > > > > No functional change intended. > > > > Co-developed-by: Reiji Watanabe > > Signed-off-by: Reiji Watanabe > > Signed-off-by: Jing Zhang > > --- > > arch/arm64/include/asm/cpufeature.h | 25 +++ > > arch/arm64/include/asm/kvm_host.h | 2 +- > > arch/arm64/kernel/cpufeature.c | 26 +-- > > arch/arm64/kvm/arm.c | 2 +- > > arch/arm64/kvm/id_regs.c | 325 ++++++++++++++++++++-------- > > arch/arm64/kvm/sys_regs.c | 3 +- > > arch/arm64/kvm/sys_regs.h | 2 +- > > 7 files changed, 261 insertions(+), 124 deletions(-) > > > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/a= sm/cpufeature.h > > index fc2c739f48f1..493ec530eefc 100644 > > --- a/arch/arm64/include/asm/cpufeature.h > > +++ b/arch/arm64/include/asm/cpufeature.h > > @@ -64,6 +64,30 @@ struct arm64_ftr_bits { > > s64 safe_val; /* safe value for FTR_EXACT features */ > > }; > > > > +#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, = SAFE_VAL) \ > > + { \ > > + .sign =3D SIGNED, \ > > + .visible =3D VISIBLE, \ > > + .strict =3D STRICT, \ > > + .type =3D TYPE, \ > > + .shift =3D SHIFT, \ > > + .width =3D WIDTH, \ > > + .safe_val =3D SAFE_VAL, \ > > + } > > + > > +/* Define a feature with unsigned values */ > > +#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) = \ > > + __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDT= H, SAFE_VAL) > > + > > +/* Define a feature with a signed value */ > > +#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL= ) \ > > + __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH,= SAFE_VAL) > > + > > +#define ARM64_FTR_END \ > > + { \ > > + .width =3D 0, \ > > + } > > + > > /* > > * Describe the early feature override to the core override code: > > * > > @@ -911,6 +935,7 @@ static inline unsigned int get_vmid_bits(u64 mmfr1) > > return 8; > > } > > > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, s= 64 cur); > > struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id); > > > > extern struct arm64_ftr_override id_aa64mmfr1_override; > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm= /kvm_host.h > > index 102860ba896d..aa83dd79e7ff 100644 > > --- a/arch/arm64/include/asm/kvm_host.h > > +++ b/arch/arm64/include/asm/kvm_host.h > > @@ -1013,7 +1013,7 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *v= cpu, > > long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, > > struct kvm_arm_copy_mte_tags *copy_tags); > > > > -void kvm_arm_set_default_id_regs(struct kvm *kvm); > > +void kvm_arm_init_id_regs(struct kvm *kvm); > > > > /* Guest/host FPSIMD coordination helpers */ > > int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeat= ure.c > > index 23bd2a926b74..e18848ee4b98 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -139,30 +139,6 @@ void dump_cpu_features(void) > > pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); > > } > > > > -#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, = SAFE_VAL) \ > > - { \ > > - .sign =3D SIGNED, \ > > - .visible =3D VISIBLE, \ > > - .strict =3D STRICT, \ > > - .type =3D TYPE, \ > > - .shift =3D SHIFT, \ > > - .width =3D WIDTH, \ > > - .safe_val =3D SAFE_VAL, \ > > - } > > - > > -/* Define a feature with unsigned values */ > > -#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) = \ > > - __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDT= H, SAFE_VAL) > > - > > -/* Define a feature with a signed value */ > > -#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL= ) \ > > - __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH,= SAFE_VAL) > > - > > -#define ARM64_FTR_END \ > > - { \ > > - .width =3D 0, \ > > - } > > - > > static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); > > > > static bool __system_matches_cap(unsigned int n); > > @@ -790,7 +766,7 @@ static u64 arm64_ftr_set_value(const struct arm64_f= tr_bits *ftrp, s64 reg, > > return reg; > > } > > > > -static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64= new, > > +s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, > > s64 cur) > > { > > s64 ret =3D 0; > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > index fb2de2cb98cb..e539d9ca9d01 100644 > > --- a/arch/arm64/kvm/arm.c > > +++ b/arch/arm64/kvm/arm.c > > @@ -135,7 +135,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long= type) > > /* The maximum number of VCPUs is limited by the host's GIC model= */ > > kvm->max_vcpus =3D kvm_arm_default_max_vcpus(); > > > > - kvm_arm_set_default_id_regs(kvm); > > + kvm_arm_init_id_regs(kvm); > > How about picking the name once and for all from the first patch? Sure, will do. > > > kvm_arm_init_hypercalls(kvm); > > > > return 0; > > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c > > index 9956c99d20f7..726b810b6e06 100644 > > --- a/arch/arm64/kvm/id_regs.c > > +++ b/arch/arm64/kvm/id_regs.c > > @@ -18,10 +18,88 @@ > > > > #include "sys_regs.h" > > > > +/* > > + * Number of entries in id_reg_desc's ftr_bits[] (Number of 4 bits fie= lds > > + * in 64 bit register + 1 entry for a terminator entry). > > + */ > > +#define FTR_FIELDS_NUM 17 > > Please see SMFR0_EL1 for an example of a sysreg that doesn't follow > the 4bits-per-field format. I expect to see more of those in the > future. > > And given that this is always a variable set of fields, why do we need > to define this as a fixed array that only bloats the structure? I'd > rather see a variable array in a side structure. > Yes, it makes more sense to use a variable array here. Do you have any suggestions? xarray? > > + > > struct id_reg_desc { > > const struct sys_reg_desc reg_desc; > > + /* > > + * KVM sanitised ID register value. > > + * It is the default value for per VM emulated ID register. > > + */ > > + u64 kvm_sys_val; > > + /* > > + * Used to validate the ID register values with arm64_check_featu= res(). > > + * The last item in the array must be terminated by an item whose > > + * width field is zero as that is expected by arm64_check_feature= s(). > > + * Only feature bits defined in this array are writable. > > + */ > > + struct arm64_ftr_bits ftr_bits[FTR_FIELDS_NUM]; > > + > > + /* > > + * Basically init() is used to setup the KVM sanitised value > > + * stored in kvm_sys_val. > > + */ > > + void (*init)(struct id_reg_desc *idr); > > Given that this callback only builds the value from the sanitised > view, and that it is very cheap (only a set of masking), why do we > bother keeping the value around? It would also allow this structure to > be kept *const*, something that is extremely desirable. > > Also, why do we need an init() method when each sysreg already have a > reset() method? Surely this should be the same thing... > > My gut feeling is that we should only have a callback returning the > limit value computed on the fly. Sure, will use a callback to return the limit value on the fly. > > > }; > > > > +static struct id_reg_desc id_reg_descs[]; > > + > > +/** > > + * arm64_check_features() - Check if a feature register value constitu= tes > > + * a subset of features indicated by @limit. > > + * > > + * @ftrp: Pointer to an array of arm64_ftr_bits. It must be terminated= by > > + * an item whose width field is zero. > > + * @val: The feature register value to check > > + * @limit: The limit value of the feature register > > + * > > + * This function will check if each feature field of @val is the "safe= " value > > + * against @limit based on @ftrp[], each of which specifies the target= field > > + * (shift, width), whether or not the field is for a signed value (sig= n), > > + * how the field is determined to be "safe" (type), and the safe value > > + * (safe_val) when type =3D=3D FTR_EXACT (safe_val won't be used by th= is > > + * function when type !=3D FTR_EXACT). Any other fields in arm64_ftr_b= its > > + * won't be used by this function. If a field value in @val is the sam= e > > + * as the one in @limit, it is always considered the safe value regard= less > > + * of the type. For register fields that are not in @ftrp[], only the = value > > + * in @limit is considered the safe value. > > + * > > + * Return: 0 if all the fields are safe. Otherwise, return negative er= rno. > > + */ > > +static int arm64_check_features(const struct arm64_ftr_bits *ftrp, u64= val, u64 limit) > > +{ > > + u64 mask =3D 0; > > + > > + for (; ftrp->width; ftrp++) { > > + s64 f_val, f_lim, safe_val; > > + > > + f_val =3D arm64_ftr_value(ftrp, val); > > + f_lim =3D arm64_ftr_value(ftrp, limit); > > + mask |=3D arm64_ftr_mask(ftrp); > > + > > + if (f_val =3D=3D f_lim) > > + safe_val =3D f_val; > > + else > > + safe_val =3D arm64_ftr_safe_value(ftrp, f_val, f= _lim); > > + > > + if (safe_val !=3D f_val) > > + return -E2BIG; > > + } > > + > > + /* > > + * For fields that are not indicated in ftrp, values in limit are= the > > + * safe values. > > + */ > > + if ((val & ~mask) !=3D (limit & ~mask)) > > + return -E2BIG; > > + > > + return 0; > > +} > > I have the feeling that the core code already implements something > similar... Right, it is similar to update_cpu_ftr_reg() in cpufeature.c. But that function can't meet the needs here. > > > + > > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) > > { > > if (kvm_vcpu_has_pmu(vcpu)) > > @@ -67,7 +145,6 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcpu,= u32 id) > > case SYS_ID_AA64PFR0_EL1: > > if (!vcpu_has_sve(vcpu)) > > val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE)= ; > > - val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); > > if (kvm_vgic_global_state.type =3D=3D VGIC_V3) { > > val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC)= ; > > val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR= 0_EL1_GIC), 1); > > @@ -94,15 +171,10 @@ u64 kvm_arm_read_id_reg(const struct kvm_vcpu *vcp= u, u32 id) > > val &=3D ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFx= T); > > break; > > case SYS_ID_AA64DFR0_EL1: > > - /* Limit debug to ARMv8.0 */ > > - val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); > > - val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_De= bugVer), 6); > > /* Set PMUver to the required version */ > > val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PM= UVer), > > vcpu_pmuver(vcpu)); > > - /* Hide SPE from guests */ > > - val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); > > break; > > case SYS_ID_DFR0_EL1: > > val &=3D ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > @@ -161,9 +233,15 @@ static int get_id_reg(struct kvm_vcpu *vcpu, const= struct sys_reg_desc *rd, > > static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc= *rd, > > u64 val) > > { > > - /* This is what we mean by invariant: you can't change it. */ > > - if (val !=3D read_id_reg(vcpu, rd)) > > - return -EINVAL; > > + int ret; > > + int id =3D reg_to_encoding(rd); > > + > > + ret =3D arm64_check_features(id_reg_descs[IDREG_IDX(id)].ftr_bits= , val, > > + id_reg_descs[IDREG_IDX(id)].kvm_sys_va= l); > > + if (ret) > > + return ret; > > + > > + vcpu->kvm->arch.id_regs[IDREG_IDX(id)] =3D val; > > > > return 0; > > } > > @@ -197,12 +275,47 @@ static unsigned int aa32_id_visibility(const stru= ct kvm_vcpu *vcpu, > > return id_visibility(vcpu, r); > > } > > > > +static void init_id_reg(struct id_reg_desc *idr) > > +{ > > + idr->kvm_sys_val =3D read_sanitised_ftr_reg(reg_to_encoding(&idr-= >reg_desc)); > > +} > > + > > +static void init_id_aa64pfr0_el1(struct id_reg_desc *idr) > > +{ > > + u64 val; > > + u32 id =3D reg_to_encoding(&idr->reg_desc); > > + > > + val =3D read_sanitised_ftr_reg(id); > > + /* > > + * The default is to expose CSV2 =3D=3D 1 if the HW isn't affecte= d. > > + * Although this is a per-CPU feature, we make it global because > > + * asymmetric systems are just a nuisance. > > + * > > + * Userspace can override this as long as it doesn't promise > > + * the impossible. > > + */ > > + if (arm64_get_spectre_v2_state() =3D=3D SPECTRE_UNAFFECTED) { > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CS= V2), 1); > > + } > > + if (arm64_get_meltdown_state() =3D=3D SPECTRE_UNAFFECTED) { > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CS= V3), 1); > > + } > > + > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); > > + > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); > > What? Why? What if I have a GICv2? What if I have no GIC? :-) Forgot how these two lines got in here. Will remove them. > > > + > > + idr->kvm_sys_val =3D val; > > +} > > How does this compose with the runtime feature reduction that takes > place in access_nested_id_reg()? kvm_sys_val is used as the initial value for the per VM idregs, which is passed into access_nested_id_reg in function access_id_reg(). > > > + > > static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > > const struct sys_reg_desc *rd, > > u64 val) > > { > > u8 csv2, csv3; > > - u64 sval =3D val; > > > > /* > > * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as > > @@ -220,16 +333,29 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *v= cpu, > > (csv3 && arm64_get_meltdown_state() !=3D SPECTRE_UNAFFECTED)) > > return -EINVAL; > > > > - /* We can only differ with CSV[23], and anything else is an error= */ > > - val ^=3D read_id_reg(vcpu, rd); > > - val &=3D ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | > > - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); > > - if (val) > > - return -EINVAL; > > + return set_id_reg(vcpu, rd, val); > > +} > > > > - vcpu->kvm->arch.id_regs[IDREG_IDX(reg_to_encoding(rd))] =3D sval; > > +static void init_id_aa64dfr0_el1(struct id_reg_desc *idr) > > +{ > > + u64 val; > > + u32 id =3D reg_to_encoding(&idr->reg_desc); > > > > - return 0; > > + val =3D read_sanitised_ftr_reg(id); > > + /* Limit debug to ARMv8.0 */ > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer),= 6); > > + /* > > + * Initialise the default PMUver before there is a chance to > > + * create an actual PMU. > > + */ > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), > > + kvm_arm_pmu_get_pmuver_limit()); > > + /* Hide SPE from guests */ > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); > > + > > + idr->kvm_sys_val =3D val; > > } > > > > static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > > @@ -238,6 +364,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcp= u, > > { > > u8 pmuver, host_pmuver; > > bool valid_pmu; > > + int ret; > > > > host_pmuver =3D kvm_arm_pmu_get_pmuver_limit(); > > > > @@ -257,39 +384,58 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *v= cpu, > > if (kvm_vcpu_has_pmu(vcpu) !=3D valid_pmu) > > return -EINVAL; > > > > - /* We can only differ with PMUver, and anything else is an error = */ > > - val ^=3D read_id_reg(vcpu, rd); > > - val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > - if (val) > > - return -EINVAL; > > - > > if (valid_pmu) { > > mutex_lock(&vcpu->kvm->lock); > > - vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] &= =3D > > - ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > - vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] |= =3D > > - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMU= Ver), pmuver); > > + ret =3D set_id_reg(vcpu, rd, val); > > + if (ret) > > + return ret; > > Next stop, Deadlock City, our final destination. Will fix it. > > > > > vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] &=3D > > ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] |=3D = FIELD_PREP( > > ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), = pmuver_to_perfmon(pmuver)); > > mutex_unlock(&vcpu->kvm->lock); > > - } else if (pmuver =3D=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) { > > - set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->a= rch.flags); > > } else { > > - clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm-= >arch.flags); > > + /* We can only differ with PMUver, and anything else is a= n error */ > > + val ^=3D read_id_reg(vcpu, rd); > > + val &=3D ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > + if (val) > > + return -EINVAL; > > I find it very odd that you add all this infrastructure to check for > writable fields, and yet have to keep this comparison. It makes me > thing that the data structures are not necessarily the right ones. This comparison is still here because for this patch, we don't allow the writable for the whole ID register and in the path of invalid pmu, the set_id_reg() (This function will do all the checks) is not called. This comparison can be removed as long as the whole ID reg is enabled writable. > > > + > > + if (pmuver =3D=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) > > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu= ->kvm->arch.flags); > > + else > > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vc= pu->kvm->arch.flags); > > + > > } > > > > return 0; > > } > > > > +static void init_id_dfr0_el1(struct id_reg_desc *idr) > > +{ > > + u64 val; > > + u32 id =3D reg_to_encoding(&idr->reg_desc); > > + > > + val =3D read_sanitised_ftr_reg(id); > > + /* > > + * Initialise the default PMUver before there is a chance to > > + * create an actual PMU. > > + */ > > + val &=3D ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > + val |=3D FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), > > + kvm_arm_pmu_get_pmuver_limit()); > > + > > + idr->kvm_sys_val =3D val; > > +} > > + > > static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > > const struct sys_reg_desc *rd, > > u64 val) > > { > > u8 perfmon, host_perfmon; > > bool valid_pmu; > > + int ret; > > > > host_perfmon =3D pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()= ); > > > > @@ -310,42 +456,46 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > > if (kvm_vcpu_has_pmu(vcpu) !=3D valid_pmu) > > return -EINVAL; > > > > - /* We can only differ with PerfMon, and anything else is an error= */ > > - val ^=3D read_id_reg(vcpu, rd); > > - val &=3D ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > - if (val) > > - return -EINVAL; > > - > > if (valid_pmu) { > > mutex_lock(&vcpu->kvm->lock); > > - vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] &=3D > > - ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > - vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_DFR0_EL1)] |=3D = FIELD_PREP( > > - ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), perfmon)= ; > > + ret =3D set_id_reg(vcpu, rd, val); > > + if (ret) > > + return ret; > > Same player, shoot again. Will fix it. > > > > > vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] &= =3D > > ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > vcpu->kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] |= =3D FIELD_PREP( > > ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), perfm= on_to_pmuver(perfmon)); > > mutex_unlock(&vcpu->kvm->lock); > > - } else if (perfmon =3D=3D ID_DFR0_EL1_PerfMon_IMPDEF) { > > - set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm->a= rch.flags); > > } else { > > - clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu->kvm-= >arch.flags); > > + /* We can only differ with PerfMon, and anything else is = an error */ > > + val ^=3D read_id_reg(vcpu, rd); > > + val &=3D ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); > > + if (val) > > + return -EINVAL; > > + > > + if (perfmon =3D=3D ID_DFR0_EL1_PerfMon_IMPDEF) > > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu= ->kvm->arch.flags); > > + else > > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vc= pu->kvm->arch.flags); > > } > > Same remarks. > > > > > return 0; > > } > > > > /* sys_reg_desc initialiser for known cpufeature ID registers */ > > +#define SYS_DESC_SANITISED(name) { \ > > + SYS_DESC(SYS_##name), \ > > + .access =3D access_id_reg, \ > > + .get_user =3D get_id_reg, \ > > + .set_user =3D set_id_reg, \ > > + .visibility =3D id_visibility, \ > > +} > > + > > #define ID_SANITISED(name) { \ > > - .reg_desc =3D { \ > > - SYS_DESC(SYS_##name), \ > > - .access =3D access_id_reg, \ > > - .get_user =3D get_id_reg, \ > > - .set_user =3D set_id_reg, \ > > - .visibility =3D id_visibility, \ > > - }, \ > > + .reg_desc =3D SYS_DESC_SANITISED(name), \ > > + .ftr_bits =3D { ARM64_FTR_END, }, \ > > + .init =3D init_id_reg, \ > > } > > > > /* sys_reg_desc initialiser for known cpufeature ID registers */ > > @@ -357,6 +507,8 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > > .set_user =3D set_id_reg, \ > > .visibility =3D aa32_id_visibility, \ > > }, \ > > + .ftr_bits =3D { ARM64_FTR_END, }, \ > > + .init =3D init_id_reg, \ > > } > > > > /* > > @@ -372,6 +524,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > > .set_user =3D set_id_reg, \ > > .visibility =3D raz_visibility \ > > }, \ > > + .ftr_bits =3D { ARM64_FTR_END, }, \ > > } > > > > /* > > @@ -387,9 +540,10 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, > > .set_user =3D set_id_reg, \ > > .visibility =3D raz_visibility, \ > > }, \ > > + .ftr_bits =3D { ARM64_FTR_END, }, \ > > } > > > > -static const struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] =3D { > > +static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] =3D { > > /* > > * ID regs: all ID_SANITISED() entries here must have correspondi= ng > > * entries in arm64_ftr_regs[]. > > @@ -405,6 +559,11 @@ static const struct id_reg_desc id_reg_descs[KVM_A= RM_ID_REG_NUM] =3D { > > .get_user =3D get_id_reg, > > .set_user =3D set_id_dfr0_el1, > > .visibility =3D aa32_id_visibility, }, > > + .ftr_bits =3D { > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > > + ID_DFR0_EL1_PerfMon_SHIFT, ID_DFR0_EL1_PerfMon_WI= DTH, 0), > > + ARM64_FTR_END, }, > > + .init =3D init_id_dfr0_el1, > > }, > > ID_HIDDEN(ID_AFR0_EL1), > > AA32_ID_SANITISED(ID_MMFR0_EL1), > > @@ -439,6 +598,13 @@ static const struct id_reg_desc id_reg_descs[KVM_A= RM_ID_REG_NUM] =3D { > > .access =3D access_id_reg, > > .get_user =3D get_id_reg, > > .set_user =3D set_id_aa64pfr0_el1, }, > > + .ftr_bits =3D { > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > > + ID_AA64PFR0_EL1_CSV2_SHIFT, ID_AA64PFR0_EL1_CSV2_= WIDTH, 0), > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > > + ID_AA64PFR0_EL1_CSV3_SHIFT, ID_AA64PFR0_EL1_CSV3_= WIDTH, 0), > > + ARM64_FTR_END, }, > > It really strikes me that you are 100% duplicating data that is > already in ftr_id_aa64pfr0[]. Only that this is a subset of the > existing data. > > You could instead have your 'init()' callback return a pair of values: > the default value based on the sanitised one, and a 64bit mask. At > this stage, you'll realise that this looks a lot like the feature > override, and that you should be able to reuse some of the existing > infrastructure. Sure, will try to improve this by your suggestion. > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. Thanks, Jing From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C03CDC6FD18 for ; Wed, 29 Mar 2023 04:30:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Froj7hbxLtNuZ0l22qwiwSqmdKdRET62MGk0KtKVIBE=; b=h/bdwSuLKiS2UQ PzfBQ6zs6RHLaQfevGUYViYmOKy7g8uP9tyy7TzPX4AGK8wnWY/AGF4fOy+q1Kgtt4T1u1inxioO3 GbJH/0NtO8JZRRHFi6cFCpssQrjkaKX8m+FHONSxjs2Q3dy+n6TuNh27WDxjusgAtjh+Zkn7ay8+V q+vKcGQLYZBEd4NmE9DBhvM9UKMEernox4bzHSAfNqmymX0lmQSifRfFHZiV8spQFXysR8e8o35nA r897U+grKqjftJOkeT4MBfLUK7b4gEiTg559thE83q4+rfDih7ik6mJtwZSlGPEj3VNifhNc2vXNt K4Tvd82+VMJbFsoD6zTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phNRM-00GYvl-2z; Wed, 29 Mar 2023 04:29:40 +0000 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1phNRI-00GYur-0q for linux-arm-kernel@lists.infradead.org; Wed, 29 Mar 2023 04:29:39 +0000 Received: by mail-ot1-x32b.google.com with SMTP id k14-20020a9d700e000000b0069faa923e7eso7584729otj.10 for ; Tue, 28 Mar 2023 21:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680064174; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=hHiUbEmnrd1nFCCqx2M3YMHCicrSJZXlbSpyBMomdOk=; b=KsmaC16QBzSHNXRqBdFrH0RtYihBW139YYX86wQCYhhFfeFlBBBxF4y0nKIWI8l8w8 kk5diBMfKiZGhERhWDRXvMPWdi1yo+e9wG9gXdtpQDRxa+W4uS8FMTcirR+IzlwXYgEW gR8EHLTmv5h/bvpWig9I0WteXF9O3ORLuvdp+CoM2OemEXSWvlsJJU/qhhJqrDbpPrqB 16c4OQzIerYKLQmq7TlvmsXuCwIwXBbu9Zces4TTPVsrrYV3drSVnS4zs1cAphHID/Tx mZHmLXiBeq4WQMEROgoNJO3xJNaH4R1PAbn0dcd0s3MJcFn9eOb6dUlHkV/ymDFBEdaT fQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680064174; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hHiUbEmnrd1nFCCqx2M3YMHCicrSJZXlbSpyBMomdOk=; b=c1buY99JYKLMb+O1xMKV4bOvFpfbBQcUyMOgAUh3mPLdfO4sphkzuSiTBy07bQrG4A 6DeEGB/229ffh7LVcbGr+/ipuAW2GlrhlrI4q7cfudgthMeBwd2xYfduwoHQXOqB3LDm jQFRKjQ9yTlZos4DNWH24mk01NZAd/1aPuFgn3Jow0S38iY3Yd3oE7jXEE4k4nVjXb0c d7SrU3zAU7rsbtbheklWUer2bp945oVXp5o2iXCSoR5rQrpw/6hAVOkLhaSaXiElK7rq BvZur8K+KfBiqmSpzpZPc+epIFVkFmsz5IeI697S+VKwEhHkh8U59mcdZHz73powkv/0 fZpw== X-Gm-Message-State: AO0yUKX0jZKhVubsJeQdDRwQPWDonP5CJMXaHld11ZQHr8qz6sS2Gl8Z Ry4lvwtblPb9eRZY1jY2BPAkNzNbEw7Dc52JdoWkfw== X-Google-Smtp-Source: AK7set/8RfUS9YEx/ISpCCVphMGNUlhdJPVR+2aDQkAPuiZyC4NhdQAqaYBLOS5gwPZl7zeg4mqoRSNc1RZNc/v6rdA= X-Received: by 2002:a9d:634a:0:b0:699:9baa:e545 with SMTP id y10-20020a9d634a000000b006999baae545mr5587158otk.0.1680064173660; Tue, 28 Mar 2023 21:29:33 -0700 (PDT) MIME-Version: 1.0 References: <20230317050637.766317-1-jingzhangos@google.com> <20230317050637.766317-7-jingzhangos@google.com> <86tty6wc67.wl-maz@kernel.org> In-Reply-To: <86tty6wc67.wl-maz@kernel.org> From: Jing Zhang Date: Tue, 28 Mar 2023 21:29:21 -0700 Message-ID: Subject: Re: [PATCH v4 6/6] KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 To: Marc Zyngier Cc: KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230328_212936_306002_108B18DF X-CRM114-Status: GOOD ( 54.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgTWFyYywKCk9uIE1vbiwgTWFyIDI3LCAyMDIzIGF0IDY6MzTigK9BTSBNYXJjIFp5bmdpZXIg PG1hekBrZXJuZWwub3JnPiB3cm90ZToKPgo+IE9uIEZyaSwgMTcgTWFyIDIwMjMgMDU6MDY6Mzcg KzAwMDAsCj4gSmluZyBaaGFuZyA8amluZ3poYW5nb3NAZ29vZ2xlLmNvbT4gd3JvdGU6Cj4gPgo+ ID4gU2F2ZSBLVk0gc2FuaXRpc2VkIElEIHJlZ2lzdGVyIHZhbHVlIGluIElEIGRlc2NyaXB0b3Ig KGt2bV9zeXNfdmFsKS4KPgo+IFdoeSBkbyB3ZSBuZWVkIHRvIHN0b3JlIGEgc2VwYXJhdGUgdmFs dWUgKmJlc2lkZSogdGhlIHNhbml0aXNlZCB2YWx1ZQo+IHRoZSBrZXJuZWwgYWxyZWFkeSBob2xk cz8KPgo+ID4gQWRkIGFuIGluaXQgY2FsbGJhY2sgZm9yIGV2ZXJ5IElEIHJlZ2lzdGVyIHRvIHNl dHVwIGt2bV9zeXNfdmFsLgo+Cj4gU2FtZSBxdWVzdGlvbi4KSXQgaXMgdXNlZCB0byBzdG9yZSB0 aGUgdmFsdWUgZnVydGhlciBzYW5pdGlzZWQgYnkgS1ZNLCB3aGljaCBtaWdodCBiZQpkaWZmZXJl bnQgZnJvbSB0aGUgb25lIGhlbGQgYnkga2VybmVsLiBCdXQgYXMgeW91IHN1Z2dlc3RlZCBsYXRl ciwKdGhpcyBpc24ndCBuZWNlc3NhcnksIHdlIGNhbiBjcmVhdGUgS1ZNIHNhbml0aXNlZCB2YWx1 ZSBvbiB0aGUgZmx5CnNpbmNlIGl0IGlzIGNoZWFwLgo+Cj4gPiBBbGwgcGVyIFZDUFUgc2FuaXRp emF0aW9ucyBhcmUgc3RpbGwgaGFuZGxlZCBvbiB0aGUgZmx5IGR1cmluZyBJRAo+ID4gcmVnaXN0 ZXIgcmVhZCBhbmQgd3JpdGUgZnJvbSB1c2Vyc3BhY2UuCj4gPiBBbiBhcm02NF9mdHJfYml0cyBh cnJheSBpcyB1c2VkIHRvIGluZGljYXRlIHdyaXRhYmxlIGZlYXR1cmUgZmllbGRzLgo+ID4KPiA+ IFJlZmFjdG9yIHdyaXRpbmdzIGZvciBJRF9BQTY0UEZSMF9FTDEuW0NTVjJ8Q1NWM10sCj4gPiBJ RF9BQTY0REZSMF9FTDEuUE1VVmVyIGFuZCBJRF9ERlIwX0VMRi5QZXJmTW9uIGJhc2VkIG9uIHV0 aWxpdGllcwo+ID4gaW50cm9kdWNlZCBieSBJRCByZWdpc3RlciBkZXNjcmlwdG9yLgo+ID4KPiA+ IE5vIGZ1bmN0aW9uYWwgY2hhbmdlIGludGVuZGVkLgo+ID4KPiA+IENvLWRldmVsb3BlZC1ieTog UmVpamkgV2F0YW5hYmUgPHJlaWppd0Bnb29nbGUuY29tPgo+ID4gU2lnbmVkLW9mZi1ieTogUmVp amkgV2F0YW5hYmUgPHJlaWppd0Bnb29nbGUuY29tPgo+ID4gU2lnbmVkLW9mZi1ieTogSmluZyBa aGFuZyA8amluZ3poYW5nb3NAZ29vZ2xlLmNvbT4KPiA+IC0tLQo+ID4gIGFyY2gvYXJtNjQvaW5j bHVkZS9hc20vY3B1ZmVhdHVyZS5oIHwgIDI1ICsrKwo+ID4gIGFyY2gvYXJtNjQvaW5jbHVkZS9h c20va3ZtX2hvc3QuaCAgIHwgICAyICstCj4gPiAgYXJjaC9hcm02NC9rZXJuZWwvY3B1ZmVhdHVy ZS5jICAgICAgfCAgMjYgKy0tCj4gPiAgYXJjaC9hcm02NC9rdm0vYXJtLmMgICAgICAgICAgICAg ICAgfCAgIDIgKy0KPiA+ICBhcmNoL2FybTY0L2t2bS9pZF9yZWdzLmMgICAgICAgICAgICB8IDMy NSArKysrKysrKysrKysrKysrKysrKy0tLS0tLS0tCj4gPiAgYXJjaC9hcm02NC9rdm0vc3lzX3Jl Z3MuYyAgICAgICAgICAgfCAgIDMgKy0KPiA+ICBhcmNoL2FybTY0L2t2bS9zeXNfcmVncy5oICAg ICAgICAgICB8ICAgMiArLQo+ID4gIDcgZmlsZXMgY2hhbmdlZCwgMjYxIGluc2VydGlvbnMoKyks IDEyNCBkZWxldGlvbnMoLSkKPiA+Cj4gPiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9pbmNsdWRl L2FzbS9jcHVmZWF0dXJlLmggYi9hcmNoL2FybTY0L2luY2x1ZGUvYXNtL2NwdWZlYXR1cmUuaAo+ ID4gaW5kZXggZmMyYzczOWY0OGYxLi40OTNlYzUzMGVlZmMgMTAwNjQ0Cj4gPiAtLS0gYS9hcmNo L2FybTY0L2luY2x1ZGUvYXNtL2NwdWZlYXR1cmUuaAo+ID4gKysrIGIvYXJjaC9hcm02NC9pbmNs dWRlL2FzbS9jcHVmZWF0dXJlLmgKPiA+IEBAIC02NCw2ICs2NCwzMCBAQCBzdHJ1Y3QgYXJtNjRf ZnRyX2JpdHMgewo+ID4gICAgICAgczY0ICAgICAgICAgICAgIHNhZmVfdmFsOyAvKiBzYWZlIHZh bHVlIGZvciBGVFJfRVhBQ1QgZmVhdHVyZXMgKi8KPiA+ICB9Owo+ID4KPiA+ICsjZGVmaW5lIF9f QVJNNjRfRlRSX0JJVFMoU0lHTkVELCBWSVNJQkxFLCBTVFJJQ1QsIFRZUEUsIFNISUZULCBXSURU SCwgU0FGRV9WQUwpIFwKPiA+ICsgICAgIHsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnNpZ24gPSBTSUdORUQsICAgICAg ICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnZpc2libGUgPSBWSVNJQkxF LCAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnN0cmljdCA9IFNUUklD VCwgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnR5cGUgPSBUWVBF LCAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnNoaWZ0ID0g U0hJRlQsICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLndpZHRo ID0gV0lEVEgsICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgICAgICAgICAgLnNh ZmVfdmFsID0gU0FGRV9WQUwsICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgIH0KPiA+ICsK PiA+ICsvKiBEZWZpbmUgYSBmZWF0dXJlIHdpdGggdW5zaWduZWQgdmFsdWVzICovCj4gPiArI2Rl ZmluZSBBUk02NF9GVFJfQklUUyhWSVNJQkxFLCBTVFJJQ1QsIFRZUEUsIFNISUZULCBXSURUSCwg U0FGRV9WQUwpIFwKPiA+ICsgICAgIF9fQVJNNjRfRlRSX0JJVFMoRlRSX1VOU0lHTkVELCBWSVNJ QkxFLCBTVFJJQ1QsIFRZUEUsIFNISUZULCBXSURUSCwgU0FGRV9WQUwpCj4gPiArCj4gPiArLyog RGVmaW5lIGEgZmVhdHVyZSB3aXRoIGEgc2lnbmVkIHZhbHVlICovCj4gPiArI2RlZmluZSBTX0FS TTY0X0ZUUl9CSVRTKFZJU0lCTEUsIFNUUklDVCwgVFlQRSwgU0hJRlQsIFdJRFRILCBTQUZFX1ZB TCkgXAo+ID4gKyAgICAgX19BUk02NF9GVFJfQklUUyhGVFJfU0lHTkVELCBWSVNJQkxFLCBTVFJJ Q1QsIFRZUEUsIFNISUZULCBXSURUSCwgU0FGRV9WQUwpCj4gPiArCj4gPiArI2RlZmluZSBBUk02 NF9GVFJfRU5EICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsg ICAgIHsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ ICsgICAgICAgICAgICAgLndpZHRoID0gMCwgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwK PiA+ICsgICAgIH0KPiA+ICsKPiA+ICAvKgo+ID4gICAqIERlc2NyaWJlIHRoZSBlYXJseSBmZWF0 dXJlIG92ZXJyaWRlIHRvIHRoZSBjb3JlIG92ZXJyaWRlIGNvZGU6Cj4gPiAgICoKPiA+IEBAIC05 MTEsNiArOTM1LDcgQEAgc3RhdGljIGlubGluZSB1bnNpZ25lZCBpbnQgZ2V0X3ZtaWRfYml0cyh1 NjQgbW1mcjEpCj4gPiAgICAgICByZXR1cm4gODsKPiA+ICB9Cj4gPgo+ID4gK3M2NCBhcm02NF9m dHJfc2FmZV92YWx1ZShjb25zdCBzdHJ1Y3QgYXJtNjRfZnRyX2JpdHMgKmZ0cnAsIHM2NCBuZXcs IHM2NCBjdXIpOwo+ID4gIHN0cnVjdCBhcm02NF9mdHJfcmVnICpnZXRfYXJtNjRfZnRyX3JlZyh1 MzIgc3lzX2lkKTsKPiA+Cj4gPiAgZXh0ZXJuIHN0cnVjdCBhcm02NF9mdHJfb3ZlcnJpZGUgaWRf YWE2NG1tZnIxX292ZXJyaWRlOwo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9h c20va3ZtX2hvc3QuaCBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaAo+ID4gaW5k ZXggMTAyODYwYmE4OTZkLi5hYTgzZGQ3OWU3ZmYgMTAwNjQ0Cj4gPiAtLS0gYS9hcmNoL2FybTY0 L2luY2x1ZGUvYXNtL2t2bV9ob3N0LmgKPiA+ICsrKyBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20v a3ZtX2hvc3QuaAo+ID4gQEAgLTEwMTMsNyArMTAxMyw3IEBAIGludCBrdm1fYXJtX3ZjcHVfYXJj aF9oYXNfYXR0cihzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiAgbG9uZyBrdm1fdm1faW9jdGxf bXRlX2NvcHlfdGFncyhzdHJ1Y3Qga3ZtICprdm0sCj4gPiAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICBzdHJ1Y3Qga3ZtX2FybV9jb3B5X210ZV90YWdzICpjb3B5X3RhZ3MpOwo+ID4KPiA+ IC12b2lkIGt2bV9hcm1fc2V0X2RlZmF1bHRfaWRfcmVncyhzdHJ1Y3Qga3ZtICprdm0pOwo+ID4g K3ZvaWQga3ZtX2FybV9pbml0X2lkX3JlZ3Moc3RydWN0IGt2bSAqa3ZtKTsKPiA+Cj4gPiAgLyog R3Vlc3QvaG9zdCBGUFNJTUQgY29vcmRpbmF0aW9uIGhlbHBlcnMgKi8KPiA+ICBpbnQga3ZtX2Fy Y2hfdmNwdV9ydW5fbWFwX2ZwKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSk7Cj4gPiBkaWZmIC0tZ2l0 IGEvYXJjaC9hcm02NC9rZXJuZWwvY3B1ZmVhdHVyZS5jIGIvYXJjaC9hcm02NC9rZXJuZWwvY3B1 ZmVhdHVyZS5jCj4gPiBpbmRleCAyM2JkMmE5MjZiNzQuLmUxODg0OGVlNGI5OCAxMDA2NDQKPiA+ IC0tLSBhL2FyY2gvYXJtNjQva2VybmVsL2NwdWZlYXR1cmUuYwo+ID4gKysrIGIvYXJjaC9hcm02 NC9rZXJuZWwvY3B1ZmVhdHVyZS5jCj4gPiBAQCAtMTM5LDMwICsxMzksNiBAQCB2b2lkIGR1bXBf Y3B1X2ZlYXR1cmVzKHZvaWQpCj4gPiAgICAgICBwcl9lbWVyZygiMHglKnBiXG4iLCBBUk02NF9O Q0FQUywgJmNwdV9od2NhcHMpOwo+ID4gIH0KPiA+Cj4gPiAtI2RlZmluZSBfX0FSTTY0X0ZUUl9C SVRTKFNJR05FRCwgVklTSUJMRSwgU1RSSUNULCBUWVBFLCBTSElGVCwgV0lEVEgsIFNBRkVfVkFM KSBcCj4gPiAtICAgICB7ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICBcCj4gPiAtICAgICAgICAgICAgIC5zaWduID0gU0lHTkVELCAgICAgICAgICAgICAgICAg ICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC52aXNpYmxlID0gVklTSUJMRSwgICAgICAgICAg ICAgICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC5zdHJpY3QgPSBTVFJJQ1QsICAgICAgICAg ICAgICAgICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC50eXBlID0gVFlQRSwgICAgICAgICAg ICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC5zaGlmdCA9IFNISUZULCAgICAg ICAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC53aWR0aCA9IFdJRFRILCAg ICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICAgICAgICAgIC5zYWZlX3ZhbCA9IFNB RkVfVkFMLCAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICB9Cj4gPiAtCj4gPiAtLyogRGVm aW5lIGEgZmVhdHVyZSB3aXRoIHVuc2lnbmVkIHZhbHVlcyAqLwo+ID4gLSNkZWZpbmUgQVJNNjRf RlRSX0JJVFMoVklTSUJMRSwgU1RSSUNULCBUWVBFLCBTSElGVCwgV0lEVEgsIFNBRkVfVkFMKSBc Cj4gPiAtICAgICBfX0FSTTY0X0ZUUl9CSVRTKEZUUl9VTlNJR05FRCwgVklTSUJMRSwgU1RSSUNU LCBUWVBFLCBTSElGVCwgV0lEVEgsIFNBRkVfVkFMKQo+ID4gLQo+ID4gLS8qIERlZmluZSBhIGZl YXR1cmUgd2l0aCBhIHNpZ25lZCB2YWx1ZSAqLwo+ID4gLSNkZWZpbmUgU19BUk02NF9GVFJfQklU UyhWSVNJQkxFLCBTVFJJQ1QsIFRZUEUsIFNISUZULCBXSURUSCwgU0FGRV9WQUwpIFwKPiA+IC0g ICAgIF9fQVJNNjRfRlRSX0JJVFMoRlRSX1NJR05FRCwgVklTSUJMRSwgU1RSSUNULCBUWVBFLCBT SElGVCwgV0lEVEgsIFNBRkVfVkFMKQo+ID4gLQo+ID4gLSNkZWZpbmUgQVJNNjRfRlRSX0VORCAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICB7ICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICAgICAg ICAgIC53aWR0aCA9IDAsICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiAtICAgICB9 Cj4gPiAtCj4gPiAgc3RhdGljIHZvaWQgY3B1X2VuYWJsZV9jbnAoc3RydWN0IGFybTY0X2NwdV9j YXBhYmlsaXRpZXMgY29uc3QgKmNhcCk7Cj4gPgo+ID4gIHN0YXRpYyBib29sIF9fc3lzdGVtX21h dGNoZXNfY2FwKHVuc2lnbmVkIGludCBuKTsKPiA+IEBAIC03OTAsNyArNzY2LDcgQEAgc3RhdGlj IHU2NCBhcm02NF9mdHJfc2V0X3ZhbHVlKGNvbnN0IHN0cnVjdCBhcm02NF9mdHJfYml0cyAqZnRy cCwgczY0IHJlZywKPiA+ICAgICAgIHJldHVybiByZWc7Cj4gPiAgfQo+ID4KPiA+IC1zdGF0aWMg czY0IGFybTY0X2Z0cl9zYWZlX3ZhbHVlKGNvbnN0IHN0cnVjdCBhcm02NF9mdHJfYml0cyAqZnRy cCwgczY0IG5ldywKPiA+ICtzNjQgYXJtNjRfZnRyX3NhZmVfdmFsdWUoY29uc3Qgc3RydWN0IGFy bTY0X2Z0cl9iaXRzICpmdHJwLCBzNjQgbmV3LAo+ID4gICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgczY0IGN1cikKPiA+ICB7Cj4gPiAgICAgICBzNjQgcmV0ID0gMDsKPiA+IGRpZmYgLS1n aXQgYS9hcmNoL2FybTY0L2t2bS9hcm0uYyBiL2FyY2gvYXJtNjQva3ZtL2FybS5jCj4gPiBpbmRl eCBmYjJkZTJjYjk4Y2IuLmU1MzlkOWNhOWQwMSAxMDA2NDQKPiA+IC0tLSBhL2FyY2gvYXJtNjQv a3ZtL2FybS5jCj4gPiArKysgYi9hcmNoL2FybTY0L2t2bS9hcm0uYwo+ID4gQEAgLTEzNSw3ICsx MzUsNyBAQCBpbnQga3ZtX2FyY2hfaW5pdF92bShzdHJ1Y3Qga3ZtICprdm0sIHVuc2lnbmVkIGxv bmcgdHlwZSkKPiA+ICAgICAgIC8qIFRoZSBtYXhpbXVtIG51bWJlciBvZiBWQ1BVcyBpcyBsaW1p dGVkIGJ5IHRoZSBob3N0J3MgR0lDIG1vZGVsICovCj4gPiAgICAgICBrdm0tPm1heF92Y3B1cyA9 IGt2bV9hcm1fZGVmYXVsdF9tYXhfdmNwdXMoKTsKPiA+Cj4gPiAtICAgICBrdm1fYXJtX3NldF9k ZWZhdWx0X2lkX3JlZ3Moa3ZtKTsKPiA+ICsgICAgIGt2bV9hcm1faW5pdF9pZF9yZWdzKGt2bSk7 Cj4KPiBIb3cgYWJvdXQgcGlja2luZyB0aGUgbmFtZSBvbmNlIGFuZCBmb3IgYWxsIGZyb20gdGhl IGZpcnN0IHBhdGNoPwpTdXJlLCB3aWxsIGRvLgo+Cj4gPiAgICAgICBrdm1fYXJtX2luaXRfaHlw ZXJjYWxscyhrdm0pOwo+ID4KPiA+ICAgICAgIHJldHVybiAwOwo+ID4gZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtNjQva3ZtL2lkX3JlZ3MuYyBiL2FyY2gvYXJtNjQva3ZtL2lkX3JlZ3MuYwo+ID4gaW5k ZXggOTk1NmM5OWQyMGY3Li43MjZiODEwYjZlMDYgMTAwNjQ0Cj4gPiAtLS0gYS9hcmNoL2FybTY0 L2t2bS9pZF9yZWdzLmMKPiA+ICsrKyBiL2FyY2gvYXJtNjQva3ZtL2lkX3JlZ3MuYwo+ID4gQEAg LTE4LDEwICsxOCw4OCBAQAo+ID4KPiA+ICAjaW5jbHVkZSAic3lzX3JlZ3MuaCIKPiA+Cj4gPiAr LyoKPiA+ICsgKiBOdW1iZXIgb2YgZW50cmllcyBpbiBpZF9yZWdfZGVzYydzIGZ0cl9iaXRzW10g KE51bWJlciBvZiA0IGJpdHMgZmllbGRzCj4gPiArICogaW4gNjQgYml0IHJlZ2lzdGVyICsgMSBl bnRyeSBmb3IgYSB0ZXJtaW5hdG9yIGVudHJ5KS4KPiA+ICsgKi8KPiA+ICsjZGVmaW5lICAgICAg RlRSX0ZJRUxEU19OVU0gIDE3Cj4KPiBQbGVhc2Ugc2VlIFNNRlIwX0VMMSBmb3IgYW4gZXhhbXBs ZSBvZiBhIHN5c3JlZyB0aGF0IGRvZXNuJ3QgZm9sbG93Cj4gdGhlIDRiaXRzLXBlci1maWVsZCBm b3JtYXQuIEkgZXhwZWN0IHRvIHNlZSBtb3JlIG9mIHRob3NlIGluIHRoZQo+IGZ1dHVyZS4KPgo+ IEFuZCBnaXZlbiB0aGF0IHRoaXMgaXMgYWx3YXlzIGEgdmFyaWFibGUgc2V0IG9mIGZpZWxkcywg d2h5IGRvIHdlIG5lZWQKPiB0byBkZWZpbmUgdGhpcyBhcyBhIGZpeGVkIGFycmF5IHRoYXQgb25s eSBibG9hdHMgdGhlIHN0cnVjdHVyZT8gSSdkCj4gcmF0aGVyIHNlZSBhIHZhcmlhYmxlIGFycmF5 IGluIGEgc2lkZSBzdHJ1Y3R1cmUuCj4KWWVzLCBpdCBtYWtlcyBtb3JlIHNlbnNlIHRvIHVzZSBh IHZhcmlhYmxlIGFycmF5IGhlcmUuIERvIHlvdSBoYXZlIGFueQpzdWdnZXN0aW9ucz8geGFycmF5 Pwo+ID4gKwo+ID4gIHN0cnVjdCBpZF9yZWdfZGVzYyB7Cj4gPiAgICAgICBjb25zdCBzdHJ1Y3Qg c3lzX3JlZ19kZXNjICAgICAgIHJlZ19kZXNjOwo+ID4gKyAgICAgLyoKPiA+ICsgICAgICAqIEtW TSBzYW5pdGlzZWQgSUQgcmVnaXN0ZXIgdmFsdWUuCj4gPiArICAgICAgKiBJdCBpcyB0aGUgZGVm YXVsdCB2YWx1ZSBmb3IgcGVyIFZNIGVtdWxhdGVkIElEIHJlZ2lzdGVyLgo+ID4gKyAgICAgICov Cj4gPiArICAgICB1NjQga3ZtX3N5c192YWw7Cj4gPiArICAgICAvKgo+ID4gKyAgICAgICogVXNl ZCB0byB2YWxpZGF0ZSB0aGUgSUQgcmVnaXN0ZXIgdmFsdWVzIHdpdGggYXJtNjRfY2hlY2tfZmVh dHVyZXMoKS4KPiA+ICsgICAgICAqIFRoZSBsYXN0IGl0ZW0gaW4gdGhlIGFycmF5IG11c3QgYmUg dGVybWluYXRlZCBieSBhbiBpdGVtIHdob3NlCj4gPiArICAgICAgKiB3aWR0aCBmaWVsZCBpcyB6 ZXJvIGFzIHRoYXQgaXMgZXhwZWN0ZWQgYnkgYXJtNjRfY2hlY2tfZmVhdHVyZXMoKS4KPiA+ICsg ICAgICAqIE9ubHkgZmVhdHVyZSBiaXRzIGRlZmluZWQgaW4gdGhpcyBhcnJheSBhcmUgd3JpdGFi bGUuCj4gPiArICAgICAgKi8KPiA+ICsgICAgIHN0cnVjdCBhcm02NF9mdHJfYml0cyAgIGZ0cl9i aXRzW0ZUUl9GSUVMRFNfTlVNXTsKPiA+ICsKPiA+ICsgICAgIC8qCj4gPiArICAgICAgKiBCYXNp Y2FsbHkgaW5pdCgpIGlzIHVzZWQgdG8gc2V0dXAgdGhlIEtWTSBzYW5pdGlzZWQgdmFsdWUKPiA+ ICsgICAgICAqIHN0b3JlZCBpbiBrdm1fc3lzX3ZhbC4KPiA+ICsgICAgICAqLwo+ID4gKyAgICAg dm9pZCAoKmluaXQpKHN0cnVjdCBpZF9yZWdfZGVzYyAqaWRyKTsKPgo+IEdpdmVuIHRoYXQgdGhp cyBjYWxsYmFjayBvbmx5IGJ1aWxkcyB0aGUgdmFsdWUgZnJvbSB0aGUgc2FuaXRpc2VkCj4gdmll dywgYW5kIHRoYXQgaXQgaXMgdmVyeSBjaGVhcCAob25seSBhIHNldCBvZiBtYXNraW5nKSwgd2h5 IGRvIHdlCj4gYm90aGVyIGtlZXBpbmcgdGhlIHZhbHVlIGFyb3VuZD8gSXQgd291bGQgYWxzbyBh bGxvdyB0aGlzIHN0cnVjdHVyZSB0bwo+IGJlIGtlcHQgKmNvbnN0Kiwgc29tZXRoaW5nIHRoYXQg aXMgZXh0cmVtZWx5IGRlc2lyYWJsZS4KPgo+IEFsc28sIHdoeSBkbyB3ZSBuZWVkIGFuIGluaXQo KSBtZXRob2Qgd2hlbiBlYWNoIHN5c3JlZyBhbHJlYWR5IGhhdmUgYQo+IHJlc2V0KCkgbWV0aG9k PyBTdXJlbHkgdGhpcyBzaG91bGQgYmUgdGhlIHNhbWUgdGhpbmcuLi4KPgo+IE15IGd1dCBmZWVs aW5nIGlzIHRoYXQgd2Ugc2hvdWxkIG9ubHkgaGF2ZSBhIGNhbGxiYWNrIHJldHVybmluZyB0aGUK PiBsaW1pdCB2YWx1ZSBjb21wdXRlZCBvbiB0aGUgZmx5LgpTdXJlLCB3aWxsIHVzZSBhIGNhbGxi YWNrIHRvIHJldHVybiB0aGUgbGltaXQgdmFsdWUgb24gdGhlIGZseS4KPgo+ID4gIH07Cj4gPgo+ ID4gK3N0YXRpYyBzdHJ1Y3QgaWRfcmVnX2Rlc2MgaWRfcmVnX2Rlc2NzW107Cj4gPiArCj4gPiAr LyoqCj4gPiArICogYXJtNjRfY2hlY2tfZmVhdHVyZXMoKSAtIENoZWNrIGlmIGEgZmVhdHVyZSBy ZWdpc3RlciB2YWx1ZSBjb25zdGl0dXRlcwo+ID4gKyAqIGEgc3Vic2V0IG9mIGZlYXR1cmVzIGlu ZGljYXRlZCBieSBAbGltaXQuCj4gPiArICoKPiA+ICsgKiBAZnRycDogUG9pbnRlciB0byBhbiBh cnJheSBvZiBhcm02NF9mdHJfYml0cy4gSXQgbXVzdCBiZSB0ZXJtaW5hdGVkIGJ5Cj4gPiArICog YW4gaXRlbSB3aG9zZSB3aWR0aCBmaWVsZCBpcyB6ZXJvLgo+ID4gKyAqIEB2YWw6IFRoZSBmZWF0 dXJlIHJlZ2lzdGVyIHZhbHVlIHRvIGNoZWNrCj4gPiArICogQGxpbWl0OiBUaGUgbGltaXQgdmFs dWUgb2YgdGhlIGZlYXR1cmUgcmVnaXN0ZXIKPiA+ICsgKgo+ID4gKyAqIFRoaXMgZnVuY3Rpb24g d2lsbCBjaGVjayBpZiBlYWNoIGZlYXR1cmUgZmllbGQgb2YgQHZhbCBpcyB0aGUgInNhZmUiIHZh bHVlCj4gPiArICogYWdhaW5zdCBAbGltaXQgYmFzZWQgb24gQGZ0cnBbXSwgZWFjaCBvZiB3aGlj aCBzcGVjaWZpZXMgdGhlIHRhcmdldCBmaWVsZAo+ID4gKyAqIChzaGlmdCwgd2lkdGgpLCB3aGV0 aGVyIG9yIG5vdCB0aGUgZmllbGQgaXMgZm9yIGEgc2lnbmVkIHZhbHVlIChzaWduKSwKPiA+ICsg KiBob3cgdGhlIGZpZWxkIGlzIGRldGVybWluZWQgdG8gYmUgInNhZmUiICh0eXBlKSwgYW5kIHRo ZSBzYWZlIHZhbHVlCj4gPiArICogKHNhZmVfdmFsKSB3aGVuIHR5cGUgPT0gRlRSX0VYQUNUIChz YWZlX3ZhbCB3b24ndCBiZSB1c2VkIGJ5IHRoaXMKPiA+ICsgKiBmdW5jdGlvbiB3aGVuIHR5cGUg IT0gRlRSX0VYQUNUKS4gQW55IG90aGVyIGZpZWxkcyBpbiBhcm02NF9mdHJfYml0cwo+ID4gKyAq IHdvbid0IGJlIHVzZWQgYnkgdGhpcyBmdW5jdGlvbi4gSWYgYSBmaWVsZCB2YWx1ZSBpbiBAdmFs IGlzIHRoZSBzYW1lCj4gPiArICogYXMgdGhlIG9uZSBpbiBAbGltaXQsIGl0IGlzIGFsd2F5cyBj b25zaWRlcmVkIHRoZSBzYWZlIHZhbHVlIHJlZ2FyZGxlc3MKPiA+ICsgKiBvZiB0aGUgdHlwZS4g Rm9yIHJlZ2lzdGVyIGZpZWxkcyB0aGF0IGFyZSBub3QgaW4gQGZ0cnBbXSwgb25seSB0aGUgdmFs dWUKPiA+ICsgKiBpbiBAbGltaXQgaXMgY29uc2lkZXJlZCB0aGUgc2FmZSB2YWx1ZS4KPiA+ICsg Kgo+ID4gKyAqIFJldHVybjogMCBpZiBhbGwgdGhlIGZpZWxkcyBhcmUgc2FmZS4gT3RoZXJ3aXNl LCByZXR1cm4gbmVnYXRpdmUgZXJybm8uCj4gPiArICovCj4gPiArc3RhdGljIGludCBhcm02NF9j aGVja19mZWF0dXJlcyhjb25zdCBzdHJ1Y3QgYXJtNjRfZnRyX2JpdHMgKmZ0cnAsIHU2NCB2YWws IHU2NCBsaW1pdCkKPiA+ICt7Cj4gPiArICAgICB1NjQgbWFzayA9IDA7Cj4gPiArCj4gPiArICAg ICBmb3IgKDsgZnRycC0+d2lkdGg7IGZ0cnArKykgewo+ID4gKyAgICAgICAgICAgICBzNjQgZl92 YWwsIGZfbGltLCBzYWZlX3ZhbDsKPiA+ICsKPiA+ICsgICAgICAgICAgICAgZl92YWwgPSBhcm02 NF9mdHJfdmFsdWUoZnRycCwgdmFsKTsKPiA+ICsgICAgICAgICAgICAgZl9saW0gPSBhcm02NF9m dHJfdmFsdWUoZnRycCwgbGltaXQpOwo+ID4gKyAgICAgICAgICAgICBtYXNrIHw9IGFybTY0X2Z0 cl9tYXNrKGZ0cnApOwo+ID4gKwo+ID4gKyAgICAgICAgICAgICBpZiAoZl92YWwgPT0gZl9saW0p Cj4gPiArICAgICAgICAgICAgICAgICAgICAgc2FmZV92YWwgPSBmX3ZhbDsKPiA+ICsgICAgICAg ICAgICAgZWxzZQo+ID4gKyAgICAgICAgICAgICAgICAgICAgIHNhZmVfdmFsID0gIGFybTY0X2Z0 cl9zYWZlX3ZhbHVlKGZ0cnAsIGZfdmFsLCBmX2xpbSk7Cj4gPiArCj4gPiArICAgICAgICAgICAg IGlmIChzYWZlX3ZhbCAhPSBmX3ZhbCkKPiA+ICsgICAgICAgICAgICAgICAgICAgICByZXR1cm4g LUUyQklHOwo+ID4gKyAgICAgfQo+ID4gKwo+ID4gKyAgICAgLyoKPiA+ICsgICAgICAqIEZvciBm aWVsZHMgdGhhdCBhcmUgbm90IGluZGljYXRlZCBpbiBmdHJwLCB2YWx1ZXMgaW4gbGltaXQgYXJl IHRoZQo+ID4gKyAgICAgICogc2FmZSB2YWx1ZXMuCj4gPiArICAgICAgKi8KPiA+ICsgICAgIGlm ICgodmFsICYgfm1hc2spICE9IChsaW1pdCAmIH5tYXNrKSkKPiA+ICsgICAgICAgICAgICAgcmV0 dXJuIC1FMkJJRzsKPiA+ICsKPiA+ICsgICAgIHJldHVybiAwOwo+ID4gK30KPgo+IEkgaGF2ZSB0 aGUgZmVlbGluZyB0aGF0IHRoZSBjb3JlIGNvZGUgYWxyZWFkeSBpbXBsZW1lbnRzIHNvbWV0aGlu Zwo+IHNpbWlsYXIuLi4KUmlnaHQsIGl0IGlzIHNpbWlsYXIgdG8gdXBkYXRlX2NwdV9mdHJfcmVn KCkgaW4gY3B1ZmVhdHVyZS5jLiBCdXQgdGhhdApmdW5jdGlvbiBjYW4ndCBtZWV0IHRoZSBuZWVk cyBoZXJlLgo+Cj4gPiArCj4gPiAgc3RhdGljIHU4IHZjcHVfcG11dmVyKGNvbnN0IHN0cnVjdCBr dm1fdmNwdSAqdmNwdSkKPiA+ICB7Cj4gPiAgICAgICBpZiAoa3ZtX3ZjcHVfaGFzX3BtdSh2Y3B1 KSkKPiA+IEBAIC02Nyw3ICsxNDUsNiBAQCB1NjQga3ZtX2FybV9yZWFkX2lkX3JlZyhjb25zdCBz dHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHUzMiBpZCkKPiA+ICAgICAgIGNhc2UgU1lTX0lEX0FBNjRQ RlIwX0VMMToKPiA+ICAgICAgICAgICAgICAgaWYgKCF2Y3B1X2hhc19zdmUodmNwdSkpCj4gPiAg ICAgICAgICAgICAgICAgICAgICAgdmFsICY9IH5BUk02NF9GRUFUVVJFX01BU0soSURfQUE2NFBG UjBfRUwxX1NWRSk7Cj4gPiAtICAgICAgICAgICAgIHZhbCAmPSB+QVJNNjRfRkVBVFVSRV9NQVNL KElEX0FBNjRQRlIwX0VMMV9BTVUpOwo+ID4gICAgICAgICAgICAgICBpZiAoa3ZtX3ZnaWNfZ2xv YmFsX3N0YXRlLnR5cGUgPT0gVkdJQ19WMykgewo+ID4gICAgICAgICAgICAgICAgICAgICAgIHZh bCAmPSB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRQRlIwX0VMMV9HSUMpOwo+ID4gICAgICAg ICAgICAgICAgICAgICAgIHZhbCB8PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9B QTY0UEZSMF9FTDFfR0lDKSwgMSk7Cj4gPiBAQCAtOTQsMTUgKzE3MSwxMCBAQCB1NjQga3ZtX2Fy bV9yZWFkX2lkX3JlZyhjb25zdCBzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHUzMiBpZCkKPiA+ICAg ICAgICAgICAgICAgICAgICAgICB2YWwgJj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0SVNB UjJfRUwxX1dGeFQpOwo+ID4gICAgICAgICAgICAgICBicmVhazsKPiA+ICAgICAgIGNhc2UgU1lT X0lEX0FBNjRERlIwX0VMMToKPiA+IC0gICAgICAgICAgICAgLyogTGltaXQgZGVidWcgdG8gQVJN djguMCAqLwo+ID4gLSAgICAgICAgICAgICB2YWwgJj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9B QTY0REZSMF9FTDFfRGVidWdWZXIpOwo+ID4gLSAgICAgICAgICAgICB2YWwgfD0gRklFTERfUFJF UChBUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwxX0RlYnVnVmVyKSwgNik7Cj4gPiAg ICAgICAgICAgICAgIC8qIFNldCBQTVV2ZXIgdG8gdGhlIHJlcXVpcmVkIHZlcnNpb24gKi8KPiA+ ICAgICAgICAgICAgICAgdmFsICY9IH5BUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwx X1BNVVZlcik7Cj4gPiAgICAgICAgICAgICAgIHZhbCB8PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRV UkVfTUFTSyhJRF9BQTY0REZSMF9FTDFfUE1VVmVyKSwKPiA+ICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgdmNwdV9wbXV2ZXIodmNwdSkpOwo+ID4gLSAgICAgICAgICAgICAvKiBIaWRl IFNQRSBmcm9tIGd1ZXN0cyAqLwo+ID4gLSAgICAgICAgICAgICB2YWwgJj0gfkFSTTY0X0ZFQVRV UkVfTUFTSyhJRF9BQTY0REZSMF9FTDFfUE1TVmVyKTsKPiA+ICAgICAgICAgICAgICAgYnJlYWs7 Cj4gPiAgICAgICBjYXNlIFNZU19JRF9ERlIwX0VMMToKPiA+ICAgICAgICAgICAgICAgdmFsICY9 IH5BUk02NF9GRUFUVVJFX01BU0soSURfREZSMF9FTDFfUGVyZk1vbik7Cj4gPiBAQCAtMTYxLDkg KzIzMywxNSBAQCBzdGF0aWMgaW50IGdldF9pZF9yZWcoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCBj b25zdCBzdHJ1Y3Qgc3lzX3JlZ19kZXNjICpyZCwKPiA+ICBzdGF0aWMgaW50IHNldF9pZF9yZWco c3RydWN0IGt2bV92Y3B1ICp2Y3B1LCBjb25zdCBzdHJ1Y3Qgc3lzX3JlZ19kZXNjICpyZCwKPiA+ ICAgICAgICAgICAgICAgICAgICAgdTY0IHZhbCkKPiA+ICB7Cj4gPiAtICAgICAvKiBUaGlzIGlz IHdoYXQgd2UgbWVhbiBieSBpbnZhcmlhbnQ6IHlvdSBjYW4ndCBjaGFuZ2UgaXQuICovCj4gPiAt ICAgICBpZiAodmFsICE9IHJlYWRfaWRfcmVnKHZjcHUsIHJkKSkKPiA+IC0gICAgICAgICAgICAg cmV0dXJuIC1FSU5WQUw7Cj4gPiArICAgICBpbnQgcmV0Owo+ID4gKyAgICAgaW50IGlkID0gcmVn X3RvX2VuY29kaW5nKHJkKTsKPiA+ICsKPiA+ICsgICAgIHJldCA9IGFybTY0X2NoZWNrX2ZlYXR1 cmVzKGlkX3JlZ19kZXNjc1tJRFJFR19JRFgoaWQpXS5mdHJfYml0cywgdmFsLAo+ID4gKyAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgaWRfcmVnX2Rlc2NzW0lEUkVHX0lEWChpZCldLmt2 bV9zeXNfdmFsKTsKPiA+ICsgICAgIGlmIChyZXQpCj4gPiArICAgICAgICAgICAgIHJldHVybiBy ZXQ7Cj4gPiArCj4gPiArICAgICB2Y3B1LT5rdm0tPmFyY2guaWRfcmVnc1tJRFJFR19JRFgoaWQp XSA9IHZhbDsKPiA+Cj4gPiAgICAgICByZXR1cm4gMDsKPiA+ICB9Cj4gPiBAQCAtMTk3LDEyICsy NzUsNDcgQEAgc3RhdGljIHVuc2lnbmVkIGludCBhYTMyX2lkX3Zpc2liaWxpdHkoY29uc3Qgc3Ry dWN0IGt2bV92Y3B1ICp2Y3B1LAo+ID4gICAgICAgcmV0dXJuIGlkX3Zpc2liaWxpdHkodmNwdSwg cik7Cj4gPiAgfQo+ID4KPiA+ICtzdGF0aWMgdm9pZCBpbml0X2lkX3JlZyhzdHJ1Y3QgaWRfcmVn X2Rlc2MgKmlkcikKPiA+ICt7Cj4gPiArICAgICBpZHItPmt2bV9zeXNfdmFsID0gcmVhZF9zYW5p dGlzZWRfZnRyX3JlZyhyZWdfdG9fZW5jb2RpbmcoJmlkci0+cmVnX2Rlc2MpKTsKPiA+ICt9Cj4g PiArCj4gPiArc3RhdGljIHZvaWQgaW5pdF9pZF9hYTY0cGZyMF9lbDEoc3RydWN0IGlkX3JlZ19k ZXNjICppZHIpCj4gPiArewo+ID4gKyAgICAgdTY0IHZhbDsKPiA+ICsgICAgIHUzMiBpZCA9IHJl Z190b19lbmNvZGluZygmaWRyLT5yZWdfZGVzYyk7Cj4gPiArCj4gPiArICAgICB2YWwgPSByZWFk X3Nhbml0aXNlZF9mdHJfcmVnKGlkKTsKPiA+ICsgICAgIC8qCj4gPiArICAgICAgKiBUaGUgZGVm YXVsdCBpcyB0byBleHBvc2UgQ1NWMiA9PSAxIGlmIHRoZSBIVyBpc24ndCBhZmZlY3RlZC4KPiA+ ICsgICAgICAqIEFsdGhvdWdoIHRoaXMgaXMgYSBwZXItQ1BVIGZlYXR1cmUsIHdlIG1ha2UgaXQg Z2xvYmFsIGJlY2F1c2UKPiA+ICsgICAgICAqIGFzeW1tZXRyaWMgc3lzdGVtcyBhcmUganVzdCBh IG51aXNhbmNlLgo+ID4gKyAgICAgICoKPiA+ICsgICAgICAqIFVzZXJzcGFjZSBjYW4gb3ZlcnJp ZGUgdGhpcyBhcyBsb25nIGFzIGl0IGRvZXNuJ3QgcHJvbWlzZQo+ID4gKyAgICAgICogdGhlIGlt cG9zc2libGUuCj4gPiArICAgICAgKi8KPiA+ICsgICAgIGlmIChhcm02NF9nZXRfc3BlY3RyZV92 Ml9zdGF0ZSgpID09IFNQRUNUUkVfVU5BRkZFQ1RFRCkgewo+ID4gKyAgICAgICAgICAgICB2YWwg Jj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9FTDFfQ1NWMik7Cj4gPiArICAgICAg ICAgICAgIHZhbCB8PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9F TDFfQ1NWMiksIDEpOwo+ID4gKyAgICAgfQo+ID4gKyAgICAgaWYgKGFybTY0X2dldF9tZWx0ZG93 bl9zdGF0ZSgpID09IFNQRUNUUkVfVU5BRkZFQ1RFRCkgewo+ID4gKyAgICAgICAgICAgICB2YWwg Jj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9FTDFfQ1NWMyk7Cj4gPiArICAgICAg ICAgICAgIHZhbCB8PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9F TDFfQ1NWMyksIDEpOwo+ID4gKyAgICAgfQo+ID4gKwo+ID4gKyAgICAgdmFsICY9IH5BUk02NF9G RUFUVVJFX01BU0soSURfQUE2NFBGUjBfRUwxX0FNVSk7Cj4gPiArCj4gPiArICAgICB2YWwgJj0g fkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9FTDFfR0lDKTsKPiA+ICsgICAgIHZhbCB8 PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0UEZSMF9FTDFfR0lDKSwgMSk7 Cj4KPiBXaGF0PyBXaHk/IFdoYXQgaWYgSSBoYXZlIGEgR0lDdjI/IFdoYXQgaWYgSSBoYXZlIG5v IEdJQz8KOi0pIEZvcmdvdCBob3cgdGhlc2UgdHdvIGxpbmVzIGdvdCBpbiBoZXJlLiBXaWxsIHJl bW92ZSB0aGVtLgo+Cj4gPiArCj4gPiArICAgICBpZHItPmt2bV9zeXNfdmFsID0gdmFsOwo+ID4g K30KPgo+IEhvdyBkb2VzIHRoaXMgY29tcG9zZSB3aXRoIHRoZSBydW50aW1lIGZlYXR1cmUgcmVk dWN0aW9uIHRoYXQgdGFrZXMKPiBwbGFjZSBpbiBhY2Nlc3NfbmVzdGVkX2lkX3JlZygpPwprdm1f c3lzX3ZhbCBpcyB1c2VkIGFzIHRoZSBpbml0aWFsIHZhbHVlIGZvciB0aGUgcGVyIFZNIGlkcmVn cywgd2hpY2gKaXMgcGFzc2VkIGludG8gYWNjZXNzX25lc3RlZF9pZF9yZWcgaW4gZnVuY3Rpb24g YWNjZXNzX2lkX3JlZygpLgo+Cj4gPiArCj4gPiAgc3RhdGljIGludCBzZXRfaWRfYWE2NHBmcjBf ZWwxKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwKPiA+ICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgY29uc3Qgc3RydWN0IHN5c19yZWdfZGVzYyAqcmQsCj4gPiAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIHU2NCB2YWwpCj4gPiAgewo+ID4gICAgICAgdTggY3N2MiwgY3N2MzsKPiA+IC0g ICAgIHU2NCBzdmFsID0gdmFsOwo+ID4KPiA+ICAgICAgIC8qCj4gPiAgICAgICAgKiBBbGxvdyBB QTY0UEZSMF9FTDEuQ1NWMiB0byBiZSBzZXQgZnJvbSB1c2Vyc3BhY2UgYXMgbG9uZyBhcwo+ID4g QEAgLTIyMCwxNiArMzMzLDI5IEBAIHN0YXRpYyBpbnQgc2V0X2lkX2FhNjRwZnIwX2VsMShzdHJ1 Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiAgICAgICAgICAgKGNzdjMgJiYgYXJtNjRfZ2V0X21lbHRk b3duX3N0YXRlKCkgIT0gU1BFQ1RSRV9VTkFGRkVDVEVEKSkKPiA+ICAgICAgICAgICAgICAgcmV0 dXJuIC1FSU5WQUw7Cj4gPgo+ID4gLSAgICAgLyogV2UgY2FuIG9ubHkgZGlmZmVyIHdpdGggQ1NW WzIzXSwgYW5kIGFueXRoaW5nIGVsc2UgaXMgYW4gZXJyb3IgKi8KPiA+IC0gICAgIHZhbCBePSBy ZWFkX2lkX3JlZyh2Y3B1LCByZCk7Cj4gPiAtICAgICB2YWwgJj0gfihBUk02NF9GRUFUVVJFX01B U0soSURfQUE2NFBGUjBfRUwxX0NTVjIpIHwKPiA+IC0gICAgICAgICAgICAgIEFSTTY0X0ZFQVRV UkVfTUFTSyhJRF9BQTY0UEZSMF9FTDFfQ1NWMykpOwo+ID4gLSAgICAgaWYgKHZhbCkKPiA+IC0g ICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4gPiArICAgICByZXR1cm4gc2V0X2lkX3JlZyh2 Y3B1LCByZCwgdmFsKTsKPiA+ICt9Cj4gPgo+ID4gLSAgICAgdmNwdS0+a3ZtLT5hcmNoLmlkX3Jl Z3NbSURSRUdfSURYKHJlZ190b19lbmNvZGluZyhyZCkpXSA9IHN2YWw7Cj4gPiArc3RhdGljIHZv aWQgaW5pdF9pZF9hYTY0ZGZyMF9lbDEoc3RydWN0IGlkX3JlZ19kZXNjICppZHIpCj4gPiArewo+ ID4gKyAgICAgdTY0IHZhbDsKPiA+ICsgICAgIHUzMiBpZCA9IHJlZ190b19lbmNvZGluZygmaWRy LT5yZWdfZGVzYyk7Cj4gPgo+ID4gLSAgICAgcmV0dXJuIDA7Cj4gPiArICAgICB2YWwgPSByZWFk X3Nhbml0aXNlZF9mdHJfcmVnKGlkKTsKPiA+ICsgICAgIC8qIExpbWl0IGRlYnVnIHRvIEFSTXY4 LjAgKi8KPiA+ICsgICAgIHZhbCAmPSB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VM MV9EZWJ1Z1Zlcik7Cj4gPiArICAgICB2YWwgfD0gRklFTERfUFJFUChBUk02NF9GRUFUVVJFX01B U0soSURfQUE2NERGUjBfRUwxX0RlYnVnVmVyKSwgNik7Cj4gPiArICAgICAvKgo+ID4gKyAgICAg ICogSW5pdGlhbGlzZSB0aGUgZGVmYXVsdCBQTVV2ZXIgYmVmb3JlIHRoZXJlIGlzIGEgY2hhbmNl IHRvCj4gPiArICAgICAgKiBjcmVhdGUgYW4gYWN0dWFsIFBNVS4KPiA+ICsgICAgICAqLwo+ID4g KyAgICAgdmFsICY9IH5BUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwxX1BNVVZlcik7 Cj4gPiArICAgICB2YWwgfD0gRklFTERfUFJFUChBUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERG UjBfRUwxX1BNVVZlciksCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBrdm1fYXJtX3BtdV9n ZXRfcG11dmVyX2xpbWl0KCkpOwo+ID4gKyAgICAgLyogSGlkZSBTUEUgZnJvbSBndWVzdHMgKi8K PiA+ICsgICAgIHZhbCAmPSB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VMMV9QTVNW ZXIpOwo+ID4gKwo+ID4gKyAgICAgaWRyLT5rdm1fc3lzX3ZhbCA9IHZhbDsKPiA+ICB9Cj4gPgo+ ID4gIHN0YXRpYyBpbnQgc2V0X2lkX2FhNjRkZnIwX2VsMShzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUs Cj4gPiBAQCAtMjM4LDYgKzM2NCw3IEBAIHN0YXRpYyBpbnQgc2V0X2lkX2FhNjRkZnIwX2VsMShz dHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiAgewo+ID4gICAgICAgdTggcG11dmVyLCBob3N0X3Bt dXZlcjsKPiA+ICAgICAgIGJvb2wgdmFsaWRfcG11Owo+ID4gKyAgICAgaW50IHJldDsKPiA+Cj4g PiAgICAgICBob3N0X3BtdXZlciA9IGt2bV9hcm1fcG11X2dldF9wbXV2ZXJfbGltaXQoKTsKPiA+ Cj4gPiBAQCAtMjU3LDM5ICszODQsNTggQEAgc3RhdGljIGludCBzZXRfaWRfYWE2NGRmcjBfZWwx KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwKPiA+ICAgICAgIGlmIChrdm1fdmNwdV9oYXNfcG11KHZj cHUpICE9IHZhbGlkX3BtdSkKPiA+ICAgICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4gPgo+ ID4gLSAgICAgLyogV2UgY2FuIG9ubHkgZGlmZmVyIHdpdGggUE1VdmVyLCBhbmQgYW55dGhpbmcg ZWxzZSBpcyBhbiBlcnJvciAqLwo+ID4gLSAgICAgdmFsIF49IHJlYWRfaWRfcmVnKHZjcHUsIHJk KTsKPiA+IC0gICAgIHZhbCAmPSB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VMMV9Q TVVWZXIpOwo+ID4gLSAgICAgaWYgKHZhbCkKPiA+IC0gICAgICAgICAgICAgcmV0dXJuIC1FSU5W QUw7Cj4gPiAtCj4gPiAgICAgICBpZiAodmFsaWRfcG11KSB7Cj4gPiAgICAgICAgICAgICAgIG11 dGV4X2xvY2soJnZjcHUtPmt2bS0+bG9jayk7Cj4gPiAtICAgICAgICAgICAgIHZjcHUtPmt2bS0+ YXJjaC5pZF9yZWdzW0lEUkVHX0lEWChTWVNfSURfQUE2NERGUjBfRUwxKV0gJj0KPiA+IC0gICAg ICAgICAgICAgICAgICAgICB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VMMV9QTVVW ZXIpOwo+ID4gLSAgICAgICAgICAgICB2Y3B1LT5rdm0tPmFyY2guaWRfcmVnc1tJRFJFR19JRFgo U1lTX0lEX0FBNjRERlIwX0VMMSldIHw9Cj4gPiAtICAgICAgICAgICAgICAgICAgICAgRklFTERf UFJFUChBUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwxX1BNVVZlciksIHBtdXZlcik7 Cj4gPiArICAgICAgICAgICAgIHJldCA9IHNldF9pZF9yZWcodmNwdSwgcmQsIHZhbCk7Cj4gPiAr ICAgICAgICAgICAgIGlmIChyZXQpCj4gPiArICAgICAgICAgICAgICAgICAgICAgcmV0dXJuIHJl dDsKPgo+IE5leHQgc3RvcCwgRGVhZGxvY2sgQ2l0eSwgb3VyIGZpbmFsIGRlc3RpbmF0aW9uLgpX aWxsIGZpeCBpdC4KPgo+ID4KPiA+ICAgICAgICAgICAgICAgdmNwdS0+a3ZtLT5hcmNoLmlkX3Jl Z3NbSURSRUdfSURYKFNZU19JRF9ERlIwX0VMMSldICY9Cj4gPiAgICAgICAgICAgICAgICAgICAg ICAgfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9uKTsKPiA+ICAgICAgICAg ICAgICAgdmNwdS0+a3ZtLT5hcmNoLmlkX3JlZ3NbSURSRUdfSURYKFNZU19JRF9ERlIwX0VMMSld IHw9IEZJRUxEX1BSRVAoCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBBUk02NF9G RUFUVVJFX01BU0soSURfREZSMF9FTDFfUGVyZk1vbiksIHBtdXZlcl90b19wZXJmbW9uKHBtdXZl cikpOwo+ID4gICAgICAgICAgICAgICBtdXRleF91bmxvY2soJnZjcHUtPmt2bS0+bG9jayk7Cj4g PiAtICAgICB9IGVsc2UgaWYgKHBtdXZlciA9PSBJRF9BQTY0REZSMF9FTDFfUE1VVmVyX0lNUF9E RUYpIHsKPiA+IC0gICAgICAgICAgICAgc2V0X2JpdChLVk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lN UF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZsYWdzKTsKPiA+ICAgICAgIH0gZWxzZSB7Cj4g PiAtICAgICAgICAgICAgIGNsZWFyX2JpdChLVk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZf UE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZsYWdzKTsKPiA+ICsgICAgICAgICAgICAgLyogV2UgY2Fu IG9ubHkgZGlmZmVyIHdpdGggUE1VdmVyLCBhbmQgYW55dGhpbmcgZWxzZSBpcyBhbiBlcnJvciAq Lwo+ID4gKyAgICAgICAgICAgICB2YWwgXj0gcmVhZF9pZF9yZWcodmNwdSwgcmQpOwo+ID4gKyAg ICAgICAgICAgICB2YWwgJj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0REZSMF9FTDFfUE1V VmVyKTsKPiA+ICsgICAgICAgICAgICAgaWYgKHZhbCkKPiA+ICsgICAgICAgICAgICAgICAgICAg ICByZXR1cm4gLUVJTlZBTDsKPgo+IEkgZmluZCBpdCB2ZXJ5IG9kZCB0aGF0IHlvdSBhZGQgYWxs IHRoaXMgaW5mcmFzdHJ1Y3R1cmUgdG8gY2hlY2sgZm9yCj4gd3JpdGFibGUgZmllbGRzLCBhbmQg eWV0IGhhdmUgdG8ga2VlcCB0aGlzIGNvbXBhcmlzb24uIEl0IG1ha2VzIG1lCj4gdGhpbmcgdGhh dCB0aGUgZGF0YSBzdHJ1Y3R1cmVzIGFyZSBub3QgbmVjZXNzYXJpbHkgdGhlIHJpZ2h0IG9uZXMu ClRoaXMgY29tcGFyaXNvbiBpcyBzdGlsbCBoZXJlIGJlY2F1c2UgZm9yIHRoaXMgcGF0Y2gsIHdl IGRvbid0IGFsbG93CnRoZSB3cml0YWJsZSBmb3IgdGhlIHdob2xlIElEIHJlZ2lzdGVyIGFuZCBp biB0aGUgcGF0aCBvZiBpbnZhbGlkIHBtdSwKdGhlIHNldF9pZF9yZWcoKSAoVGhpcyBmdW5jdGlv biB3aWxsIGRvIGFsbCB0aGUgY2hlY2tzKSBpcyBub3QgY2FsbGVkLgpUaGlzIGNvbXBhcmlzb24g Y2FuIGJlIHJlbW92ZWQgYXMgbG9uZyBhcyB0aGUgd2hvbGUgSUQgcmVnIGlzIGVuYWJsZWQKd3Jp dGFibGUuCj4KPiA+ICsKPiA+ICsgICAgICAgICAgICAgaWYgKHBtdXZlciA9PSBJRF9BQTY0REZS MF9FTDFfUE1VVmVyX0lNUF9ERUYpCj4gPiArICAgICAgICAgICAgICAgICAgICAgc2V0X2JpdChL Vk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZsYWdz KTsKPiA+ICsgICAgICAgICAgICAgZWxzZQo+ID4gKyAgICAgICAgICAgICAgICAgICAgIGNsZWFy X2JpdChLVk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNo LmZsYWdzKTsKPiA+ICsKPiA+ICAgICAgIH0KPiA+Cj4gPiAgICAgICByZXR1cm4gMDsKPiA+ICB9 Cj4gPgo+ID4gK3N0YXRpYyB2b2lkIGluaXRfaWRfZGZyMF9lbDEoc3RydWN0IGlkX3JlZ19kZXNj ICppZHIpCj4gPiArewo+ID4gKyAgICAgdTY0IHZhbDsKPiA+ICsgICAgIHUzMiBpZCA9IHJlZ190 b19lbmNvZGluZygmaWRyLT5yZWdfZGVzYyk7Cj4gPiArCj4gPiArICAgICB2YWwgPSByZWFkX3Nh bml0aXNlZF9mdHJfcmVnKGlkKTsKPiA+ICsgICAgIC8qCj4gPiArICAgICAgKiBJbml0aWFsaXNl IHRoZSBkZWZhdWx0IFBNVXZlciBiZWZvcmUgdGhlcmUgaXMgYSBjaGFuY2UgdG8KPiA+ICsgICAg ICAqIGNyZWF0ZSBhbiBhY3R1YWwgUE1VLgo+ID4gKyAgICAgICovCj4gPiArICAgICB2YWwgJj0g fkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9uKTsKPiA+ICsgICAgIHZhbCB8 PSBGSUVMRF9QUkVQKEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9uKSwKPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgIGt2bV9hcm1fcG11X2dldF9wbXV2ZXJfbGltaXQoKSk7 Cj4gPiArCj4gPiArICAgICBpZHItPmt2bV9zeXNfdmFsID0gdmFsOwo+ID4gK30KPiA+ICsKPiA+ ICBzdGF0aWMgaW50IHNldF9pZF9kZnIwX2VsMShzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiAg ICAgICAgICAgICAgICAgICAgICAgICAgY29uc3Qgc3RydWN0IHN5c19yZWdfZGVzYyAqcmQsCj4g PiAgICAgICAgICAgICAgICAgICAgICAgICAgdTY0IHZhbCkKPiA+ICB7Cj4gPiAgICAgICB1OCBw ZXJmbW9uLCBob3N0X3BlcmZtb247Cj4gPiAgICAgICBib29sIHZhbGlkX3BtdTsKPiA+ICsgICAg IGludCByZXQ7Cj4gPgo+ID4gICAgICAgaG9zdF9wZXJmbW9uID0gcG11dmVyX3RvX3BlcmZtb24o a3ZtX2FybV9wbXVfZ2V0X3BtdXZlcl9saW1pdCgpKTsKPiA+Cj4gPiBAQCAtMzEwLDQyICs0NTYs NDYgQEAgc3RhdGljIGludCBzZXRfaWRfZGZyMF9lbDEoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAo+ ID4gICAgICAgaWYgKGt2bV92Y3B1X2hhc19wbXUodmNwdSkgIT0gdmFsaWRfcG11KQo+ID4gICAg ICAgICAgICAgICByZXR1cm4gLUVJTlZBTDsKPiA+Cj4gPiAtICAgICAvKiBXZSBjYW4gb25seSBk aWZmZXIgd2l0aCBQZXJmTW9uLCBhbmQgYW55dGhpbmcgZWxzZSBpcyBhbiBlcnJvciAqLwo+ID4g LSAgICAgdmFsIF49IHJlYWRfaWRfcmVnKHZjcHUsIHJkKTsKPiA+IC0gICAgIHZhbCAmPSB+QVJN NjRfRkVBVFVSRV9NQVNLKElEX0RGUjBfRUwxX1BlcmZNb24pOwo+ID4gLSAgICAgaWYgKHZhbCkK PiA+IC0gICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4gPiAtCj4gPiAgICAgICBpZiAodmFs aWRfcG11KSB7Cj4gPiAgICAgICAgICAgICAgIG11dGV4X2xvY2soJnZjcHUtPmt2bS0+bG9jayk7 Cj4gPiAtICAgICAgICAgICAgIHZjcHUtPmt2bS0+YXJjaC5pZF9yZWdzW0lEUkVHX0lEWChTWVNf SURfREZSMF9FTDEpXSAmPQo+ID4gLSAgICAgICAgICAgICAgICAgICAgIH5BUk02NF9GRUFUVVJF X01BU0soSURfREZSMF9FTDFfUGVyZk1vbik7Cj4gPiAtICAgICAgICAgICAgIHZjcHUtPmt2bS0+ YXJjaC5pZF9yZWdzW0lEUkVHX0lEWChTWVNfSURfREZSMF9FTDEpXSB8PSBGSUVMRF9QUkVQKAo+ ID4gLSAgICAgICAgICAgICAgICAgICAgIEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9Q ZXJmTW9uKSwgcGVyZm1vbik7Cj4gPiArICAgICAgICAgICAgIHJldCA9IHNldF9pZF9yZWcodmNw dSwgcmQsIHZhbCk7Cj4gPiArICAgICAgICAgICAgIGlmIChyZXQpCj4gPiArICAgICAgICAgICAg ICAgICAgICAgcmV0dXJuIHJldDsKPgo+IFNhbWUgcGxheWVyLCBzaG9vdCBhZ2Fpbi4KV2lsbCBm aXggaXQuCj4KPiA+Cj4gPiAgICAgICAgICAgICAgIHZjcHUtPmt2bS0+YXJjaC5pZF9yZWdzW0lE UkVHX0lEWChTWVNfSURfQUE2NERGUjBfRUwxKV0gJj0KPiA+ICAgICAgICAgICAgICAgICAgICAg ICB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VMMV9QTVVWZXIpOwo+ID4gICAgICAg ICAgICAgICB2Y3B1LT5rdm0tPmFyY2guaWRfcmVnc1tJRFJFR19JRFgoU1lTX0lEX0FBNjRERlIw X0VMMSldIHw9IEZJRUxEX1BSRVAoCj4gPiAgICAgICAgICAgICAgICAgICAgICAgQVJNNjRfRkVB VFVSRV9NQVNLKElEX0FBNjRERlIwX0VMMV9QTVVWZXIpLCBwZXJmbW9uX3RvX3BtdXZlcihwZXJm bW9uKSk7Cj4gPiAgICAgICAgICAgICAgIG11dGV4X3VubG9jaygmdmNwdS0+a3ZtLT5sb2NrKTsK PiA+IC0gICAgIH0gZWxzZSBpZiAocGVyZm1vbiA9PSBJRF9ERlIwX0VMMV9QZXJmTW9uX0lNUERF Rikgewo+ID4gLSAgICAgICAgICAgICBzZXRfYml0KEtWTV9BUkNIX0ZMQUdfVkNQVV9IQVNfSU1Q X0RFRl9QTVUsICZ2Y3B1LT5rdm0tPmFyY2guZmxhZ3MpOwo+ID4gICAgICAgfSBlbHNlIHsKPiA+ IC0gICAgICAgICAgICAgY2xlYXJfYml0KEtWTV9BUkNIX0ZMQUdfVkNQVV9IQVNfSU1QX0RFRl9Q TVUsICZ2Y3B1LT5rdm0tPmFyY2guZmxhZ3MpOwo+ID4gKyAgICAgICAgICAgICAvKiBXZSBjYW4g b25seSBkaWZmZXIgd2l0aCBQZXJmTW9uLCBhbmQgYW55dGhpbmcgZWxzZSBpcyBhbiBlcnJvciAq Lwo+ID4gKyAgICAgICAgICAgICB2YWwgXj0gcmVhZF9pZF9yZWcodmNwdSwgcmQpOwo+ID4gKyAg ICAgICAgICAgICB2YWwgJj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9u KTsKPiA+ICsgICAgICAgICAgICAgaWYgKHZhbCkKPiA+ICsgICAgICAgICAgICAgICAgICAgICBy ZXR1cm4gLUVJTlZBTDsKPiA+ICsKPiA+ICsgICAgICAgICAgICAgaWYgKHBlcmZtb24gPT0gSURf REZSMF9FTDFfUGVyZk1vbl9JTVBERUYpCj4gPiArICAgICAgICAgICAgICAgICAgICAgc2V0X2Jp dChLVk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZs YWdzKTsKPiA+ICsgICAgICAgICAgICAgZWxzZQo+ID4gKyAgICAgICAgICAgICAgICAgICAgIGNs ZWFyX2JpdChLVk1fQVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5h cmNoLmZsYWdzKTsKPiA+ICAgICAgIH0KPgo+IFNhbWUgcmVtYXJrcy4KPgo+ID4KPiA+ICAgICAg IHJldHVybiAwOwo+ID4gIH0KPiA+Cj4gPiAgLyogc3lzX3JlZ19kZXNjIGluaXRpYWxpc2VyIGZv ciBrbm93biBjcHVmZWF0dXJlIElEIHJlZ2lzdGVycyAqLwo+ID4gKyNkZWZpbmUgU1lTX0RFU0Nf U0FOSVRJU0VEKG5hbWUpIHsgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAgU1lTX0RFU0Mo U1lTXyMjbmFtZSksICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAgLmFjY2Vz cyA9IGFjY2Vzc19pZF9yZWcsICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAgLmdl dF91c2VyID0gZ2V0X2lkX3JlZywgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAg LnNldF91c2VyID0gc2V0X2lkX3JlZywgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAg ICAgLnZpc2liaWxpdHkgPSBpZF92aXNpYmlsaXR5LCAgICAgICAgICAgICAgICAgICAgXAo+ID4g K30KPiA+ICsKPiA+ICAjZGVmaW5lIElEX1NBTklUSVNFRChuYW1lKSB7ICAgICAgICAgICAgICAg ICAgICAgICAgIFwKPiA+IC0gICAgIC5yZWdfZGVzYyA9IHsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIFwKPiA+IC0gICAgICAgICAgICAgU1lTX0RFU0MoU1lTXyMjbmFtZSksICAg ICAgICAgICAgICAgICAgIFwKPiA+IC0gICAgICAgICAgICAgLmFjY2VzcyA9IGFjY2Vzc19pZF9y ZWcsICAgICAgICAgICAgICAgIFwKPiA+IC0gICAgICAgICAgICAgLmdldF91c2VyID0gZ2V0X2lk X3JlZywgICAgICAgICAgICAgICAgIFwKPiA+IC0gICAgICAgICAgICAgLnNldF91c2VyID0gc2V0 X2lkX3JlZywgICAgICAgICAgICAgICAgIFwKPiA+IC0gICAgICAgICAgICAgLnZpc2liaWxpdHkg PSBpZF92aXNpYmlsaXR5LCAgICAgICAgICAgIFwKPiA+IC0gICAgIH0sICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgIC5yZWdfZGVzYyA9IFNZ U19ERVNDX1NBTklUSVNFRChuYW1lKSwgICAgICAgICAgIFwKPiA+ICsgICAgIC5mdHJfYml0cyA9 IHsgQVJNNjRfRlRSX0VORCwgfSwgICAgICAgICAgICAgICAgIFwKPiA+ICsgICAgIC5pbml0ID0g aW5pdF9pZF9yZWcsICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ICB9Cj4gPgo+ID4g IC8qIHN5c19yZWdfZGVzYyBpbml0aWFsaXNlciBmb3Iga25vd24gY3B1ZmVhdHVyZSBJRCByZWdp c3RlcnMgKi8KPiA+IEBAIC0zNTcsNiArNTA3LDggQEAgc3RhdGljIGludCBzZXRfaWRfZGZyMF9l bDEoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAo+ID4gICAgICAgICAgICAgICAuc2V0X3VzZXIgPSBz ZXRfaWRfcmVnLCAgICAgICAgICAgICAgICAgXAo+ID4gICAgICAgICAgICAgICAudmlzaWJpbGl0 eSA9IGFhMzJfaWRfdmlzaWJpbGl0eSwgICAgICAgXAo+ID4gICAgICAgfSwgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAgLmZ0cl9iaXRzID0g eyBBUk02NF9GVFJfRU5ELCB9LCAgICAgICAgICAgICAgICAgXAo+ID4gKyAgICAgLmluaXQgPSBp bml0X2lkX3JlZywgICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4gIH0KPiA+Cj4gPiAg LyoKPiA+IEBAIC0zNzIsNiArNTI0LDcgQEAgc3RhdGljIGludCBzZXRfaWRfZGZyMF9lbDEoc3Ry dWN0IGt2bV92Y3B1ICp2Y3B1LAo+ID4gICAgICAgICAgICAgICAuc2V0X3VzZXIgPSBzZXRfaWRf cmVnLCAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiAgICAgICAgICAgICAgIC52aXNpYmls aXR5ID0gcmF6X3Zpc2liaWxpdHkgICAgICAgICAgICAgICAgICAgIFwKPiA+ICAgICAgIH0sICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4g KyAgICAgLmZ0cl9iaXRzID0geyBBUk02NF9GVFJfRU5ELCB9LCAgICAgICAgICAgICAgICAgICAg ICAgICBcCj4gPiAgfQo+ID4KPiA+ICAvKgo+ID4gQEAgLTM4Nyw5ICs1NDAsMTAgQEAgc3RhdGlj IGludCBzZXRfaWRfZGZyMF9lbDEoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAo+ID4gICAgICAgICAg ICAgICAuc2V0X3VzZXIgPSBzZXRfaWRfcmVnLCAgICAgICAgICAgICAgICAgXAo+ID4gICAgICAg ICAgICAgICAudmlzaWJpbGl0eSA9IHJhel92aXNpYmlsaXR5LCAgICAgICAgICAgXAo+ID4gICAg ICAgfSwgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4g KyAgICAgLmZ0cl9iaXRzID0geyBBUk02NF9GVFJfRU5ELCB9LCAgICAgICAgICAgICAgICAgXAo+ ID4gIH0KPiA+Cj4gPiAtc3RhdGljIGNvbnN0IHN0cnVjdCBpZF9yZWdfZGVzYyBpZF9yZWdfZGVz Y3NbS1ZNX0FSTV9JRF9SRUdfTlVNXSA9IHsKPiA+ICtzdGF0aWMgc3RydWN0IGlkX3JlZ19kZXNj IGlkX3JlZ19kZXNjc1tLVk1fQVJNX0lEX1JFR19OVU1dID0gewo+ID4gICAgICAgLyoKPiA+ICAg ICAgICAqIElEIHJlZ3M6IGFsbCBJRF9TQU5JVElTRUQoKSBlbnRyaWVzIGhlcmUgbXVzdCBoYXZl IGNvcnJlc3BvbmRpbmcKPiA+ICAgICAgICAqIGVudHJpZXMgaW4gYXJtNjRfZnRyX3JlZ3NbXS4K PiA+IEBAIC00MDUsNiArNTU5LDExIEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3QgaWRfcmVnX2Rlc2Mg aWRfcmVnX2Rlc2NzW0tWTV9BUk1fSURfUkVHX05VTV0gPSB7Cj4gPiAgICAgICAgICAgICAgIC5n ZXRfdXNlciA9IGdldF9pZF9yZWcsCj4gPiAgICAgICAgICAgICAgIC5zZXRfdXNlciA9IHNldF9p ZF9kZnIwX2VsMSwKPiA+ICAgICAgICAgICAgICAgLnZpc2liaWxpdHkgPSBhYTMyX2lkX3Zpc2li aWxpdHksIH0sCj4gPiArICAgICAgIC5mdHJfYml0cyA9IHsKPiA+ICsgICAgICAgICAgICAgQVJN NjRfRlRSX0JJVFMoRlRSX1ZJU0lCTEUsIEZUUl9TVFJJQ1QsIEZUUl9MT1dFUl9TQUZFLAo+ID4g KyAgICAgICAgICAgICAgICAgICAgIElEX0RGUjBfRUwxX1BlcmZNb25fU0hJRlQsIElEX0RGUjBf RUwxX1BlcmZNb25fV0lEVEgsIDApLAo+ID4gKyAgICAgICAgICAgICBBUk02NF9GVFJfRU5ELCB9 LAo+ID4gKyAgICAgICAuaW5pdCA9IGluaXRfaWRfZGZyMF9lbDEsCj4gPiAgICAgICB9LAo+ID4g ICAgICAgSURfSElEREVOKElEX0FGUjBfRUwxKSwKPiA+ICAgICAgIEFBMzJfSURfU0FOSVRJU0VE KElEX01NRlIwX0VMMSksCj4gPiBAQCAtNDM5LDYgKzU5OCwxMyBAQCBzdGF0aWMgY29uc3Qgc3Ry dWN0IGlkX3JlZ19kZXNjIGlkX3JlZ19kZXNjc1tLVk1fQVJNX0lEX1JFR19OVU1dID0gewo+ID4g ICAgICAgICAgICAgICAuYWNjZXNzID0gYWNjZXNzX2lkX3JlZywKPiA+ICAgICAgICAgICAgICAg LmdldF91c2VyID0gZ2V0X2lkX3JlZywKPiA+ICAgICAgICAgICAgICAgLnNldF91c2VyID0gc2V0 X2lkX2FhNjRwZnIwX2VsMSwgfSwKPiA+ICsgICAgICAgLmZ0cl9iaXRzID0gewo+ID4gKyAgICAg ICAgICAgICBBUk02NF9GVFJfQklUUyhGVFJfVklTSUJMRSwgRlRSX1NUUklDVCwgRlRSX0xPV0VS X1NBRkUsCj4gPiArICAgICAgICAgICAgICAgICAgICAgSURfQUE2NFBGUjBfRUwxX0NTVjJfU0hJ RlQsIElEX0FBNjRQRlIwX0VMMV9DU1YyX1dJRFRILCAwKSwKPiA+ICsgICAgICAgICAgICAgQVJN NjRfRlRSX0JJVFMoRlRSX1ZJU0lCTEUsIEZUUl9TVFJJQ1QsIEZUUl9MT1dFUl9TQUZFLAo+ID4g KyAgICAgICAgICAgICAgICAgICAgIElEX0FBNjRQRlIwX0VMMV9DU1YzX1NISUZULCBJRF9BQTY0 UEZSMF9FTDFfQ1NWM19XSURUSCwgMCksCj4gPiArICAgICAgICAgICAgIEFSTTY0X0ZUUl9FTkQs IH0sCj4KPiBJdCByZWFsbHkgc3RyaWtlcyBtZSB0aGF0IHlvdSBhcmUgMTAwJSBkdXBsaWNhdGlu ZyBkYXRhIHRoYXQgaXMKPiBhbHJlYWR5IGluIGZ0cl9pZF9hYTY0cGZyMFtdLiBPbmx5IHRoYXQg dGhpcyBpcyBhIHN1YnNldCBvZiB0aGUKPiBleGlzdGluZyBkYXRhLgo+Cj4gWW91IGNvdWxkIGlu c3RlYWQgaGF2ZSB5b3VyICdpbml0KCknIGNhbGxiYWNrIHJldHVybiBhIHBhaXIgb2YgdmFsdWVz Ogo+IHRoZSBkZWZhdWx0IHZhbHVlIGJhc2VkIG9uIHRoZSBzYW5pdGlzZWQgb25lLCBhbmQgYSA2 NGJpdCBtYXNrLiBBdAo+IHRoaXMgc3RhZ2UsIHlvdSdsbCByZWFsaXNlIHRoYXQgdGhpcyBsb29r cyBhIGxvdCBsaWtlIHRoZSBmZWF0dXJlCj4gb3ZlcnJpZGUsIGFuZCB0aGF0IHlvdSBzaG91bGQg YmUgYWJsZSB0byByZXVzZSBzb21lIG9mIHRoZSBleGlzdGluZwo+IGluZnJhc3RydWN0dXJlLgpT dXJlLCB3aWxsIHRyeSB0byBpbXByb3ZlIHRoaXMgYnkgeW91ciBzdWdnZXN0aW9uLgo+Cj4gVGhh bmtzLAo+Cj4gICAgICAgICBNLgo+Cj4gLS0KPiBXaXRob3V0IGRldmlhdGlvbiBmcm9tIHRoZSBu b3JtLCBwcm9ncmVzcyBpcyBub3QgcG9zc2libGUuClRoYW5rcywKSmluZwoKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWls aW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0 cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=