* [Qemu-devel] [PATCH 0/2] target/mips: Two corrections
@ 2018-10-22 11:57 Aleksandar Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c Aleksandar Markovic
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Aleksandar Markovic @ 2018-10-22 11:57 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
This small series adds two corrections for issues reported recently.
Aleksandar Markovic (2):
target/mips: Fix the title of translate.c
target/mips: Fix decoding of ALIGN and DALIGN instructions
target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++---------
1 file changed, 33 insertions(+), 9 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c
2018-10-22 11:57 [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Aleksandar Markovic
@ 2018-10-22 11:57 ` Aleksandar Markovic
2018-10-22 12:07 ` Stefan Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
2018-10-22 23:38 ` [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Philippe Mathieu-Daudé
2 siblings, 1 reply; 6+ messages in thread
From: Aleksandar Markovic @ 2018-10-22 11:57 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 74ef160..1afb105 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1,5 +1,5 @@
/*
- * MIPS32 emulation for qemu: main translation routines.
+ * MIPS emulation for QEMU: main translation routines.
*
* Copyright (c) 2004-2005 Jocelyn Mayer
* Copyright (c) 2006 Marius Groeger (FPU operations)
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions
2018-10-22 11:57 [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Aleksandar Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c Aleksandar Markovic
@ 2018-10-22 11:57 ` Aleksandar Markovic
2018-10-22 12:10 ` Stefan Markovic
2018-10-22 23:38 ` [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Philippe Mathieu-Daudé
2 siblings, 1 reply; 6+ messages in thread
From: Aleksandar Markovic @ 2018-10-22 11:57 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 40 ++++++++++++++++++++++++++++++++--------
1 file changed, 32 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1afb105..e5db92e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -463,8 +463,10 @@ enum {
OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
OPC_SEB = (0x10 << 6) | OPC_BSHFL,
OPC_SEH = (0x18 << 6) | OPC_BSHFL,
- OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
- OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
+ OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
+ OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
+ OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
+ OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
};
@@ -474,8 +476,14 @@ enum {
enum {
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
- OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
- OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
+ OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
+ OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
+ OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
+ OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
+ OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
+ OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL,
+ OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
+ OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
};
@@ -23957,7 +23965,9 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN:
- case OPC_ALIGN_END:
+ case OPC_ALIGN_1:
+ case OPC_ALIGN_2:
+ case OPC_ALIGN_3:
gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
@@ -23983,7 +23993,13 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN:
- case OPC_DALIGN_END:
+ case OPC_DALIGN_1:
+ case OPC_DALIGN_2:
+ case OPC_DALIGN_3:
+ case OPC_DALIGN_4:
+ case OPC_DALIGN_5:
+ case OPC_DALIGN_6:
+ case OPC_DALIGN_7:
gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
@@ -24843,7 +24859,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN:
- case OPC_ALIGN_END:
+ case OPC_ALIGN_1:
+ case OPC_ALIGN_2:
+ case OPC_ALIGN_3:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -24869,7 +24887,13 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN:
- case OPC_DALIGN_END:
+ case OPC_DALIGN_1:
+ case OPC_DALIGN_2:
+ case OPC_DALIGN_3:
+ case OPC_DALIGN_4:
+ case OPC_DALIGN_5:
+ case OPC_DALIGN_6:
+ case OPC_DALIGN_7:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c
2018-10-22 11:57 ` [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c Aleksandar Markovic
@ 2018-10-22 12:07 ` Stefan Markovic
0 siblings, 0 replies; 6+ messages in thread
From: Stefan Markovic @ 2018-10-22 12:07 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, amarkovic, pjovanovic
On 22.10.18. 13:57, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Replace MIPS32 with MIPS, since the file covers all generations
> of MIPS architectures.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 74ef160..1afb105 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1,5 +1,5 @@
> /*
> - * MIPS32 emulation for qemu: main translation routines.
> + * MIPS emulation for QEMU: main translation routines.
> *
> * Copyright (c) 2004-2005 Jocelyn Mayer
> * Copyright (c) 2006 Marius Groeger (FPU operations)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions
2018-10-22 11:57 ` [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
@ 2018-10-22 12:10 ` Stefan Markovic
0 siblings, 0 replies; 6+ messages in thread
From: Stefan Markovic @ 2018-10-22 12:10 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, amarkovic, pjovanovic
On 22.10.18. 13:57, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
> allow paremeter 'bp' to occupy two and three bits, respectively.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 40 ++++++++++++++++++++++++++++++++--------
> 1 file changed, 32 insertions(+), 8 deletions(-)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 1afb105..e5db92e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -463,8 +463,10 @@ enum {
> OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
> OPC_SEB = (0x10 << 6) | OPC_BSHFL,
> OPC_SEH = (0x18 << 6) | OPC_BSHFL,
> - OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
> - OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
> + OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
> + OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
> + OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
> + OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
> OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
> };
>
> @@ -474,8 +476,14 @@ enum {
> enum {
> OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
> OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
> - OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
> - OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
> + OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
> + OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
> + OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
> + OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
> + OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
> + OPC_DALIG
>
>
> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
>
>
> N_5 = (0x0D << 6) | OPC_DBSHFL,
> + OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
> + OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
> OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
> };
>
> @@ -23957,7 +23965,9 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
> op2 = MASK_BSHFL(ctx->opcode);
> switch (op2) {
> case OPC_ALIGN:
> - case OPC_ALIGN_END:
> + case OPC_ALIGN_1:
> + case OPC_ALIGN_2:
> + case OPC_ALIGN_3:
> gen_align(ctx, 32, rd, rs, rt, sa & 3);
> break;
> case OPC_BITSWAP:
> @@ -23983,7 +23993,13 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
> op2 = MASK_DBSHFL(ctx->opcode);
> switch (op2) {
> case OPC_DALIGN:
> - case OPC_DALIGN_END:
> + case OPC_DALIGN_1:
> + case OPC_DALIGN_2:
> + case OPC_DALIGN_3:
> + case OPC_DALIGN_4:
> + case OPC_DALIGN_5:
> + case OPC_DALIGN_6:
> + case OPC_DALIGN_7:
> gen_align(ctx, 64, rd, rs, rt, sa & 7);
> break;
> case OPC_DBITSWAP:
> @@ -24843,7 +24859,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> op2 = MASK_BSHFL(ctx->opcode);
> switch (op2) {
> case OPC_ALIGN:
> - case OPC_ALIGN_END:
> + case OPC_ALIGN_1:
> + case OPC_ALIGN_2:
> + case OPC_ALIGN_3:
> case OPC_BITSWAP:
> check_insn(ctx, ISA_MIPS32R6);
> decode_opc_special3_r6(env, ctx);
> @@ -24869,7 +24887,13 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> op2 = MASK_DBSHFL(ctx->opcode);
> switch (op2) {
> case OPC_DALIGN:
> - case OPC_DALIGN_END:
> + case OPC_DALIGN_1:
> + case OPC_DALIGN_2:
> + case OPC_DALIGN_3:
> + case OPC_DALIGN_4:
> + case OPC_DALIGN_5:
> + case OPC_DALIGN_6:
> + case OPC_DALIGN_7:
> case OPC_DBITSWAP:
> check_insn(ctx, ISA_MIPS32R6);
> decode_opc_special3_r6(env, ctx);
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH 0/2] target/mips: Two corrections
2018-10-22 11:57 [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Aleksandar Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c Aleksandar Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
@ 2018-10-22 23:38 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-22 23:38 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: qemu-devel@nongnu.org Developers, Stefan Markovic,
Petar Jovanovic, Aleksandar Markovic, Aurelien Jarno
On Mon, Oct 22, 2018 at 1:59 PM Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> This small series adds two corrections for issues reported recently.
>
> Aleksandar Markovic (2):
> target/mips: Fix the title of translate.c
> target/mips: Fix decoding of ALIGN and DALIGN instructions
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-10-22 23:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2018-10-22 11:57 [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Aleksandar Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c Aleksandar Markovic
2018-10-22 12:07 ` Stefan Markovic
2018-10-22 11:57 ` [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions Aleksandar Markovic
2018-10-22 12:10 ` Stefan Markovic
2018-10-22 23:38 ` [Qemu-devel] [PATCH 0/2] target/mips: Two corrections Philippe Mathieu-Daudé
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