Le ven. 28 août 2020 16:23, Richard Henderson a écrit : > Continue eliminating the sregs array in favor of individual members. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daudé --- > target/microblaze/cpu.h | 1 + > target/microblaze/gdbstub.c | 4 ++-- > target/microblaze/helper.c | 6 +++--- > target/microblaze/op_helper.c | 8 ++++---- > target/microblaze/translate.c | 6 ++++-- > 5 files changed, 14 insertions(+), 11 deletions(-) > > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 36de61d9f9..c9035b410e 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -238,6 +238,7 @@ struct CPUMBState { > uint32_t regs[32]; > uint64_t pc; > uint64_t msr; > + uint64_t ear; > uint64_t sregs[14]; > float_status fp_status; > /* Stack protectors. Yes, it's a hw feature. */ > diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c > index e4c4936a7a..e33a613efe 100644 > --- a/target/microblaze/gdbstub.c > +++ b/target/microblaze/gdbstub.c > @@ -65,7 +65,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray > *mem_buf, int n) > val = env->msr; > break; > case GDB_EAR: > - val = env->sregs[SR_EAR]; > + val = env->ear; > break; > case GDB_ESR: > val = env->sregs[SR_ESR]; > @@ -121,7 +121,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t > *mem_buf, int n) > env->msr = tmp; > break; > case GDB_EAR: > - env->sregs[SR_EAR] = tmp; > + env->ear = tmp; > break; > case GDB_ESR: > env->sregs[SR_ESR] = tmp; > diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c > index a18314540f..afe9634781 100644 > --- a/target/microblaze/helper.c > +++ b/target/microblaze/helper.c > @@ -85,7 +85,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int > size, > qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", > mmu_idx, address); > > - env->sregs[SR_EAR] = address; > + env->ear = address; > switch (lu.err) { > case ERR_PROT: > env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16; > @@ -145,7 +145,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > qemu_log_mask(CPU_LOG_INT, > "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " > " > "esr=%" PRIx64 " iflags=%x\n", > - env->pc, env->sregs[SR_EAR], > + env->pc, env->ear, > env->sregs[SR_ESR], env->iflags); > log_cpu_state_mask(CPU_LOG_INT, cs, 0); > env->iflags &= ~(IMM_FLAG | D_FLAG); > @@ -188,7 +188,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > qemu_log_mask(CPU_LOG_INT, > "exception at pc=%" PRIx64 " ear=%" PRIx64 " " > "iflags=%x\n", > - env->pc, env->sregs[SR_EAR], env->iflags); > + env->pc, env->ear, env->iflags); > log_cpu_state_mask(CPU_LOG_INT, cs, 0); > env->iflags &= ~(IMM_FLAG | D_FLAG); > env->pc = cpu->cfg.base_vectors + 0x20; > diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c > index 3668382d36..5bacd29663 100644 > --- a/target/microblaze/op_helper.c > +++ b/target/microblaze/op_helper.c > @@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env) > qemu_log("PC=%" PRIx64 "\n", env->pc); > qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " > "debug[%x] imm=%x iflags=%x\n", > - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], > + env->msr, env->sregs[SR_ESR], env->ear, > env->debug, env->imm, env->iflags); > qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d > ie=%d\n", > env->btaken, env->btarget, > @@ -431,7 +431,7 @@ void helper_memalign(CPUMBState *env, target_ulong > addr, > "unaligned access addr=" TARGET_FMT_lx > " mask=%x, wr=%d dr=r%d\n", > addr, mask, wr, dr); > - env->sregs[SR_EAR] = addr; > + env->ear = addr; > env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \ > | (dr & 31) << 5; > if (mask == 3) { > @@ -450,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong > addr) > qemu_log_mask(CPU_LOG_INT, "Stack protector violation at " > TARGET_FMT_lx " %x %x\n", > addr, env->slr, env->shr); > - env->sregs[SR_EAR] = addr; > + env->ear = addr; > env->sregs[SR_ESR] = ESR_EC_STACKPROT; > helper_raise_exception(env, EXCP_HW_EXCP); > } > @@ -488,7 +488,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr > physaddr, vaddr addr, > return; > } > > - env->sregs[SR_EAR] = addr; > + env->ear = addr; > if (access_type == MMU_INST_FETCH) { > if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { > env->sregs[SR_ESR] = ESR_EC_INSN_BUS; > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index 9f2dcd82cd..62747b02f3 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int > flags) > qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " > "debug=%x imm=%x iflags=%x fsr=%" PRIx64 " " > "rbtr=%" PRIx64 "\n", > - env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR], > + env->msr, env->sregs[SR_ESR], env->ear, > env->debug, env->imm, env->iflags, env->sregs[SR_FSR], > env->sregs[SR_BTR]); > qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) " > @@ -1873,8 +1873,10 @@ void mb_tcg_init(void) > tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc"); > cpu_SR[SR_MSR] = > tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), > "rmsr"); > + cpu_SR[SR_EAR] = > + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), > "rear"); > > - for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { > + for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) { > cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, > offsetof(CPUMBState, sregs[i]), > special_regnames[i]); > -- > 2.25.1 > > >