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Mon, 25 Oct 2021 06:04:39 -0700 (PDT) MIME-Version: 1.0 References: <20211025063343.29494-1-nico.cheng@rock-chips.com> <20211025141454.v2.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> In-Reply-To: <20211025141454.v2.3.Ib0d964f78ba35e91a4bef91d322101768d9fcfbf@changeid> From: Philipp Tomsich Date: Mon, 25 Oct 2021 15:04:28 +0200 Message-ID: Subject: Re: [PATCH v2 3/3] rockchip: rk3568: add arch_cpu_init() To: Nico Cheng Cc: Simon Glass , Kever Yang , yamada.masahiro@socionext.com, chenjh@rock-chips.com, jason.zhu@rock-chips.com, trini@konsulko.com, Yifeng Zhao , U-Boot Mailing List Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Mon, 25 Oct 2021 at 08:34, Nico Cheng wrote: > > We configured the drive strength and security of EMMC in > arch_cpu_init(). > > Signed-off-by: Nico Cheng > --- > > Changes in v2: > We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to > secure. > Modify comments to make them more explicit. > > arch/arm/mach-rockchip/rk3568/rk3568.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c > index 973b4f9dcb..1a62052731 100644 > --- a/arch/arm/mach-rockchip/rk3568/rk3568.c > +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c > @@ -13,6 +13,14 @@ > > #define PMUGRF_BASE 0xfdc20000 > #define GRF_BASE 0xfdc60000 > +#define GRF_GPIO1B_DS_2 0x218 > +#define GRF_GPIO1B_DS_3 0x21c > +#define GRF_GPIO1C_DS_0 0x220 > +#define GRF_GPIO1C_DS_1 0x224 > +#define GRF_GPIO1C_DS_2 0x228 > +#define GRF_GPIO1C_DS_3 0x22c > +#define SGRF_BASE 0xFDD18000 > +#define SGRF_SOC_CON4 0x10 > > /* PMU_GRF_GPIO0D_IOMUX_L */ > enum { > @@ -81,5 +89,16 @@ void board_debug_uart_init(void) > > int arch_cpu_init(void) > { > +#ifdef CONFIG_SPL_BUILD > + /* Set the emmc sdmmc0 to secure */ > + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (0x3 << 11 | 0x1 << 4)); Please introduce symbolic constants (or at least a C99 'const' expressions with a suitable names) to clarify what bits[12:11] and bit[4] control? > + /* set the emmc driver strength to level 2 */ > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); > + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); > +#endif > return 0; > } > -- > 2.17.1 > > >