From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA68CC433EF for ; Fri, 10 Sep 2021 13:50:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D7E7611C9 for ; Fri, 10 Sep 2021 13:50:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2D7E7611C9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:47474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mOguu-0000XP-5V for qemu-devel@archiver.kernel.org; Fri, 10 Sep 2021 09:50:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mOgsY-0007N7-I2 for qemu-devel@nongnu.org; Fri, 10 Sep 2021 09:47:42 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:46706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mOgsK-00027R-Md for qemu-devel@nongnu.org; Fri, 10 Sep 2021 09:47:42 -0400 Received: by mail-wr1-x42e.google.com with SMTP id x6so2703368wrv.13 for ; Fri, 10 Sep 2021 06:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/SireHdATS8Pbhm9WvKkuymI9xKYWFbAOkuA1L8ruq8=; b=q+eqngHUhB+NVQqForNqsRawUtWRZm+7i78cjf8GjenWy8d2YhwWEDT2h6oYwtic8h murH/Gex0KDQhZPSGuzNBs3EYspMiWw1ZELO1t8+he0XrgvluRtrFZ4BFv1uve6awAH3 qn1SRf8jx1bvw9Hh216oEkgbBRp6MFMiEHnz2q1fLPR5XgII3/1oY7w70dbEIzNCOT4n JepzbxnN8n5/aL5qIvT/O5GB94CTkmyEuSCZXFEIZhiJZj8zRyRvro25H/KGOdj1+JUK lNpq/p/RVIf5/J0KV1ALQP362FkjUBhUEYu8zQiAYyI0PZ31Odr/P4q03anIWjFMSTDe ja9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/SireHdATS8Pbhm9WvKkuymI9xKYWFbAOkuA1L8ruq8=; b=b+zRs+cMp1P4Ag0RNegYVTUMmE23BVVw4Igj7cwjSxPdTsjwk1ubYQAwS6DWOANXD9 iM9ddQlfoDmid1SuN5A3qroefgZP4oKaEGo4wc8VYrgHUPYRGFDBxQPqaxsTybN+HNhr aysXALxh8nn0+Dcm+uNXckQRRI+6Lp+MHp4WRxTyS0GfupEwVk8VZSCd7xbLY+lBsLes DKjn4kZVlroNGyYVyiTrkUKECAIAkOvxuXMkSQ7+3fcsMczqhhkuP4fXPRUgycSEroGV 2W9wzEJd5YbfCWPa+decT9m3/DpNp5PVij5JquHLnOHotjknpkzJtVgJXlbUrr5Avq/f dbEA== X-Gm-Message-State: AOAM532Q5SFH84qpEsoBCeSgtREhC/36H1uj5MUuirqlOjSXvBp+Io0M 9Ojm+60GQ+N77/TyOj9Btl1r8SH5BhynQGsSBh0zEZXrFSej86nU X-Google-Smtp-Source: ABdhPJzx21obO5x23+IsZZmzVuxf8i/2PLpu+h+Q8hEuZp2pxYZ7UjgJYmQ1layMsjJ5r83aAl3pV2A1GzBTi/hMOLc= X-Received: by 2002:a05:6000:18c8:: with SMTP id w8mr9796631wrq.90.1631281646080; Fri, 10 Sep 2021 06:47:26 -0700 (PDT) MIME-Version: 1.0 References: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> <20210904203516.2570119-4-philipp.tomsich@vrull.eu> <3e608998-3270-cf41-66b5-32158db99de0@linaro.org> <641dcee6-0577-35e3-0b58-2acdc2b80c2d@linaro.org> In-Reply-To: <641dcee6-0577-35e3-0b58-2acdc2b80c2d@linaro.org> From: Philipp Tomsich Date: Fri, 10 Sep 2021 16:47:15 +0300 Message-ID: Subject: Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) To: Richard Henderson Content-Type: multipart/alternative; boundary="0000000000000b2c6c05cba45b12" Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philipp.tomsich@vrull.eu; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000000b2c6c05cba45b12 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, 10 Sept 2021 at 16:40, Richard Henderson < richard.henderson@linaro.org> wrote: > On 9/10/21 3:36 PM, Philipp Tomsich wrote: > > Richard, > > > > Did you have a chance to consider what to do with clzw? > > I would prefer to avoid the extra extension instructions and change the > implementation > > (and would update the commit message to provide more context), but if > you insist on > > setting 'ctx->w' I'll just have the extra extensions emitted than delay > this series further=E2=80=A6 > > I don't mind not setting ctx->w, but bear in mind that UXL is going to > automatically set > this flag when executing RV32 on RV64. That's why I have written a tcg > patch set to > eliminate unnecessary sign-extensions. > Ok, thanks! Updated patches follow, once all test workloads have run=E2=80= =A6 Just wondering regarding the UXL-comment: the clzw instruction will be an illegal encoding for RV32 (the w-form instructions are present on RV64 only), so it should never be encountered in a RV32 instruction stream. Did you mean that clz (the instruction operating on xlen-registers) would have ctx->w set for RV32 executing on RV64 ... or am I missing something fundamental? Philipp. --0000000000000b2c6c05cba45b12 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Fri, 10 Sept 2021 at 16:40,= Richard Henderson <rich= ard.henderson@linaro.org> wrote:
On 9/10/21 3:36 PM, Philipp Tomsich wrote:
> Richard,
>
> Did you have a chance to consider what to do with clzw?
> I would prefer to avoid the extra extension instructions and change th= e implementation
> (and would update the commit message to provide more context), but if = you insist on
> setting 'ctx->w' I'll just have the extra extensions em= itted than delay this series further=E2=80=A6

I don't mind not setting ctx->w, but bear in mind that UXL is going = to automatically set
this flag when executing RV32 on RV64.=C2=A0 That's why I have written = a tcg patch set to
eliminate unnecessary sign-extensions.

Ok, t= hanks!=C2=A0 Updated patches follow, once all test workloads have run=E2=80= =A6

Ju= st wondering regarding the UXL-comment: the clzw=C2=A0instruction will be a= n illegal encoding for RV32 (the w-form instructions are present on RV64 on= ly), so it should never be encountered in a RV32 instruction stream.=C2=A0 = Did you mean that clz (the instruction operating on xlen-registers) would h= ave ctx->w set for RV32 executing on RV64 ... or am I missing something = fundamental?

Philipp.

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