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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, 13 Apr 2022 at 05:03, Heiko Stuebner wrote: > > Svpbmt (the S should be capitalized) is the > "Supervisor-mode: page-based memory types" extension > that specifies attributes for cacheability, idempotency > and ordering. > > The relevant settings are done in special bits in PTEs: > > Here is the svpbmt PTE format: > | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > N MT RSW D A G U X W R V > ^ > > Of the Reserved bits [63:54] in a leaf PTE, the high bit is already > allocated (as the N bit), so bits [62:61] are used as the MT (aka > MemType) field. This field specifies one of three memory types that > are close equivalents (or equivalent in effect) to the three main x86 > and ARMv8 memory types - as shown in the following table. > > RISC-V > Encoding & > MemType RISC-V Description > ---------- ------------------------------------------------ > 00 - PMA Normal Cacheable, No change to implied PMA memory type > 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > 11 - Rsvd Reserved for future standard use > > As the extension will not be present on all implementations, > implement a method to handle cpufeatures via alternatives > to not incur runtime penalties on cpu variants not supporting > specific extensions and patch relevant code parts at runtime. > > Co-developed-by: Wei Fu > Signed-off-by: Wei Fu > Co-developed-by: Liu Shaohua > Signed-off-by: Liu Shaohua > Co-developed-by: Guo Ren > Signed-off-by: Guo Ren > [moved to use the alternatives mechanism] > Signed-off-by: Heiko Stuebner > Cc: Christoph Hellwig > Cc: Arnd Bergmann > Cc: Drew Fustini > Cc: Wei Fu > Cc: Wei Wu > Cc: Chen-Yu Tsai > Cc: Maxime Ripard > Cc: Daniel Lustig > Cc: Greg Favor > Cc: Andrea Mondelli > Cc: Jonathan Behrens > Cc: Xinhaoqu (Freddie) > Cc: Bill Huffman > Cc: Nick Kossifidis > Cc: Allen Baum > Cc: Josh Scheid > Cc: Richard Trauben Reviewed-by: Philipp Tomsich _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77636C433EF for ; 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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 13 Apr 2022 at 05:03, Heiko Stuebner wrote: > > Svpbmt (the S should be capitalized) is the > "Supervisor-mode: page-based memory types" extension > that specifies attributes for cacheability, idempotency > and ordering. > > The relevant settings are done in special bits in PTEs: > > Here is the svpbmt PTE format: > | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > N MT RSW D A G U X W R V > ^ > > Of the Reserved bits [63:54] in a leaf PTE, the high bit is already > allocated (as the N bit), so bits [62:61] are used as the MT (aka > MemType) field. This field specifies one of three memory types that > are close equivalents (or equivalent in effect) to the three main x86 > and ARMv8 memory types - as shown in the following table. > > RISC-V > Encoding & > MemType RISC-V Description > ---------- ------------------------------------------------ > 00 - PMA Normal Cacheable, No change to implied PMA memory type > 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > 11 - Rsvd Reserved for future standard use > > As the extension will not be present on all implementations, > implement a method to handle cpufeatures via alternatives > to not incur runtime penalties on cpu variants not supporting > specific extensions and patch relevant code parts at runtime. > > Co-developed-by: Wei Fu > Signed-off-by: Wei Fu > Co-developed-by: Liu Shaohua > Signed-off-by: Liu Shaohua > Co-developed-by: Guo Ren > Signed-off-by: Guo Ren > [moved to use the alternatives mechanism] > Signed-off-by: Heiko Stuebner > Cc: Christoph Hellwig > Cc: Arnd Bergmann > Cc: Drew Fustini > Cc: Wei Fu > Cc: Wei Wu > Cc: Chen-Yu Tsai > Cc: Maxime Ripard > Cc: Daniel Lustig > Cc: Greg Favor > Cc: Andrea Mondelli > Cc: Jonathan Behrens > Cc: Xinhaoqu (Freddie) > Cc: Bill Huffman > Cc: Nick Kossifidis > Cc: Allen Baum > Cc: Josh Scheid > Cc: Richard Trauben Reviewed-by: Philipp Tomsich