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Tue, 12 Oct 2021 22:11:04 -0700 (PDT) MIME-Version: 1.0 References: <20210916181510.963449-1-oupton@google.com> <20210916181510.963449-6-oupton@google.com> In-Reply-To: <20210916181510.963449-6-oupton@google.com> From: Reiji Watanabe Date: Tue, 12 Oct 2021 22:10:48 -0700 Message-ID: Subject: Re: [PATCH v8 5/8] arm64: cpufeature: Enumerate support for FEAT_ECV >= 0x2 To: Oliver Upton Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Catalin Marinas , Will Deacon , Marc Zyngier , Peter Shier , Sean Christopherson , David Matlack , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, Jim Mattson Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Sep 16, 2021 at 11:15 AM Oliver Upton wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b268082d67ed..3fa6b091384d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -849,6 +849,7 @@ > #define ID_AA64MMFR0_ASID_8 0x0 > #define ID_AA64MMFR0_ASID_16 0x2 > > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..2f5042bb107c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2328,6 +2328,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_HAS_ECV2, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..f73a30d5fb1c 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -18,6 +18,7 @@ HAS_CRC32 > HAS_DCPODP > HAS_DCPOP > HAS_E0PD > +HAS_ECV2 > HAS_EPAN > HAS_GENERIC_AUTH > HAS_GENERIC_AUTH_ARCH > -- Reviewed-by: Reiji Watanabe Personally, I would prefer a more descriptive name (e.g. ECV_PHYS) rather than ECV2 though. Thanks, Reiji From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8825C433F5 for ; Wed, 13 Oct 2021 05:11:09 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 4ABCE60FDA for ; Wed, 13 Oct 2021 05:11:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4ABCE60FDA Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B11794B0F7; Wed, 13 Oct 2021 01:11:08 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); 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Tue, 12 Oct 2021 22:11:04 -0700 (PDT) MIME-Version: 1.0 References: <20210916181510.963449-1-oupton@google.com> <20210916181510.963449-6-oupton@google.com> In-Reply-To: <20210916181510.963449-6-oupton@google.com> From: Reiji Watanabe Date: Tue, 12 Oct 2021 22:10:48 -0700 Message-ID: Subject: Re: [PATCH v8 5/8] arm64: cpufeature: Enumerate support for FEAT_ECV >= 0x2 To: Oliver Upton Cc: kvm@vger.kernel.org, Catalin Marinas , Peter Shier , Marc Zyngier , David Matlack , Paolo Bonzini , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Jim Mattson X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Sep 16, 2021 at 11:15 AM Oliver Upton wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b268082d67ed..3fa6b091384d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -849,6 +849,7 @@ > #define ID_AA64MMFR0_ASID_8 0x0 > #define ID_AA64MMFR0_ASID_16 0x2 > > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..2f5042bb107c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2328,6 +2328,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_HAS_ECV2, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..f73a30d5fb1c 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -18,6 +18,7 @@ HAS_CRC32 > HAS_DCPODP > HAS_DCPOP > HAS_E0PD > +HAS_ECV2 > HAS_EPAN > HAS_GENERIC_AUTH > HAS_GENERIC_AUTH_ARCH > -- Reviewed-by: Reiji Watanabe Personally, I would prefer a more descriptive name (e.g. ECV_PHYS) rather than ECV2 though. Thanks, Reiji _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA8EC433EF for ; Wed, 13 Oct 2021 05:13:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1387F60E8B for ; Wed, 13 Oct 2021 05:13:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1387F60E8B Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; 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Tue, 12 Oct 2021 22:11:04 -0700 (PDT) MIME-Version: 1.0 References: <20210916181510.963449-1-oupton@google.com> <20210916181510.963449-6-oupton@google.com> In-Reply-To: <20210916181510.963449-6-oupton@google.com> From: Reiji Watanabe Date: Tue, 12 Oct 2021 22:10:48 -0700 Message-ID: Subject: Re: [PATCH v8 5/8] arm64: cpufeature: Enumerate support for FEAT_ECV >= 0x2 To: Oliver Upton Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Catalin Marinas , Will Deacon , Marc Zyngier , Peter Shier , Sean Christopherson , David Matlack , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, Jim Mattson X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_221113_484014_E6F897C0 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 16, 2021 at 11:15 AM Oliver Upton wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV>=0x2). > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 12 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b268082d67ed..3fa6b091384d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -849,6 +849,7 @@ > #define ID_AA64MMFR0_ASID_8 0x0 > #define ID_AA64MMFR0_ASID_16 0x2 > > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 > #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..2f5042bb107c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2328,6 +2328,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_HAS_ECV2, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..f73a30d5fb1c 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -18,6 +18,7 @@ HAS_CRC32 > HAS_DCPODP > HAS_DCPOP > HAS_E0PD > +HAS_ECV2 > HAS_EPAN > HAS_GENERIC_AUTH > HAS_GENERIC_AUTH_ARCH > -- Reviewed-by: Reiji Watanabe Personally, I would prefer a more descriptive name (e.g. ECV_PHYS) rather than ECV2 though. Thanks, Reiji _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel