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Mon, 13 Mar 2023 22:14:29 -0700 (PDT) MIME-Version: 1.0 References: <20230228062246.1222387-1-jingzhangos@google.com> <20230228062246.1222387-5-jingzhangos@google.com> In-Reply-To: From: Reiji Watanabe Date: Mon, 13 Mar 2023 22:14:13 -0700 Message-ID: Subject: Re: [PATCH v3 4/6] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer To: Jing Zhang Cc: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Ricardo Koller , Raghavendra Rao Ananta Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Mar 13, 2023 at 9:37=E2=80=AFPM Jing Zhang = wrote: > > Hi Reiji, > > On Sun, Mar 12, 2023 at 9:13=E2=80=AFPM Reiji Watanabe wrote: > > > > Hi Jing, > > > > On Thu, Mar 9, 2023 at 6:38=E2=80=AFPM Jing Zhang wrote: > > > > > > Hi Reiji, > > > > > > On Wed, Mar 8, 2023 at 8:42 AM Reiji Watanabe wro= te: > > > > > > > > Hi Jing, > > > > > > > > On Mon, Feb 27, 2023 at 10:23=E2=80=AFPM Jing Zhang wrote: > > > > > > > > > > With per guest ID registers, PMUver settings from userspace > > > > > can be stored in its corresponding ID register. > > > > > > > > > > No functional change intended. > > > > > > > > > > Signed-off-by: Jing Zhang > > > > > --- > > > > > arch/arm64/include/asm/kvm_host.h | 11 ++++--- > > > > > arch/arm64/kvm/arm.c | 6 ---- > > > > > arch/arm64/kvm/id_regs.c | 52 ++++++++++++++++++++++++-= ------ > > > > > include/kvm/arm_pmu.h | 6 ++-- > > > > > 4 files changed, 51 insertions(+), 24 deletions(-) > > > > > > > > > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/inclu= de/asm/kvm_host.h > > > > > index f64347eb77c2..effb61a9a855 100644 > > > > > --- a/arch/arm64/include/asm/kvm_host.h > > > > > +++ b/arch/arm64/include/asm/kvm_host.h > > > > > @@ -218,6 +218,12 @@ struct kvm_arch { > > > > > #define KVM_ARCH_FLAG_EL1_32BIT 4 > > > > > /* PSCI SYSTEM_SUSPEND enabled for the guest */ > > > > > #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5 > > > > > + /* > > > > > + * AA64DFR0_EL1.PMUver was set as ID_AA64DFR0_EL1_PMUVer_= IMP_DEF > > > > > + * or DFR0_EL1.PerfMon was set as ID_DFR0_EL1_PerfMon_IMP= DEF from > > > > > + * userspace for VCPUs without PMU. > > > > > + */ > > > > > +#define KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU 6 > > > > > > > > > > unsigned long flags; > > > > > > > > > > @@ -230,11 +236,6 @@ struct kvm_arch { > > > > > > > > > > cpumask_var_t supported_cpus; > > > > > > > > > > - struct { > > > > > - u8 imp:4; > > > > > - u8 unimp:4; > > > > > - } dfr0_pmuver; > > > > > - > > > > > /* Hypercall features firmware registers' descriptor */ > > > > > struct kvm_smccc_features smccc_feat; > > > > > > > > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > > > > index c78d68d011cb..fb2de2cb98cb 100644 > > > > > --- a/arch/arm64/kvm/arm.c > > > > > +++ b/arch/arm64/kvm/arm.c > > > > > @@ -138,12 +138,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsign= ed long type) > > > > > kvm_arm_set_default_id_regs(kvm); > > > > > kvm_arm_init_hypercalls(kvm); > > > > > > > > > > - /* > > > > > - * Initialise the default PMUver before there is a chance= to > > > > > - * create an actual PMU. > > > > > - */ > > > > > - kvm->arch.dfr0_pmuver.imp =3D kvm_arm_pmu_get_pmuver_limi= t(); > > > > > - > > > > > return 0; > > > > > > > > > > err_free_cpumask: > > > > > diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c > > > > > index 36859e4caf02..21ec8fc10d79 100644 > > > > > --- a/arch/arm64/kvm/id_regs.c > > > > > +++ b/arch/arm64/kvm/id_regs.c > > > > > @@ -21,9 +21,12 @@ > > > > > static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu) > > > > > { > > > > > if (kvm_vcpu_has_pmu(vcpu)) > > > > > - return vcpu->kvm->arch.dfr0_pmuver.imp; > > > > > - > > > > > - return vcpu->kvm->arch.dfr0_pmuver.unimp; > > > > > + return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_E= L1_PMUVer), > > > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_= EL1)); > > > > > + else if (test_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vc= pu->kvm->arch.flags)) > > > > > + return ID_AA64DFR0_EL1_PMUVer_IMP_DEF; > > > > > + else > > > > > + return 0; > > > > > } > > > > > > > > > > static u8 perfmon_to_pmuver(u8 perfmon) > > > > > @@ -256,10 +259,19 @@ static int set_id_aa64dfr0_el1(struct kvm_v= cpu *vcpu, > > > > > if (val) > > > > > return -EINVAL; > > > > > > > > > > - if (valid_pmu) > > > > > - vcpu->kvm->arch.dfr0_pmuver.imp =3D pmuver; > > > > > - else > > > > > - vcpu->kvm->arch.dfr0_pmuver.unimp =3D pmuver; > > > > > + if (valid_pmu) { > > > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &=3D ~ARM64= _FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |=3D > > > > > + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0= _EL1_PMUVer), pmuver); > > > > > + > > > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &=3D ~ARM64_FEA= TURE_MASK(ID_DFR0_EL1_PerfMon); > > > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |=3D > > > > > + FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1= _PerfMon), pmuver); > > > > > > > > The pmuver must be converted to perfmon for ID_DFR0_EL1. > > > Yes, wil fix it. > > > > > > > > Also, I think those registers should be updated atomically, althoug= h PMUver > > > > specified by userspace will be normally the same for all vCPUs with > > > > PMUv3 configured (I have the same comment for set_id_dfr0_el1()). > > > > > > > I think there is no race condition here. No corrupted data would be > > > set in the field, right? > > > > If userspace tries to set inconsistent values of PMUver/Perfmon > > for vCPUs with vPMU configured at the same time, PMUver and Perfmon > > won't be consistent even with this KVM code. > > It won't be sane userspace though :) > > > I am still not convinced. I don't believe a VM would set AArch64 and > AArch32 ID registers at the same time. Difference threads will set (restore) those registers for different vCPUs in parallel, although those data are shared per VM. (e.g. kvm_arm_set_fw_reg_bmap() addresses the similar case) > Anyway, let's see if there are > any ideas from others before adding the lockings. > > > > > > > > > + } else if (pmuver =3D=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) = { > > > > > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu= ->kvm->arch.flags); > > > > > + } else { > > > > > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vc= pu->kvm->arch.flags); > > > > > + } > > > > > > > > > > return 0; > > > > > } > > > > > @@ -296,10 +308,19 @@ static int set_id_dfr0_el1(struct kvm_vcpu = *vcpu, > > > > > if (val) > > > > > return -EINVAL; > > > > > > > > > > - if (valid_pmu) > > > > > - vcpu->kvm->arch.dfr0_pmuver.imp =3D perfmon_to_pm= uver(perfmon); > > > > > - else > > > > > - vcpu->kvm->arch.dfr0_pmuver.unimp =3D perfmon_to_= pmuver(perfmon); > > > > > + if (valid_pmu) { > > > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) &=3D ~ARM64_FEA= TURE_MASK(ID_DFR0_EL1_PerfMon); > > > > > + IDREG(vcpu->kvm, SYS_ID_DFR0_EL1) |=3D FIELD_PREP= ( > > > > > + ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), = perfmon_to_pmuver(perfmon)); > > > > > > > > The perfmon value should be set for ID_DFR0_EL1 (not pmuver). > > > > > > > Sure, will fix it. > > > > > + > > > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) &=3D ~ARM64= _FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); > > > > > + IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1) |=3D FIELD_= PREP( > > > > > + ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer= ), perfmon_to_pmuver(perfmon)); > > > > > + } else if (perfmon =3D=3D ID_DFR0_EL1_PerfMon_IMPDEF) { > > > > > + set_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vcpu= ->kvm->arch.flags); > > > > > + } else { > > > > > + clear_bit(KVM_ARCH_FLAG_VCPU_HAS_IMP_DEF_PMU, &vc= pu->kvm->arch.flags); > > > > > + } > > > > > > > > > > return 0; > > > > > } > > > > > @@ -543,4 +564,13 @@ void kvm_arm_set_default_id_regs(struct kvm = *kvm) > > > > > } > > > > > > > > > > IDREG(kvm, SYS_ID_AA64PFR0_EL1) =3D val; > > > > > + > > > > > + /* > > > > > + * Initialise the default PMUver before there is a chance= to > > > > > + * create an actual PMU. > > > > > + */ > > > > > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) &=3D ~ARM64_FEATURE_MASK(= ID_AA64DFR0_EL1_PMUVer); > > > > > + IDREG(kvm, SYS_ID_AA64DFR0_EL1) |=3D > > > > > + FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMU= Ver), > > > > > + kvm_arm_pmu_get_pmuver_limit()); > > > > > } > > > > > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > > > > > index 628775334d5e..eef67b7d9751 100644 > > > > > --- a/include/kvm/arm_pmu.h > > > > > +++ b/include/kvm/arm_pmu.h > > > > > @@ -92,8 +92,10 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu= *vcpu); > > > > > /* > > > > > * Evaluates as true when emulating PMUv3p5, and false otherwise= . > > > > > */ > > > > > -#define kvm_pmu_is_3p5(vcpu) = \ > > > > > - (vcpu->kvm->arch.dfr0_pmuver.imp >=3D ID_AA64DFR0_EL1_PMU= Ver_V3P5) > > > > > +#define kvm_pmu_is_3p5(vcpu) = \ > > > > > + (kvm_vcpu_has_pmu(vcpu) && = \ > > > > > > > > What is the reason for adding this kvm_vcpu_has_pmu() checking ? > > > > I don't think this patch's changes necessitated this. > > > For the same VM, is it possible that some VCPUs would have PMU, but > > > some may not have? > > > That's why the kvm_vcpu_has_pmu is added here. > > > > Yes, it's possible. But, it doesn't appear that this patch or any > > patches in the series adds a code that newly uses the macro. > > I believe this macro is always used for the vCPUs with vPMU > > configured currently. > > Did you find a case where this is used for vCPUs with no vPMU ? > > > > If this change tries to address an existing issue, I think it would > > be nicer to fix this in a separate patch. Or it would be helpful > > if you could add an explanation in the commit log at least. > I don't think we should assume the potential users for the macro. Only > adding kvm_vcpu_has_pmu() in the macro can have the same semantics as > the original macro. > The original macro would return false if it is used by a vCPU without > vPMU. I think we should keep it as the same. The original macro always uses dfr0_pmuver.imp, which is the PMU version for vCPUs with PMU configured. So, if the macro is used for vCPUs with no PMU configured, it might return true (it depends on the value of dfr0_pmuver.imp). Or am I missing something ?? Thank you, Reiji From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF609C6FD1F for ; Tue, 14 Mar 2023 05:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eP3Z2x4kMhc2DHhVG3+lDzEYlzjZ1efQB/dtKY+Knnw=; b=KcbW2dnlh+3lzv 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Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Ricardo Koller , Raghavendra Rao Ananta X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230313_221437_907103_87D27BEA X-CRM114-Status: GOOD ( 56.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCBNYXIgMTMsIDIwMjMgYXQgOTozN+KAr1BNIEppbmcgWmhhbmcgPGppbmd6aGFuZ29z QGdvb2dsZS5jb20+IHdyb3RlOgo+Cj4gSGkgUmVpamksCj4KPiBPbiBTdW4sIE1hciAxMiwgMjAy MyBhdCA5OjEz4oCvUE0gUmVpamkgV2F0YW5hYmUgPHJlaWppd0Bnb29nbGUuY29tPiB3cm90ZToK PiA+Cj4gPiBIaSBKaW5nLAo+ID4KPiA+IE9uIFRodSwgTWFyIDksIDIwMjMgYXQgNjozOOKAr1BN IEppbmcgWmhhbmcgPGppbmd6aGFuZ29zQGdvb2dsZS5jb20+IHdyb3RlOgo+ID4gPgo+ID4gPiBI aSBSZWlqaSwKPiA+ID4KPiA+ID4gT24gV2VkLCBNYXIgOCwgMjAyMyBhdCA4OjQyIEFNIFJlaWpp IFdhdGFuYWJlIDxyZWlqaXdAZ29vZ2xlLmNvbT4gd3JvdGU6Cj4gPiA+ID4KPiA+ID4gPiBIaSBK aW5nLAo+ID4gPiA+Cj4gPiA+ID4gT24gTW9uLCBGZWIgMjcsIDIwMjMgYXQgMTA6MjPigK9QTSBK aW5nIFpoYW5nIDxqaW5nemhhbmdvc0Bnb29nbGUuY29tPiB3cm90ZToKPiA+ID4gPiA+Cj4gPiA+ ID4gPiBXaXRoIHBlciBndWVzdCBJRCByZWdpc3RlcnMsIFBNVXZlciBzZXR0aW5ncyBmcm9tIHVz ZXJzcGFjZQo+ID4gPiA+ID4gY2FuIGJlIHN0b3JlZCBpbiBpdHMgY29ycmVzcG9uZGluZyBJRCBy ZWdpc3Rlci4KPiA+ID4gPiA+Cj4gPiA+ID4gPiBObyBmdW5jdGlvbmFsIGNoYW5nZSBpbnRlbmRl ZC4KPiA+ID4gPiA+Cj4gPiA+ID4gPiBTaWduZWQtb2ZmLWJ5OiBKaW5nIFpoYW5nIDxqaW5nemhh bmdvc0Bnb29nbGUuY29tPgo+ID4gPiA+ID4gLS0tCj4gPiA+ID4gPiAgYXJjaC9hcm02NC9pbmNs dWRlL2FzbS9rdm1faG9zdC5oIHwgMTEgKysrKy0tLQo+ID4gPiA+ID4gIGFyY2gvYXJtNjQva3Zt L2FybS5jICAgICAgICAgICAgICB8ICA2IC0tLS0KPiA+ID4gPiA+ICBhcmNoL2FybTY0L2t2bS9p ZF9yZWdzLmMgICAgICAgICAgfCA1MiArKysrKysrKysrKysrKysrKysrKysrKystLS0tLS0tCj4g PiA+ID4gPiAgaW5jbHVkZS9rdm0vYXJtX3BtdS5oICAgICAgICAgICAgIHwgIDYgKystLQo+ID4g PiA+ID4gIDQgZmlsZXMgY2hhbmdlZCwgNTEgaW5zZXJ0aW9ucygrKSwgMjQgZGVsZXRpb25zKC0p Cj4gPiA+ID4gPgo+ID4gPiA+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20v a3ZtX2hvc3QuaCBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaAo+ID4gPiA+ID4g aW5kZXggZjY0MzQ3ZWI3N2MyLi5lZmZiNjFhOWE4NTUgMTAwNjQ0Cj4gPiA+ID4gPiAtLS0gYS9h cmNoL2FybTY0L2luY2x1ZGUvYXNtL2t2bV9ob3N0LmgKPiA+ID4gPiA+ICsrKyBiL2FyY2gvYXJt NjQvaW5jbHVkZS9hc20va3ZtX2hvc3QuaAo+ID4gPiA+ID4gQEAgLTIxOCw2ICsyMTgsMTIgQEAg c3RydWN0IGt2bV9hcmNoIHsKPiA+ID4gPiA+ICAjZGVmaW5lIEtWTV9BUkNIX0ZMQUdfRUwxXzMy QklUICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICA0Cj4gPiA+ID4gPiAgICAgICAgIC8q IFBTQ0kgU1lTVEVNX1NVU1BFTkQgZW5hYmxlZCBmb3IgdGhlIGd1ZXN0ICovCj4gPiA+ID4gPiAg I2RlZmluZSBLVk1fQVJDSF9GTEFHX1NZU1RFTV9TVVNQRU5EX0VOQUJMRUQgICAgICAgICAgIDUK PiA+ID4gPiA+ICsgICAgICAgLyoKPiA+ID4gPiA+ICsgICAgICAgICogQUE2NERGUjBfRUwxLlBN VXZlciB3YXMgc2V0IGFzIElEX0FBNjRERlIwX0VMMV9QTVVWZXJfSU1QX0RFRgo+ID4gPiA+ID4g KyAgICAgICAgKiBvciBERlIwX0VMMS5QZXJmTW9uIHdhcyBzZXQgYXMgSURfREZSMF9FTDFfUGVy Zk1vbl9JTVBERUYgZnJvbQo+ID4gPiA+ID4gKyAgICAgICAgKiB1c2Vyc3BhY2UgZm9yIFZDUFVz IHdpdGhvdXQgUE1VLgo+ID4gPiA+ID4gKyAgICAgICAgKi8KPiA+ID4gPiA+ICsjZGVmaW5lIEtW TV9BUkNIX0ZMQUdfVkNQVV9IQVNfSU1QX0RFRl9QTVUgICAgICAgICAgICAgNgo+ID4gPiA+ID4K PiA+ID4gPiA+ICAgICAgICAgdW5zaWduZWQgbG9uZyBmbGFnczsKPiA+ID4gPiA+Cj4gPiA+ID4g PiBAQCAtMjMwLDExICsyMzYsNiBAQCBzdHJ1Y3Qga3ZtX2FyY2ggewo+ID4gPiA+ID4KPiA+ID4g PiA+ICAgICAgICAgY3B1bWFza192YXJfdCBzdXBwb3J0ZWRfY3B1czsKPiA+ID4gPiA+Cj4gPiA+ ID4gPiAtICAgICAgIHN0cnVjdCB7Cj4gPiA+ID4gPiAtICAgICAgICAgICAgICAgdTggaW1wOjQ7 Cj4gPiA+ID4gPiAtICAgICAgICAgICAgICAgdTggdW5pbXA6NDsKPiA+ID4gPiA+IC0gICAgICAg fSBkZnIwX3BtdXZlcjsKPiA+ID4gPiA+IC0KPiA+ID4gPiA+ICAgICAgICAgLyogSHlwZXJjYWxs IGZlYXR1cmVzIGZpcm13YXJlIHJlZ2lzdGVycycgZGVzY3JpcHRvciAqLwo+ID4gPiA+ID4gICAg ICAgICBzdHJ1Y3Qga3ZtX3NtY2NjX2ZlYXR1cmVzIHNtY2NjX2ZlYXQ7Cj4gPiA+ID4gPgo+ID4g PiA+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQva3ZtL2FybS5jIGIvYXJjaC9hcm02NC9rdm0v YXJtLmMKPiA+ID4gPiA+IGluZGV4IGM3OGQ2OGQwMTFjYi4uZmIyZGUyY2I5OGNiIDEwMDY0NAo+ ID4gPiA+ID4gLS0tIGEvYXJjaC9hcm02NC9rdm0vYXJtLmMKPiA+ID4gPiA+ICsrKyBiL2FyY2gv YXJtNjQva3ZtL2FybS5jCj4gPiA+ID4gPiBAQCAtMTM4LDEyICsxMzgsNiBAQCBpbnQga3ZtX2Fy Y2hfaW5pdF92bShzdHJ1Y3Qga3ZtICprdm0sIHVuc2lnbmVkIGxvbmcgdHlwZSkKPiA+ID4gPiA+ ICAgICAgICAga3ZtX2FybV9zZXRfZGVmYXVsdF9pZF9yZWdzKGt2bSk7Cj4gPiA+ID4gPiAgICAg ICAgIGt2bV9hcm1faW5pdF9oeXBlcmNhbGxzKGt2bSk7Cj4gPiA+ID4gPgo+ID4gPiA+ID4gLSAg ICAgICAvKgo+ID4gPiA+ID4gLSAgICAgICAgKiBJbml0aWFsaXNlIHRoZSBkZWZhdWx0IFBNVXZl ciBiZWZvcmUgdGhlcmUgaXMgYSBjaGFuY2UgdG8KPiA+ID4gPiA+IC0gICAgICAgICogY3JlYXRl IGFuIGFjdHVhbCBQTVUuCj4gPiA+ID4gPiAtICAgICAgICAqLwo+ID4gPiA+ID4gLSAgICAgICBr dm0tPmFyY2guZGZyMF9wbXV2ZXIuaW1wID0ga3ZtX2FybV9wbXVfZ2V0X3BtdXZlcl9saW1pdCgp Owo+ID4gPiA+ID4gLQo+ID4gPiA+ID4gICAgICAgICByZXR1cm4gMDsKPiA+ID4gPiA+Cj4gPiA+ ID4gPiAgZXJyX2ZyZWVfY3B1bWFzazoKPiA+ID4gPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybTY0 L2t2bS9pZF9yZWdzLmMgYi9hcmNoL2FybTY0L2t2bS9pZF9yZWdzLmMKPiA+ID4gPiA+IGluZGV4 IDM2ODU5ZTRjYWYwMi4uMjFlYzhmYzEwZDc5IDEwMDY0NAo+ID4gPiA+ID4gLS0tIGEvYXJjaC9h cm02NC9rdm0vaWRfcmVncy5jCj4gPiA+ID4gPiArKysgYi9hcmNoL2FybTY0L2t2bS9pZF9yZWdz LmMKPiA+ID4gPiA+IEBAIC0yMSw5ICsyMSwxMiBAQAo+ID4gPiA+ID4gIHN0YXRpYyB1OCB2Y3B1 X3BtdXZlcihjb25zdCBzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUpCj4gPiA+ID4gPiAgewo+ID4gPiA+ ID4gICAgICAgICBpZiAoa3ZtX3ZjcHVfaGFzX3BtdSh2Y3B1KSkKPiA+ID4gPiA+IC0gICAgICAg ICAgICAgICByZXR1cm4gdmNwdS0+a3ZtLT5hcmNoLmRmcjBfcG11dmVyLmltcDsKPiA+ID4gPiA+ IC0KPiA+ID4gPiA+IC0gICAgICAgcmV0dXJuIHZjcHUtPmt2bS0+YXJjaC5kZnIwX3BtdXZlci51 bmltcDsKPiA+ID4gPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gRklFTERfR0VUKEFSTTY0X0ZF QVRVUkVfTUFTSyhJRF9BQTY0REZSMF9FTDFfUE1VVmVyKSwKPiA+ID4gPiA+ICsgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgSURSRUcodmNwdS0+a3ZtLCBTWVNfSURfQUE2NERGUjBfRUwx KSk7Cj4gPiA+ID4gPiArICAgICAgIGVsc2UgaWYgKHRlc3RfYml0KEtWTV9BUkNIX0ZMQUdfVkNQ VV9IQVNfSU1QX0RFRl9QTVUsICZ2Y3B1LT5rdm0tPmFyY2guZmxhZ3MpKQo+ID4gPiA+ID4gKyAg ICAgICAgICAgICAgIHJldHVybiBJRF9BQTY0REZSMF9FTDFfUE1VVmVyX0lNUF9ERUY7Cj4gPiA+ ID4gPiArICAgICAgIGVsc2UKPiA+ID4gPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gMDsKPiA+ ID4gPiA+ICB9Cj4gPiA+ID4gPgo+ID4gPiA+ID4gIHN0YXRpYyB1OCBwZXJmbW9uX3RvX3BtdXZl cih1OCBwZXJmbW9uKQo+ID4gPiA+ID4gQEAgLTI1NiwxMCArMjU5LDE5IEBAIHN0YXRpYyBpbnQg c2V0X2lkX2FhNjRkZnIwX2VsMShzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsCj4gPiA+ID4gPiAgICAg ICAgIGlmICh2YWwpCj4gPiA+ID4gPiAgICAgICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7Cj4g PiA+ID4gPgo+ID4gPiA+ID4gLSAgICAgICBpZiAodmFsaWRfcG11KQo+ID4gPiA+ID4gLSAgICAg ICAgICAgICAgIHZjcHUtPmt2bS0+YXJjaC5kZnIwX3BtdXZlci5pbXAgPSBwbXV2ZXI7Cj4gPiA+ ID4gPiAtICAgICAgIGVsc2UKPiA+ID4gPiA+IC0gICAgICAgICAgICAgICB2Y3B1LT5rdm0tPmFy Y2guZGZyMF9wbXV2ZXIudW5pbXAgPSBwbXV2ZXI7Cj4gPiA+ID4gPiArICAgICAgIGlmICh2YWxp ZF9wbXUpIHsKPiA+ID4gPiA+ICsgICAgICAgICAgICAgICBJRFJFRyh2Y3B1LT5rdm0sIFNZU19J RF9BQTY0REZSMF9FTDEpICY9IH5BUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwxX1BN VVZlcik7Cj4gPiA+ID4gPiArICAgICAgICAgICAgICAgSURSRUcodmNwdS0+a3ZtLCBTWVNfSURf QUE2NERGUjBfRUwxKSB8PQo+ID4gPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgRklFTERf UFJFUChBUk02NF9GRUFUVVJFX01BU0soSURfQUE2NERGUjBfRUwxX1BNVVZlciksIHBtdXZlcik7 Cj4gPiA+ID4gPiArCj4gPiA+ID4gPiArICAgICAgICAgICAgICAgSURSRUcodmNwdS0+a3ZtLCBT WVNfSURfREZSMF9FTDEpICY9IH5BUk02NF9GRUFUVVJFX01BU0soSURfREZSMF9FTDFfUGVyZk1v bik7Cj4gPiA+ID4gPiArICAgICAgICAgICAgICAgSURSRUcodmNwdS0+a3ZtLCBTWVNfSURfREZS MF9FTDEpIHw9Cj4gPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBGSUVMRF9QUkVQKEFS TTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9uKSwgcG11dmVyKTsKPiA+ID4gPgo+ ID4gPiA+IFRoZSBwbXV2ZXIgbXVzdCBiZSBjb252ZXJ0ZWQgdG8gcGVyZm1vbiBmb3IgSURfREZS MF9FTDEuCj4gPiA+IFllcywgd2lsIGZpeCBpdC4KPiA+ID4gPgo+ID4gPiA+IEFsc28sIEkgdGhp bmsgdGhvc2UgcmVnaXN0ZXJzIHNob3VsZCBiZSB1cGRhdGVkIGF0b21pY2FsbHksIGFsdGhvdWdo IFBNVXZlcgo+ID4gPiA+IHNwZWNpZmllZCBieSB1c2Vyc3BhY2Ugd2lsbCBiZSBub3JtYWxseSB0 aGUgc2FtZSBmb3IgYWxsIHZDUFVzIHdpdGgKPiA+ID4gPiBQTVV2MyBjb25maWd1cmVkIChJIGhh dmUgdGhlIHNhbWUgY29tbWVudCBmb3Igc2V0X2lkX2RmcjBfZWwxKCkpLgo+ID4gPiA+Cj4gPiA+ IEkgdGhpbmsgdGhlcmUgaXMgbm8gcmFjZSBjb25kaXRpb24gaGVyZS4gTm8gY29ycnVwdGVkIGRh dGEgd291bGQgYmUKPiA+ID4gc2V0IGluIHRoZSBmaWVsZCwgcmlnaHQ/Cj4gPgo+ID4gSWYgdXNl cnNwYWNlIHRyaWVzIHRvIHNldCBpbmNvbnNpc3RlbnQgdmFsdWVzIG9mIFBNVXZlci9QZXJmbW9u Cj4gPiBmb3IgdkNQVXMgd2l0aCB2UE1VIGNvbmZpZ3VyZWQgYXQgdGhlIHNhbWUgdGltZSwgUE1V dmVyIGFuZCBQZXJmbW9uCj4gPiB3b24ndCBiZSBjb25zaXN0ZW50IGV2ZW4gd2l0aCB0aGlzIEtW TSBjb2RlLgo+ID4gSXQgd29uJ3QgYmUgc2FuZSB1c2Vyc3BhY2UgdGhvdWdoIDopCj4gPgo+IEkg YW0gc3RpbGwgbm90IGNvbnZpbmNlZC4gSSBkb24ndCBiZWxpZXZlIGEgVk0gd291bGQgc2V0IEFB cmNoNjQgYW5kCj4gQUFyY2gzMiBJRCByZWdpc3RlcnMgYXQgdGhlIHNhbWUgdGltZS4KCkRpZmZl cmVuY2UgdGhyZWFkcyB3aWxsIHNldCAocmVzdG9yZSkgdGhvc2UgcmVnaXN0ZXJzIGZvcgpkaWZm ZXJlbnQgdkNQVXMgaW4gcGFyYWxsZWwsIGFsdGhvdWdoIHRob3NlIGRhdGEgYXJlIHNoYXJlZCBw ZXIgVk0uCihlLmcuIGt2bV9hcm1fc2V0X2Z3X3JlZ19ibWFwKCkgYWRkcmVzc2VzIHRoZSBzaW1p bGFyIGNhc2UpCgo+IEFueXdheSwgbGV0J3Mgc2VlIGlmIHRoZXJlIGFyZQo+IGFueSBpZGVhcyBm cm9tIG90aGVycyBiZWZvcmUgYWRkaW5nIHRoZSBsb2NraW5ncy4KPiA+ID4gPgo+ID4gPiA+ID4g KyAgICAgICB9IGVsc2UgaWYgKHBtdXZlciA9PSBJRF9BQTY0REZSMF9FTDFfUE1VVmVyX0lNUF9E RUYpIHsKPiA+ID4gPiA+ICsgICAgICAgICAgICAgICBzZXRfYml0KEtWTV9BUkNIX0ZMQUdfVkNQ VV9IQVNfSU1QX0RFRl9QTVUsICZ2Y3B1LT5rdm0tPmFyY2guZmxhZ3MpOwo+ID4gPiA+ID4gKyAg ICAgICB9IGVsc2Ugewo+ID4gPiA+ID4gKyAgICAgICAgICAgICAgIGNsZWFyX2JpdChLVk1fQVJD SF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZsYWdzKTsKPiA+ ID4gPiA+ICsgICAgICAgfQo+ID4gPiA+ID4KPiA+ID4gPiA+ICAgICAgICAgcmV0dXJuIDA7Cj4g PiA+ID4gPiAgfQo+ID4gPiA+ID4gQEAgLTI5NiwxMCArMzA4LDE5IEBAIHN0YXRpYyBpbnQgc2V0 X2lkX2RmcjBfZWwxKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwKPiA+ID4gPiA+ICAgICAgICAgaWYg KHZhbCkKPiA+ID4gPiA+ICAgICAgICAgICAgICAgICByZXR1cm4gLUVJTlZBTDsKPiA+ID4gPiA+ Cj4gPiA+ID4gPiAtICAgICAgIGlmICh2YWxpZF9wbXUpCj4gPiA+ID4gPiAtICAgICAgICAgICAg ICAgdmNwdS0+a3ZtLT5hcmNoLmRmcjBfcG11dmVyLmltcCA9IHBlcmZtb25fdG9fcG11dmVyKHBl cmZtb24pOwo+ID4gPiA+ID4gLSAgICAgICBlbHNlCj4gPiA+ID4gPiAtICAgICAgICAgICAgICAg dmNwdS0+a3ZtLT5hcmNoLmRmcjBfcG11dmVyLnVuaW1wID0gcGVyZm1vbl90b19wbXV2ZXIocGVy Zm1vbik7Cj4gPiA+ID4gPiArICAgICAgIGlmICh2YWxpZF9wbXUpIHsKPiA+ID4gPiA+ICsgICAg ICAgICAgICAgICBJRFJFRyh2Y3B1LT5rdm0sIFNZU19JRF9ERlIwX0VMMSkgJj0gfkFSTTY0X0ZF QVRVUkVfTUFTSyhJRF9ERlIwX0VMMV9QZXJmTW9uKTsKPiA+ID4gPiA+ICsgICAgICAgICAgICAg ICBJRFJFRyh2Y3B1LT5rdm0sIFNZU19JRF9ERlIwX0VMMSkgfD0gRklFTERfUFJFUCgKPiA+ID4g PiA+ICsgICAgICAgICAgICAgICAgICAgICAgIEFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9ERlIwX0VM MV9QZXJmTW9uKSwgcGVyZm1vbl90b19wbXV2ZXIocGVyZm1vbikpOwo+ID4gPiA+Cj4gPiA+ID4g VGhlIHBlcmZtb24gdmFsdWUgc2hvdWxkIGJlIHNldCBmb3IgSURfREZSMF9FTDEgKG5vdCBwbXV2 ZXIpLgo+ID4gPiA+Cj4gPiA+IFN1cmUsIHdpbGwgZml4IGl0Lgo+ID4gPiA+ID4gKwo+ID4gPiA+ ID4gKyAgICAgICAgICAgICAgIElEUkVHKHZjcHUtPmt2bSwgU1lTX0lEX0FBNjRERlIwX0VMMSkg Jj0gfkFSTTY0X0ZFQVRVUkVfTUFTSyhJRF9BQTY0REZSMF9FTDFfUE1VVmVyKTsKPiA+ID4gPiA+ ICsgICAgICAgICAgICAgICBJRFJFRyh2Y3B1LT5rdm0sIFNZU19JRF9BQTY0REZSMF9FTDEpIHw9 IEZJRUxEX1BSRVAoCj4gPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBBUk02NF9GRUFU VVJFX01BU0soSURfQUE2NERGUjBfRUwxX1BNVVZlciksIHBlcmZtb25fdG9fcG11dmVyKHBlcmZt b24pKTsKPiA+ID4gPiA+ICsgICAgICAgfSBlbHNlIGlmIChwZXJmbW9uID09IElEX0RGUjBfRUwx X1BlcmZNb25fSU1QREVGKSB7Cj4gPiA+ID4gPiArICAgICAgICAgICAgICAgc2V0X2JpdChLVk1f QVJDSF9GTEFHX1ZDUFVfSEFTX0lNUF9ERUZfUE1VLCAmdmNwdS0+a3ZtLT5hcmNoLmZsYWdzKTsK PiA+ID4gPiA+ICsgICAgICAgfSBlbHNlIHsKPiA+ID4gPiA+ICsgICAgICAgICAgICAgICBjbGVh cl9iaXQoS1ZNX0FSQ0hfRkxBR19WQ1BVX0hBU19JTVBfREVGX1BNVSwgJnZjcHUtPmt2bS0+YXJj aC5mbGFncyk7Cj4gPiA+ID4gPiArICAgICAgIH0KPiA+ID4gPiA+Cj4gPiA+ID4gPiAgICAgICAg IHJldHVybiAwOwo+ID4gPiA+ID4gIH0KPiA+ID4gPiA+IEBAIC01NDMsNCArNTY0LDEzIEBAIHZv aWQga3ZtX2FybV9zZXRfZGVmYXVsdF9pZF9yZWdzKHN0cnVjdCBrdm0gKmt2bSkKPiA+ID4gPiA+ ICAgICAgICAgfQo+ID4gPiA+ID4KPiA+ID4gPiA+ICAgICAgICAgSURSRUcoa3ZtLCBTWVNfSURf QUE2NFBGUjBfRUwxKSA9IHZhbDsKPiA+ID4gPiA+ICsKPiA+ID4gPiA+ICsgICAgICAgLyoKPiA+ ID4gPiA+ICsgICAgICAgICogSW5pdGlhbGlzZSB0aGUgZGVmYXVsdCBQTVV2ZXIgYmVmb3JlIHRo ZXJlIGlzIGEgY2hhbmNlIHRvCj4gPiA+ID4gPiArICAgICAgICAqIGNyZWF0ZSBhbiBhY3R1YWwg UE1VLgo+ID4gPiA+ID4gKyAgICAgICAgKi8KPiA+ID4gPiA+ICsgICAgICAgSURSRUcoa3ZtLCBT WVNfSURfQUE2NERGUjBfRUwxKSAmPSB+QVJNNjRfRkVBVFVSRV9NQVNLKElEX0FBNjRERlIwX0VM MV9QTVVWZXIpOwo+ID4gPiA+ID4gKyAgICAgICBJRFJFRyhrdm0sIFNZU19JRF9BQTY0REZSMF9F TDEpIHw9Cj4gPiA+ID4gPiArICAgICAgICAgICAgICAgRklFTERfUFJFUChBUk02NF9GRUFUVVJF X01BU0soSURfQUE2NERGUjBfRUwxX1BNVVZlciksCj4gPiA+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgICAgICBrdm1fYXJtX3BtdV9nZXRfcG11dmVyX2xpbWl0KCkpOwo+ID4gPiA+ID4gIH0K PiA+ID4gPiA+IGRpZmYgLS1naXQgYS9pbmNsdWRlL2t2bS9hcm1fcG11LmggYi9pbmNsdWRlL2t2 bS9hcm1fcG11LmgKPiA+ID4gPiA+IGluZGV4IDYyODc3NTMzNGQ1ZS4uZWVmNjdiN2Q5NzUxIDEw MDY0NAo+ID4gPiA+ID4gLS0tIGEvaW5jbHVkZS9rdm0vYXJtX3BtdS5oCj4gPiA+ID4gPiArKysg Yi9pbmNsdWRlL2t2bS9hcm1fcG11LmgKPiA+ID4gPiA+IEBAIC05Miw4ICs5MiwxMCBAQCB2b2lk IGt2bV92Y3B1X3BtdV9yZXN0b3JlX2hvc3Qoc3RydWN0IGt2bV92Y3B1ICp2Y3B1KTsKPiA+ID4g PiA+ICAvKgo+ID4gPiA+ID4gICAqIEV2YWx1YXRlcyBhcyB0cnVlIHdoZW4gZW11bGF0aW5nIFBN VXYzcDUsIGFuZCBmYWxzZSBvdGhlcndpc2UuCj4gPiA+ID4gPiAgICovCj4gPiA+ID4gPiAtI2Rl ZmluZSBrdm1fcG11X2lzXzNwNSh2Y3B1KSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBcCj4gPiA+ID4gPiAtICAgICAgICh2Y3B1LT5rdm0tPmFyY2guZGZyMF9wbXV2 ZXIuaW1wID49IElEX0FBNjRERlIwX0VMMV9QTVVWZXJfVjNQNSkKPiA+ID4gPiA+ICsjZGVmaW5l IGt2bV9wbXVfaXNfM3A1KHZjcHUpICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ID4gPiA+ICsgICAgICAgKGt2bV92 Y3B1X2hhc19wbXUodmNwdSkgJiYgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+ID4gPgo+ID4gPiA+IFdoYXQgaXMgdGhlIHJl YXNvbiBmb3IgYWRkaW5nIHRoaXMga3ZtX3ZjcHVfaGFzX3BtdSgpIGNoZWNraW5nID8KPiA+ID4g PiBJIGRvbid0IHRoaW5rIHRoaXMgcGF0Y2gncyBjaGFuZ2VzIG5lY2Vzc2l0YXRlZCB0aGlzLgo+ ID4gPiBGb3IgdGhlIHNhbWUgVk0sIGlzIGl0IHBvc3NpYmxlIHRoYXQgc29tZSBWQ1BVcyB3b3Vs ZCBoYXZlIFBNVSwgYnV0Cj4gPiA+IHNvbWUgbWF5IG5vdCBoYXZlPwo+ID4gPiBUaGF0J3Mgd2h5 IHRoZSBrdm1fdmNwdV9oYXNfcG11IGlzIGFkZGVkIGhlcmUuCj4gPgo+ID4gWWVzLCBpdCdzIHBv c3NpYmxlLiBCdXQsIGl0IGRvZXNuJ3QgYXBwZWFyIHRoYXQgdGhpcyBwYXRjaCBvciBhbnkKPiA+ IHBhdGNoZXMgaW4gdGhlIHNlcmllcyBhZGRzIGEgY29kZSB0aGF0IG5ld2x5IHVzZXMgdGhlIG1h Y3JvLgo+ID4gSSBiZWxpZXZlIHRoaXMgbWFjcm8gaXMgYWx3YXlzIHVzZWQgZm9yIHRoZSB2Q1BV cyB3aXRoIHZQTVUKPiA+IGNvbmZpZ3VyZWQgY3VycmVudGx5Lgo+ID4gRGlkIHlvdSBmaW5kIGEg Y2FzZSB3aGVyZSB0aGlzIGlzIHVzZWQgZm9yIHZDUFVzIHdpdGggbm8gdlBNVSA/Cj4gPgo+ID4g SWYgdGhpcyBjaGFuZ2UgdHJpZXMgdG8gYWRkcmVzcyBhbiBleGlzdGluZyBpc3N1ZSwgSSB0aGlu ayBpdCB3b3VsZAo+ID4gYmUgbmljZXIgdG8gZml4IHRoaXMgaW4gYSBzZXBhcmF0ZSBwYXRjaC4g T3IgaXQgd291bGQgYmUgaGVscGZ1bAo+ID4gaWYgeW91IGNvdWxkIGFkZCBhbiBleHBsYW5hdGlv biBpbiB0aGUgY29tbWl0IGxvZyBhdCBsZWFzdC4KPiBJIGRvbid0IHRoaW5rIHdlIHNob3VsZCBh c3N1bWUgdGhlIHBvdGVudGlhbCB1c2VycyBmb3IgdGhlIG1hY3JvLiBPbmx5Cj4gYWRkaW5nIGt2 bV92Y3B1X2hhc19wbXUoKSBpbiB0aGUgbWFjcm8gY2FuIGhhdmUgdGhlIHNhbWUgc2VtYW50aWNz IGFzCj4gdGhlIG9yaWdpbmFsIG1hY3JvLgo+IFRoZSBvcmlnaW5hbCBtYWNybyB3b3VsZCByZXR1 cm4gZmFsc2UgaWYgaXQgaXMgdXNlZCBieSBhIHZDUFUgd2l0aG91dAo+IHZQTVUuIEkgdGhpbmsg d2Ugc2hvdWxkIGtlZXAgaXQgYXMgdGhlIHNhbWUuCgpUaGUgb3JpZ2luYWwgbWFjcm8gYWx3YXlz IHVzZXMgZGZyMF9wbXV2ZXIuaW1wLCB3aGljaCBpcyB0aGUgUE1VIHZlcnNpb24KZm9yIHZDUFVz IHdpdGggUE1VIGNvbmZpZ3VyZWQuICBTbywgaWYgdGhlIG1hY3JvIGlzIHVzZWQgZm9yIHZDUFVz CndpdGggbm8gUE1VIGNvbmZpZ3VyZWQsIGl0IG1pZ2h0IHJldHVybiB0cnVlIChpdCBkZXBlbmRz IG9uIHRoZSB2YWx1ZQpvZiBkZnIwX3BtdXZlci5pbXApLgpPciBhbSBJIG1pc3Npbmcgc29tZXRo aW5nID8/CgpUaGFuayB5b3UsClJlaWppCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==