From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C3EC433EF for ; Mon, 4 Apr 2022 04:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377131AbiDDErc (ORCPT ); Mon, 4 Apr 2022 00:47:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233038AbiDDEr3 (ORCPT ); Mon, 4 Apr 2022 00:47:29 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1B9032EEB for ; Sun, 3 Apr 2022 21:45:31 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id g15-20020a17090adb0f00b001caa9a230c7so512055pjv.5 for ; Sun, 03 Apr 2022 21:45:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=kO4FdgYOebV/t2yzqBUOJ9hdCnVOAE3BWF9Xy8r7hy5NcvqQG9Q59fB2bGDz3+c94d tzqJw1ebi1BVASe6U2F6kGGXnf8lsXzK3vuEkvTHitRwLEPwoilxOyk3Vk07cBPVgcbF ue4XLYc4quOAF2XEnzJm7J0Gv/svvXxIfc2fSdexbpx2QcdTBwR5rcljcYhLapjF/0Pf t44yEaWd3T89rgPU9PQCuCtS7eGl7rqKj5LfFqG4ovsi3qcjmGPiktdZU9tq6DqSzj7i 7hcDvWP9+15F67X9PrYumh8bQaJy1B2Kx7moJbcJNCEk4aR6eaJnViNcNQmPbLuepjRS 8iYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=sfHRKuWMJeYWkpPkLQxD2YQNKwORCF/K96YpuXbuX5qKCbMjnbufIOJEIQAEbTDQMa WdQGDZYy3utskEAxwKrzroGK0r7XNKJriws5Y96UTyIrdJGZghlzHq+Oc3vWeeJxKr9R YrlQvRJ0t+ijUHjoMNqsG/catDPgtYEH0QWfSxid3rByaUfsmE+BHxIkYB4EzJGrKjTq bQKWx0yzBxXzl4lvtcxEYL7XN3RSWaWLDrAsAnjZT+aNZzgxjRBmuknw/9IVvNeC5RXo SXCGOfuDjnRuyBr0kWLSyeOW/ylmAAn4kewHTCybdDvPcsiO0qiKmIyel+KPYpqslKFm yscA== X-Gm-Message-State: AOAM532u0QBT9AomvDX/1PL+Je3cHh1e+Rl1fXZBm5/D4PNyySMxyJrp KkPWIMKXItnZ2tRX2cwnNbCvfg0OB1virkk23wuNPw== X-Google-Smtp-Source: ABdhPJzDVFMCClRUsK6gQWVxwlJiuN5q5hN2bBgrZWH+gsR5sokMSlYJUr9RMO+e4xu5pPL/2GX8kvOJQQ01h2wlkk8= X-Received: by 2002:a17:90b:2350:b0:1ca:23b5:69a6 with SMTP id ms16-20020a17090b235000b001ca23b569a6mr20934316pjb.9.1649047530910; Sun, 03 Apr 2022 21:45:30 -0700 (PDT) MIME-Version: 1.0 References: <20220401010832.3425787-1-oupton@google.com> <20220401010832.3425787-4-oupton@google.com> In-Reply-To: <20220401010832.3425787-4-oupton@google.com> From: Reiji Watanabe Date: Sun, 3 Apr 2022 21:45:15 -0700 Message-ID: Subject: Re: [PATCH v2 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests To: Oliver Upton Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Linux ARM , Peter Shier , Ricardo Koller Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Thu, Mar 31, 2022 at 6:08 PM Oliver Upton wrote: > > To date KVM has not trapped ID register accesses from AArch32, meaning > that guests get an unconstrained view of what hardware supports. This > can be a serious problem because we try to base the guest's feature > registers on values that are safe system-wide. Furthermore, KVM does not > implement the latest ISA in the PMU and Debug architecture, so we > constrain these fields to supported values. > > Since KVM now correctly handles CP15 and CP10 register traps, we no > longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead > emulate reads with their safe values. > > Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe BTW, due to this, on a system that supports PMUv3, ID_DFR0_E1 value will become 0 for the aarch32 guest without PMUv3. This is the correct behavior, but it affects migration. I'm not sure how much we should care about migration of the aarch32 guest though (and it will be resolved once ID registers become configurable anyway). Thanks, Reiji From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 425C1C433EF for ; Mon, 4 Apr 2022 04:45:36 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7F24349F4A; Mon, 4 Apr 2022 00:45:35 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@google.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E4mgtFamlxHZ; Mon, 4 Apr 2022 00:45:34 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 746674A104; Mon, 4 Apr 2022 00:45:34 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 07C0849F4A for ; Mon, 4 Apr 2022 00:45:33 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kjqeJhIMABpL for ; Mon, 4 Apr 2022 00:45:32 -0400 (EDT) Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id EFEA349F2A for ; Mon, 4 Apr 2022 00:45:31 -0400 (EDT) Received: by mail-pj1-f48.google.com with SMTP id ku13-20020a17090b218d00b001ca8fcd3adeso1975493pjb.2 for ; Sun, 03 Apr 2022 21:45:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=kO4FdgYOebV/t2yzqBUOJ9hdCnVOAE3BWF9Xy8r7hy5NcvqQG9Q59fB2bGDz3+c94d tzqJw1ebi1BVASe6U2F6kGGXnf8lsXzK3vuEkvTHitRwLEPwoilxOyk3Vk07cBPVgcbF ue4XLYc4quOAF2XEnzJm7J0Gv/svvXxIfc2fSdexbpx2QcdTBwR5rcljcYhLapjF/0Pf t44yEaWd3T89rgPU9PQCuCtS7eGl7rqKj5LfFqG4ovsi3qcjmGPiktdZU9tq6DqSzj7i 7hcDvWP9+15F67X9PrYumh8bQaJy1B2Kx7moJbcJNCEk4aR6eaJnViNcNQmPbLuepjRS 8iYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=SA+st294zWeCKmlimhVhXEWIxiRmuBJLr5NXWYgVgPYomK+PRAiZcdbluMPOQIZdi/ by1fU/c4OBnpPixJ9zsKWlmQ6WEW9Y/IQ4WrmMSb+XHh4iy2sY9KNJcuHak6pX4+BiSy zWRHYfCTDlT8ZIoQdtDQq3/zcb2H3Cn9YZn8sGq/DBsh9l7nRU2Zz5fCmDIfmaMWEiXr f4kX7KWRAR9wv9l0kR30f2wbOFI0pwFlM5MIa8KBS5YDqOMpFiNz8ARgNzZHA+tt5/Qv uur0WnS4x0i/ASFS8M9yFllr7DzNMEwMgA6F+rIr51TyBvwGKqrJiaOdB+DCO2n6o7vX PXdQ== X-Gm-Message-State: AOAM531cjRo3m0h+/Jvim+OuKhUF/cqKr9DG1O8EIpAQQVb895RnAgEk 6H7N2FCmRSYcurgejPoxbc+Na6DPUtRBC32OZge9bg== X-Google-Smtp-Source: ABdhPJzDVFMCClRUsK6gQWVxwlJiuN5q5hN2bBgrZWH+gsR5sokMSlYJUr9RMO+e4xu5pPL/2GX8kvOJQQ01h2wlkk8= X-Received: by 2002:a17:90b:2350:b0:1ca:23b5:69a6 with SMTP id ms16-20020a17090b235000b001ca23b569a6mr20934316pjb.9.1649047530910; Sun, 03 Apr 2022 21:45:30 -0700 (PDT) MIME-Version: 1.0 References: <20220401010832.3425787-1-oupton@google.com> <20220401010832.3425787-4-oupton@google.com> In-Reply-To: <20220401010832.3425787-4-oupton@google.com> From: Reiji Watanabe Date: Sun, 3 Apr 2022 21:45:15 -0700 Message-ID: Subject: Re: [PATCH v2 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests To: Oliver Upton Cc: kvm@vger.kernel.org, Marc Zyngier , Peter Shier , kvmarm@lists.cs.columbia.edu, Linux ARM X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Mar 31, 2022 at 6:08 PM Oliver Upton wrote: > > To date KVM has not trapped ID register accesses from AArch32, meaning > that guests get an unconstrained view of what hardware supports. This > can be a serious problem because we try to base the guest's feature > registers on values that are safe system-wide. Furthermore, KVM does not > implement the latest ISA in the PMU and Debug architecture, so we > constrain these fields to supported values. > > Since KVM now correctly handles CP15 and CP10 register traps, we no > longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead > emulate reads with their safe values. > > Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe BTW, due to this, on a system that supports PMUv3, ID_DFR0_E1 value will become 0 for the aarch32 guest without PMUv3. This is the correct behavior, but it affects migration. I'm not sure how much we should care about migration of the aarch32 guest though (and it will be resolved once ID registers become configurable anyway). Thanks, Reiji _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 059E5C433EF for ; Mon, 4 Apr 2022 04:46:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KGZNJMTx2qsXcyHQC+M8Tcve/UMyKsUAyhFuPbVwJ9A=; b=Aj6h+R3R0Huwps fOC1kH0xVzC1Fw96Ltwbb/ZwZzzHlw6+zUGVTIgdzzcvQYFdALZYkBA+D/tnibg58XoG+2adZJCKV rxHZ33Ngp8qsqKwnBOneWxhIjpvRlUm9mVthJhH8+u07jrkh48oqDWAynzNMdJW1NqPMdNYAhTQ2R Y/hgLvUIOKLECJ0RirNjz1398CShfI9W5odVb2zaQ/7k0xKx72cJDYwhcke+maUd97Eujq4QLpXod 5dEGNC4H81O10pmByuGhll7QHVwG92+misQk7ugzkB6I0E9sT5TWLiDAZIhRAfJOGYS59NTC8Y8eW QsTf4snda1TDX3cdg6Tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbEau-00D3V4-3A; Mon, 04 Apr 2022 04:45:36 +0000 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbEaq-00D3UO-L9 for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2022 04:45:33 +0000 Received: by mail-pj1-x1033.google.com with SMTP id a16-20020a17090a6d9000b001c7d6c1bb13so7901657pjk.4 for ; Sun, 03 Apr 2022 21:45:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=kO4FdgYOebV/t2yzqBUOJ9hdCnVOAE3BWF9Xy8r7hy5NcvqQG9Q59fB2bGDz3+c94d tzqJw1ebi1BVASe6U2F6kGGXnf8lsXzK3vuEkvTHitRwLEPwoilxOyk3Vk07cBPVgcbF ue4XLYc4quOAF2XEnzJm7J0Gv/svvXxIfc2fSdexbpx2QcdTBwR5rcljcYhLapjF/0Pf t44yEaWd3T89rgPU9PQCuCtS7eGl7rqKj5LfFqG4ovsi3qcjmGPiktdZU9tq6DqSzj7i 7hcDvWP9+15F67X9PrYumh8bQaJy1B2Kx7moJbcJNCEk4aR6eaJnViNcNQmPbLuepjRS 8iYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EEBN46zG2gvj2WY3lcxbVjrOksL0c/6WsjgZKCCzd/I=; b=SdmYOcne3miMAgh8ZIfVP7tFdF9R2L+ALQbKRWiWNrixvPBeox4yGANSZpmLbMmNgF GhWr3hxlYQJfbnnOKGaRziCPCWdgOhqKkX1e2m/qo7tEKd7weq9Ljk92d9wusVYf5xXg FBpjClPq1IT7UI2eG+Inl0L8M0c89XuMHFPutBfUE2hFq9lVPq1tckIdMk9+31vfB/Lw WALoORA3n4uG6I8dPFgxzTZYy8/jIXP+iKOTD0OYH2yBUERyjUg+zDs0Sy+SC2HAiTxn Gh4/abgY6dLcZAWoS7Zs1D/LaDRv2+6enxtJ5rchQMtK7+mkt60syKYqOxLW+KVNWUxV Kguw== X-Gm-Message-State: AOAM533pv05VXqagSIqjLx65kwpWeH6ZxbzraB4q3SMoFgi5pYVWgEge QaSR4qFwM9uuOAwMg18QwCSocEJ5WrbdC57kVWN3+w== X-Google-Smtp-Source: ABdhPJzDVFMCClRUsK6gQWVxwlJiuN5q5hN2bBgrZWH+gsR5sokMSlYJUr9RMO+e4xu5pPL/2GX8kvOJQQ01h2wlkk8= X-Received: by 2002:a17:90b:2350:b0:1ca:23b5:69a6 with SMTP id ms16-20020a17090b235000b001ca23b569a6mr20934316pjb.9.1649047530910; Sun, 03 Apr 2022 21:45:30 -0700 (PDT) MIME-Version: 1.0 References: <20220401010832.3425787-1-oupton@google.com> <20220401010832.3425787-4-oupton@google.com> In-Reply-To: <20220401010832.3425787-4-oupton@google.com> From: Reiji Watanabe Date: Sun, 3 Apr 2022 21:45:15 -0700 Message-ID: Subject: Re: [PATCH v2 3/3] KVM: arm64: Start trapping ID registers for 32 bit guests To: Oliver Upton Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Linux ARM , Peter Shier , Ricardo Koller X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220403_214532_729678_5D1CB8E6 X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 31, 2022 at 6:08 PM Oliver Upton wrote: > > To date KVM has not trapped ID register accesses from AArch32, meaning > that guests get an unconstrained view of what hardware supports. This > can be a serious problem because we try to base the guest's feature > registers on values that are safe system-wide. Furthermore, KVM does not > implement the latest ISA in the PMU and Debug architecture, so we > constrain these fields to supported values. > > Since KVM now correctly handles CP15 and CP10 register traps, we no > longer need to clear HCR_EL2.TID3 for 32 bit guests and will instead > emulate reads with their safe values. > > Signed-off-by: Oliver Upton Reviewed-by: Reiji Watanabe BTW, due to this, on a system that supports PMUv3, ID_DFR0_E1 value will become 0 for the aarch32 guest without PMUv3. This is the correct behavior, but it affects migration. I'm not sure how much we should care about migration of the aarch32 guest though (and it will be resolved once ID registers become configurable anyway). Thanks, Reiji _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel