From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: ** X-Spam-Status: No, score=2.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEE73C2B9F7 for ; Wed, 26 May 2021 08:00:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44A04613D3 for ; Wed, 26 May 2021 08:00:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44A04613D3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98D266EC29; Wed, 26 May 2021 08:00:11 +0000 (UTC) Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F1096EC29 for ; Wed, 26 May 2021 08:00:10 +0000 (UTC) Received: by mail-wm1-x335.google.com with SMTP id y184-20020a1ce1c10000b02901769b409001so395459wmg.3 for ; Wed, 26 May 2021 01:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=GfwRj98POsvrbO3K0pzw9bSxUUt/IU1P9BkPwlzftF8=; b=b4h88skHOifBGL0khktzNyQdSGiIGeZHokelOpQgjlekbTRaTTup1XEfj+jLViuWME TyuiXZ9BKPA1/M20Dv5KnE+tKESdBQR8YzHcDj6MD82Um/p00P+wmiglRXz9/lnqmcom Nu2XeaCGWa9bk8hxBS5jYkB2COb8wzUHpGAswxAIgThJAvwPC6LhJM8HTHfMyz/pnQ5/ A+j6GNlpce1lSWhrK3arEarTIIM1XlG2IduLPq39a5qpS6U1YnwMlBb0HGOIgtPaRy4i ABQC+0r5LLd/ApVQMvwLCs6NCVCNlMYjW17plxeOyrjFJ6khk8V0svW+bKWkJ6twd8kl Bb9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=GfwRj98POsvrbO3K0pzw9bSxUUt/IU1P9BkPwlzftF8=; b=A7T9asXNhEuDzn9nSCd9VkBN3OFaA3dhjQJbCuZ2MDknXjbr8pVezjzwg4ekhKEJve xMe2CeDse9ToWbW6IPCD3eLPY5tmosYhsJfMZaEOvoSZpyfJ+bSYktTaUVc/eNYs1RMC Rx2DXZ1/EwApawujwBtmvvfREYLj4EsePCruMnHRJuZFyoXpfMgT9xwRR5MaHQrEmrTI d/wohMRw/RQmmuSFZ6YR4OIDA8BcxycjfkKHqgNaCDjjlrTtPY/AB8yv4dmjcbd+zc/S FBjU7JLUuEdNtZ/AmZ1Q/ZCZ93tNMUX6QhMAPEhpRYmv92pU5vijPHzWYOuaUe1dn6cr O0vw== X-Gm-Message-State: AOAM530svaULH089HSmFmg9NiDeRUkhAFwdjwnABQxYnoH8kqyqq677a oDkvBLlDnIXQNDBROIegTGuRzKTAX5lLoJVgBT8= X-Google-Smtp-Source: ABdhPJw2pqjUlSghIw3lFWImLjpOFfUI+le6BqBxaJFGfJIANc5K69qXH3ERe94ZyOcF3dnO2sNsKIrEx2UoY3Lh9mo= X-Received: by 2002:a05:600c:3227:: with SMTP id r39mr27807520wmp.26.1622016008763; Wed, 26 May 2021 01:00:08 -0700 (PDT) MIME-Version: 1.0 References: <20210425123607.26537-1-kevin3.tang@gmail.com> <20210425123607.26537-5-kevin3.tang@gmail.com> <20210430092249.n75to2das5m6p4zb@gilmour> In-Reply-To: From: Chunyan Zhang Date: Wed, 26 May 2021 15:59:32 +0800 Message-ID: Subject: Re: [PATCH v5 4/6] drm/sprd: add Unisoc's drm display controller driver To: Robin Murphy Content-Type: multipart/alternative; boundary="00000000000005ba6d05c3370898" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , DTML , Kevin Tang , David Airlie , Joerg Roedel , "Linux-Kernel@Vger. Kernel. Org" , ML dri-devel , Rob Herring , Maxime Ripard , Orson Zhai , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --00000000000005ba6d05c3370898 Content-Type: text/plain; charset="UTF-8" Hi Robin, On Tue, 18 May 2021 at 00:35, Robin Murphy wrote: > On 2021-05-17 10:27, Joerg Roedel wrote: > > On Fri, Apr 30, 2021 at 08:20:10PM +0800, Kevin Tang wrote: > >> Cc Robin & Joerg > > > > This is just some GPU internal MMU being used here, it seems. It doesn't > > use the IOMMU core code, so no Ack needed from the IOMMU side. > > Except the actual MMU being used is drivers/iommu/sprd_iommu.c - this is Yes, it is using drivers/iommu/sprd_iommu.c. > > just the display driver poking directly at the interrupt registers of > its associated IOMMU instance. Actually the display driver is poking its own interrupt registers in which some interrupts are caused by using IOMMU, others are purely its own ones: +/* Interrupt control & status bits */ +#define BIT_DPU_INT_DONE BIT(0) +#define BIT_DPU_INT_TE BIT(1) +#define BIT_DPU_INT_ERR BIT(2) +#define BIT_DPU_INT_UPDATE_DONE BIT(4) +#define BIT_DPU_INT_VSYNC BIT(5) +#define BIT_DPU_INT_MMU_VAOR_RD BIT(16) +#define BIT_DPU_INT_MMU_VAOR_WR BIT(17) +#define BIT_DPU_INT_MMU_INV_RD BIT(18) +#define BIT_DPU_INT_MMU_INV_WR BIT(19) >From what I see in the product code, along with the information my colleagues told me, these _INT_MMU_ interrupts only need to be dealt with by client devices(i.e. display). IOMMU doesn't even have the INT_STS register for some early products which we're trying to support in the mainstream kernel. > I still think this is wrong, and that it > should be treated as a shared interrupt, with the IOMMU driver handling > its own registers and reporting to the client through the standard > report_iommu_fault() API, especially since there are apparently more > blocks using these IOMMU instances than just the display. > For the next generation IOMMU, we will handle interrupts in IOMMU drivers like you say here. But like I explained above, we have to leave interrupt handling in the client device driver since the IOMMU we 're using in this display device doesn't have an INT_STS register in the IOMMU register range. Thanks for the review, Chunyan > Robin. > --00000000000005ba6d05c3370898 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Robin,

On Tue, 18 May 2021 at 00:35, Robin Murp= hy <robin.murp= hy@arm.com> wrote:
On 2021-05-17 10:27, Joerg Roedel wrote:
> On Fri, Apr 30, 2021 at 08:20:10PM +0800, Kevin Tang wrote:
>> Cc=C2=A0 Robin & Joerg
>
> This is just some GPU internal MMU being used here, it seems. It doesn= 't
> use the IOMMU core code, so no Ack needed from the IOMMU side.

Except the actual MMU being used is drivers/iommu/sprd_iommu.c - this is

Yes, it is using drivers/iommu/sprd_iommu.c.
=C2=A0

just the display driver poking directly at the interrupt registers of
its associated IOMMU instance.

Actually the display dri= ver is poking its own interrupt registers in which some interrupts are caus= ed by using IOMMU, others are purely its own ones:
+/*=C2=A0Inte= rrupt=C2=A0control & status bits */
+#define BIT_DPU_INT_DONE= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(0)
+#define B= IT_DPU_INT_TE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= BIT(1)
+#define BIT_DPU_INT_ERR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT(2)
+#define BIT_DPU_INT_U= PDATE_DONE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT(4)+#define BIT_DPU_INT_VSYNC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= BIT(5)
+#define BIT_DPU_INT_MMU_VAOR_RD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 BIT(16)
+#define BIT_DPU_INT_MMU_VAOR_WR=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT(17)
+#define BIT_DP= U_INT_MMU_INV_RD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(18)
+#define BIT_DPU_INT_MMU_INV_WR=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0BIT(19)

From wha= t I see in the product code, along with the information my colleagues told = me, these _INT_MMU_ interrupts only need to be dealt with by client device= s(i.e. display). IOMMU doesn't even have the INT_STS register for some = early products which we're trying to support in the mainstream kernel.<= /span>
=C2=A0
I still think this is wrong, and that it
should be treated as a shared interrupt, with the IOMMU driver handling its own registers and reporting to the client through the standard
report_iommu_fault() API, especially since there are apparently more
blocks using these IOMMU instances than just the display.
<= div>
For the next generation IOMMU, we will handle interrupts in IOMMU driv= ers like you say here.
But like I explained above, we have to leave interrupt = handling in the client device driver since the IOMMU we 're using in th= is display device doesn't have an INT_STS register in the IOMMU registe= r range.
=
Than= ks for the review,
Chunyan


Robin.
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