From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E655C43334 for ; Sun, 17 Jul 2022 23:35:58 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4LmM0s0Jfrz3c6f for ; Mon, 18 Jul 2022 09:35:57 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=g+RS9rMN; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::e2c; helo=mail-vs1-xe2c.google.com; envelope-from=shorne@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=g+RS9rMN; dkim-atps=neutral Received: from mail-vs1-xe2c.google.com (mail-vs1-xe2c.google.com [IPv6:2607:f8b0:4864:20::e2c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Lm0WW130Bz2xgX for ; Sun, 17 Jul 2022 19:42:46 +1000 (AEST) Received: by mail-vs1-xe2c.google.com with SMTP id 125so8005253vsx.7 for ; Sun, 17 Jul 2022 02:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jP9irTWDrAJ3uK+gZP/3yO1ZauIstFAwM+AwsXaPL1Y=; b=g+RS9rMNBnNN6FT6Kn7ke5GSmoF6hlDsdH4YV90BiJHyO0tAUK4GOLMKfAdnS8Bh1O 7hFOSYr0Mv7JNWTVv5QI3da9bF+MNLUURbVfhhuuHGvkeq/X4Nv+/MSVnK6dWcoLNj9A PqzLj5AXFy20LIKW+AtnjlvRIBOKD5m5p7vbQ1RQFgfFvcM92d0EE6BHA9AuVr8xS30E 6GV3ziaGw+4FR4X26vNoHsO/i9y7DVPCMVJGsjqnU7fSM6bCx+EJXfl2JcUe+IKPe0fs dZB3pxVqMsJxmDF3Yzo6XWsdlxMO+pPlOixU/G6/qpklTX6ZSi2ncsDnCQZRHbsHCW8Z B41w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jP9irTWDrAJ3uK+gZP/3yO1ZauIstFAwM+AwsXaPL1Y=; b=3aXMjZTKKQ3C/DwCUJlkehAebzVnqOOPA2zIoiuqc6hUiiz5cZ/Zwrcem/20POPr+4 OtbwdXEMj9Z0NQcch7RsJdY9DwFUnVN7yRnJfdZ1vFTaiaLUmbhptSRegJcyyTorruQI reMP72twVOurZGe19STZqz/sOtJl2HQ1V0YLlsT8TXhtvhlgUZ/EBHAMOhxf1ybGaJ3M +eUop6QtaN8pWEZF0HHehrAotZ5hJsZR39a1d/SV+Nu5XPTvpV4q8XGOLj01NIijPbMC 021Kj2ww4QhvsIMOsJjhn2qOHzvpxwRPt2W4TY2ZeOjQu/TgfEOI75dY7weXjBfUpZOd Ot1g== X-Gm-Message-State: AJIora8AvmgzcW3qwRK5+mCYQXadb8CHzN7KoebTYsVS1yB8kWrM1Etx wBhYgG/b30UoJ4X+sMbDlpQ+xIFPiiWqki+ue/Q= X-Google-Smtp-Source: AGRyM1tPiWzs22MFdZvBNMRZwhjGC0Hft44kTAMnIgXFbqWngh0GfbCoaxNKR494SbYZRCSEoZime+FASrWOg6GRjfU= X-Received: by 2002:a05:6102:2411:b0:357:3349:b305 with SMTP id j17-20020a056102241100b003573349b305mr8144937vsi.5.1658050962626; Sun, 17 Jul 2022 02:42:42 -0700 (PDT) MIME-Version: 1.0 References: <20220717033453.2896843-1-shorne@gmail.com> <20220717033453.2896843-2-shorne@gmail.com> In-Reply-To: From: Stafford Horne Date: Sun, 17 Jul 2022 18:42:32 +0900 Message-ID: Subject: Re: [PATCH v2 1/2] asm-generic: Remove pci.h copying remaining code to x86 To: Geert Uytterhoeven Content-Type: multipart/alternative; boundary="000000000000a59cf905e3fd129d" X-Mailman-Approved-At: Mon, 18 Jul 2022 09:35:23 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:IA64 \(Itanium\) PL..." , Matthew Rosato , Dave Hansen , "Gustavo A. R. Silva" , Max Filippov , Paul Mackerras , "H. Peter Anvin" , sparclinux , Alexander Gordeev , linux-riscv , Linux-Arch , linux-s390 , Arnd Bergmann , the arch/x86 maintainers , Ingo Molnar , linux-pci , Matt Turner , Christian Borntraeger , "open list:TENSILICA XTENSA PORT \(xtensa\)" , Albert Ou , Kees Cook , Vasily Gorbik , Niklas Schnelle , Heiko Carstens , linux-m68k , Ivan Kokshaysky , Paul Walmsley , Bjorn Helgaas , Thomas Gleixner , Richard Henderson , Chris Zankel , Pierre Morel , Nick Child , LKML , Palmer Dabbelt , Sven Schnelle , alpha , Borislav Petkov , linuxppc-dev , "David S. Miller" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" --000000000000a59cf905e3fd129d Content-Type: text/plain; charset="UTF-8" On Sun, Jul 17, 2022, 6:23 PM Geert Uytterhoeven wrote: > Hi Stafford, > > On Sun, Jul 17, 2022 at 5:35 AM Stafford Horne wrote: > > The generic pci.h header now only provides a definition of > > pci_get_legacy_ide_irq which is used by architectures that support PNP. > > Of the architectures that use asm-generic/pci.h this is only x86. > > > > This patch removes the old pci.h in order to make room for a new > > pci.h to be used by arm64, riscv, openrisc, etc. > > > > The existing code in pci.h is moved out to x86. On other architectures > > we clean up any outstanding references. > > > > Suggested-by: Arnd Bergmann > > Link: > https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn=Jbvf=nkbpVaZCycyv40pZNCJJXQ@mail.gmail.com/ > > Signed-off-by: Stafford Horne > > Thanks for your patch! > > > --- a/arch/m68k/include/asm/pci.h > > +++ b/arch/m68k/include/asm/pci.h > > @@ -2,11 +2,14 @@ > > #ifndef _ASM_M68K_PCI_H > > #define _ASM_M68K_PCI_H > > > > -#include > > - > > #define pcibios_assign_all_busses() 1 > > > > #define PCIBIOS_MIN_IO 0x00000100 > > #define PCIBIOS_MIN_MEM 0x02000000 > > > > +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int > channel) > > +{ > > + return channel ? 15 : 14; > > +} > > + > > I thought you were not going to add this? > I though so too. Somehow I lost track of a fixup. I'll send a v3 tomorrow. -Stafford > --000000000000a59cf905e3fd129d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Sun, Jul 17, 2022, 6:23 PM Geert Uytterhoeven <<= a href=3D"mailto:geert@linux-m68k.org">geert@linux-m68k.org> wrote:<= br>
Hi Stafford,

On Sun, Jul 17, 2022 at 5:35 AM Stafford Horne <shorne@gmail.com> w= rote:
> The generic pci.h header now only provides a definition of
> pci_get_legacy_ide_irq which is used by architectures that support PNP= .
> Of the architectures that use asm-generic/pci.h this is only x86.
>
> This patch removes the old pci.h in order to make room for a new
> pci.h to be used by arm64, riscv, openrisc, etc.
>
> The existing code in pci.h is moved out to x86.=C2=A0 On other archite= ctures
> we clean up any outstanding references.
>
> Suggested-by: Arnd Bergmann <arnd@arndb.de>
> Link: https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn= =3DJbvf=3DnkbpVaZCycyv40pZNCJJXQ@mail.gmail.com/
> Signed-off-by: Stafford Horne <shorne@gmail.com>

Thanks for your patch!

> --- a/arch/m68k/include/asm/pci.h
> +++ b/arch/m68k/include/asm/pci.h
> @@ -2,11 +2,14 @@
>=C2=A0 #ifndef _ASM_M68K_PCI_H
>=C2=A0 #define _ASM_M68K_PCI_H
>
> -#include <asm-generic/pci.h>
> -
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 pcibios_assign_all_busses()= =C2=A0 =C2=A0 =C2=A01
>
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCIBIOS_MIN_IO=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 0x00000100
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCIBIOS_MIN_MEM=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A00x02000000
>
> +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int cha= nnel)
> +{
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0return channel ? 15 : 14;
> +}
> +

I thought you were not going to add this?

I though so too. Somehow I lost tr= ack of a fixup.

I'll= send a v3 tomorrow.

-St= afford=C2=A0
--000000000000a59cf905e3fd129d-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stafford Horne Subject: Re: [PATCH v2 1/2] asm-generic: Remove pci.h copying remaining code to x86 Date: Sun, 17 Jul 2022 18:42:32 +0900 Message-ID: References: <20220717033453.2896843-1-shorne@gmail.com> <20220717033453.2896843-2-shorne@gmail.com> Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="000000000000a59cf905e3fd129d" Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jP9irTWDrAJ3uK+gZP/3yO1ZauIstFAwM+AwsXaPL1Y=; b=g+RS9rMNBnNN6FT6Kn7ke5GSmoF6hlDsdH4YV90BiJHyO0tAUK4GOLMKfAdnS8Bh1O 7hFOSYr0Mv7JNWTVv5QI3da9bF+MNLUURbVfhhuuHGvkeq/X4Nv+/MSVnK6dWcoLNj9A PqzLj5AXFy20LIKW+AtnjlvRIBOKD5m5p7vbQ1RQFgfFvcM92d0EE6BHA9AuVr8xS30E 6GV3ziaGw+4FR4X26vNoHsO/i9y7DVPCMVJGsjqnU7fSM6bCx+EJXfl2JcUe+IKPe0fs dZB3pxVqMsJxmDF3Yzo6XWsdlxMO+pPlOixU/G6/qpklTX6ZSi2ncsDnCQZRHbsHCW8Z B41w== In-Reply-To: List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+glppe-linuxppc-embedded-2=m.gmane-mx.org@lists.ozlabs.org Sender: "Linuxppc-dev" To: Geert Uytterhoeven Cc: "open list:IA64 (Itanium) PL..." , Matthew Rosato , Dave Hansen , "Gustavo A. R. Silva" , Max Filippov , Paul Mackerras , "H. Peter Anvin" , sparclinux , Alexander Gordeev , linux-riscv , Linux-Arch , linux-s390 , Arnd Bergmann , the arch/x86 maintainers , Ingo Molnar , linux-pci , Matt Turner , Christian Borntraeger , "open list:TENSILICA XTENSA PORT (xtensa)" , Albert Ou , Kees Cook , Va --000000000000a59cf905e3fd129d Content-Type: text/plain; charset="UTF-8" On Sun, Jul 17, 2022, 6:23 PM Geert Uytterhoeven wrote: > Hi Stafford, > > On Sun, Jul 17, 2022 at 5:35 AM Stafford Horne wrote: > > The generic pci.h header now only provides a definition of > > pci_get_legacy_ide_irq which is used by architectures that support PNP. > > Of the architectures that use asm-generic/pci.h this is only x86. > > > > This patch removes the old pci.h in order to make room for a new > > pci.h to be used by arm64, riscv, openrisc, etc. > > > > The existing code in pci.h is moved out to x86. On other architectures > > we clean up any outstanding references. > > > > Suggested-by: Arnd Bergmann > > Link: > https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn=Jbvf=nkbpVaZCycyv40pZNCJJXQ@mail.gmail.com/ > > Signed-off-by: Stafford Horne > > Thanks for your patch! > > > --- a/arch/m68k/include/asm/pci.h > > +++ b/arch/m68k/include/asm/pci.h > > @@ -2,11 +2,14 @@ > > #ifndef _ASM_M68K_PCI_H > > #define _ASM_M68K_PCI_H > > > > -#include > > - > > #define pcibios_assign_all_busses() 1 > > > > #define PCIBIOS_MIN_IO 0x00000100 > > #define PCIBIOS_MIN_MEM 0x02000000 > > > > +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int > channel) > > +{ > > + return channel ? 15 : 14; > > +} > > + > > I thought you were not going to add this? > I though so too. Somehow I lost track of a fixup. I'll send a v3 tomorrow. -Stafford > --000000000000a59cf905e3fd129d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Sun, Jul 17, 2022, 6:23 PM Geert Uytterhoeven <<= a href=3D"mailto:geert@linux-m68k.org">geert@linux-m68k.org> wrote:<= br>
Hi Stafford,

On Sun, Jul 17, 2022 at 5:35 AM Stafford Horne <shorne@gmail.com> w= rote:
> The generic pci.h header now only provides a definition of
> pci_get_legacy_ide_irq which is used by architectures that support PNP= .
> Of the architectures that use asm-generic/pci.h this is only x86.
>
> This patch removes the old pci.h in order to make room for a new
> pci.h to be used by arm64, riscv, openrisc, etc.
>
> The existing code in pci.h is moved out to x86.=C2=A0 On other archite= ctures
> we clean up any outstanding references.
>
> Suggested-by: Arnd Bergmann <arnd@arndb.de>
> Link: https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn= =3DJbvf=3DnkbpVaZCycyv40pZNCJJXQ@mail.gmail.com/
> Signed-off-by: Stafford Horne <shorne@gmail.com>

Thanks for your patch!

> --- a/arch/m68k/include/asm/pci.h
> +++ b/arch/m68k/include/asm/pci.h
> @@ -2,11 +2,14 @@
>=C2=A0 #ifndef _ASM_M68K_PCI_H
>=C2=A0 #define _ASM_M68K_PCI_H
>
> -#include <asm-generic/pci.h>
> -
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 pcibios_assign_all_busses()= =C2=A0 =C2=A0 =C2=A01
>
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCIBIOS_MIN_IO=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 0x00000100
>=C2=A0 #define=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCIBIOS_MIN_MEM=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A00x02000000
>
> +static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int cha= nnel)
> +{
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0return channel ? 15 : 14;
> +}
> +

I thought you were not going to add this?

I though so too. Somehow I lost tr= ack of a fixup.

I'll= send a v3 tomorrow.

-St= afford=C2=A0
--000000000000a59cf905e3fd129d--