From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Goldschmidt Date: Thu, 14 Feb 2019 16:39:13 +0100 Subject: [U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM In-Reply-To: <2d4a246d-87fa-f38d-4e70-97aec2211897@kernel.org> References: <20190207212309.27559-1-simon.k.r.goldschmidt@gmail.com> <2d4a246d-87fa-f38d-4e70-97aec2211897@kernel.org> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Feb 14, 2019 at 4:37 PM Dinh Nguyen wrote: > > Hi Marek, > > On 2/9/19 4:01 AM, Marek Vasut wrote: > > On 2/7/19 10:23 PM, Simon Goldschmidt wrote: > >> To clean up reset handling for socfpga gen5, let's move the code snippet > >> taking the DDR controller out of reset from SPL to the DDR driver. > >> > >> While at it, port the ddr driver to UCLASS_RAM and use dts. > >> > >> Signed-off-by: Simon Goldschmidt > >> --- > >> > >> This is an RFC to show what the SDRAM driver moved to DM (UCLASS_RAM) would > >> look like. It's RFC both because Dinh did not seem too fond of changing the > >> register address of the SDR in devicetree to include what the undocumented > >> registers 'sequencer.c' uses as well as because of my observed code growth. > > > > Dinh, if the SDRAM controller spans some addresses, it should be > > described like so in the DT. Whether those registers are documented or > > not does not matter, DT is a hardware description and should describe > > hardware accurately. > > Yes, I agree with above statement. I'll wait for this patch to land here > and will take the DTS patch to sync up Linux and U-Boot DTS. Thanks. I'll first work up the U-Boot patch and once that's in an acceptable state I'll send v2 of the Linux patch (which has compiler errors in the suspend code in v1). Regards, Simon