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d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DSn6XjRg0PbwGAe5aupCxoR3xo9khOKhTSDoJF9mVDo=; b=BXTNN3+0t7vhPjsiWmgcDLP78ZNmqu7AHMG96yGDTgEFlHTNRC7lcF8p0J8IF5Rrw1 IJ3Om+MqKrn1uXmShPfFdsKR1xNJJbJGyratyVuz+ltElgqw5/wl7pN1JJhKA+4KWZu6 D/pMk3j5cGUWOYu1D3cYdU2i906fwpWVzxiIWvsZfrkTKrv0mKn4Ve4tJ9KrQl6tPZPC xtoh5wcLGFHAyMPF3+cecg6fAF8A0pAcyHw5VfEkUsw8gvJ7LdYIoh09hCUahVLGaVe3 V6ftDffwNm3UuZshn/Z3zSorXtK1WONp/1QbzbmDfuld/5BR9deC/6xR3a+01zpRC/eq y2vg== X-Gm-Message-State: AOAM532L0UzUWNx3TCSEhnKYvX2O70hBvBzSIpjbtEJatvNxdVQocHJw kv/EbW60m0uS6EKeEXu9wb0ebZULbZEST9+aMqUXMw== X-Google-Smtp-Source: ABdhPJyWiPmoDmfNB/69cnZzb1pow0MLb9HlG5u3nWeZ3BQcVWVCVGvjpwbYHlDzicq2az5Z4j+MJxHFcFcVo9tRBT4= X-Received: by 2002:a5d:464b:: with SMTP id j11mr10707490wrs.356.1626241991022; Tue, 13 Jul 2021 22:53:11 -0700 (PDT) MIME-Version: 1.0 References: <20210618123851.1344518-1-anup.patel@wdc.com> <20210618123851.1344518-7-anup.patel@wdc.com> <20210712192207.GA2322460@robh.at.kernel.org> In-Reply-To: <20210712192207.GA2322460@robh.at.kernel.org> From: Anup Patel Date: Tue, 13 Jul 2021 20:57:43 +0530 Message-ID: Subject: Re: [RFC PATCH v2 06/11] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings To: Rob Herring Cc: Anup Patel , Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , DTML , Bin Meng Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 13, 2021 at 12:52 AM Rob Herring wrote: > > On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: > > We add DT bindings documentation for the ACLINT MSWI and SSWI > > devices found on RISC-V SOCs. > > > > Signed-off-by: Anup Patel > > Reviewed-by: Bin Meng > > --- > > .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > new file mode 100644 > > index 000000000000..b74025542866 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: RISC-V ACLINT Software Interrupt Devices > > + > > +maintainers: > > + - Anup Patel > > + > > +description: > > + RISC-V SOCs include an implementation of the M-level software interrupt > > + (MSWI) device and the S-level software interrupt (SSWI) device defined > > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. > > + > > + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT > > + specification located at > > + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > > + > > + The ACLINT MSWI and SSWI devices directly connect to the M-level and > > + S-level software interrupt lines of various HARTs (or CPUs) respectively > > + so the RISC-V per-HART (or per-CPU) local interrupt controller is the > > + parent interrupt controller for the ACLINT MSWI and SSWI devices. > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - riscv,aclint-mswi > > + - riscv,aclint-sswi > > + > > + description: > > + Should be ",-aclint-mswi" and "riscv,aclint-mswi" OR > > + ",-aclint-sswi" and "riscv,aclint-sswi". > > The schema doesn't match the description. > > There's no actual vendor implementation yet? You could do: > > items: > - {} > - const: riscv,aclint-mswi > > But then your example will fail. Is it okay to have optional vendor compatible string ? Vendors can add their specific compatible string if there is some special handling required. If there is not special handling required then the two compatible strings are enough. > > > + > > + reg: > > + maxItems: 1 > > + > > + "#interrupt-cells": > > + const: 0 > > + > > + interrupts-extended: > > + minItems: 1 > > You need maxItems too. I guess this based on number of cores, so just > pick a 'should be enough' value. There is a limit on the maximum number of connections between the device and HARTs or CPUs so this will be the maxItems over here. I will update this in the next patch revision. > > > + > > + interrupt-controller: true > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupts-extended > > + - interrupt-controller > > + - "#interrupt-cells" > > + > > +examples: > > + - | > > + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): > > + > > + interrupt-controller@2000000 { > > + compatible = "riscv,aclint-mswi"; > > + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; > > interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; Okay, will update. > > > + reg = <0x2000000 0x4000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + }; > > + > > + - | > > + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): > > + > > + interrupt-controller@2100000 { > > + compatible = "riscv,aclint-sswi"; > > + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; > > Same here. Okay, will update here as well. > > > + reg = <0x2100000 0x4000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + }; > > +... > > -- > > 2.25.1 > > > > Regards, Anup From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.4 required=3.0 tests=BAYES_00,DATE_IN_PAST_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61D96C07E9A for ; Wed, 14 Jul 2021 05:53:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12205613B6 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 13, 2021 at 12:52 AM Rob Herring wrote: > > On Fri, Jun 18, 2021 at 06:08:46PM +0530, Anup Patel wrote: > > We add DT bindings documentation for the ACLINT MSWI and SSWI > > devices found on RISC-V SOCs. > > > > Signed-off-by: Anup Patel > > Reviewed-by: Bin Meng > > --- > > .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > new file mode 100644 > > index 000000000000..b74025542866 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: RISC-V ACLINT Software Interrupt Devices > > + > > +maintainers: > > + - Anup Patel > > + > > +description: > > + RISC-V SOCs include an implementation of the M-level software interrupt > > + (MSWI) device and the S-level software interrupt (SSWI) device defined > > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. > > + > > + The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT > > + specification located at > > + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > > + > > + The ACLINT MSWI and SSWI devices directly connect to the M-level and > > + S-level software interrupt lines of various HARTs (or CPUs) respectively > > + so the RISC-V per-HART (or per-CPU) local interrupt controller is the > > + parent interrupt controller for the ACLINT MSWI and SSWI devices. > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - riscv,aclint-mswi > > + - riscv,aclint-sswi > > + > > + description: > > + Should be ",-aclint-mswi" and "riscv,aclint-mswi" OR > > + ",-aclint-sswi" and "riscv,aclint-sswi". > > The schema doesn't match the description. > > There's no actual vendor implementation yet? You could do: > > items: > - {} > - const: riscv,aclint-mswi > > But then your example will fail. Is it okay to have optional vendor compatible string ? Vendors can add their specific compatible string if there is some special handling required. If there is not special handling required then the two compatible strings are enough. > > > + > > + reg: > > + maxItems: 1 > > + > > + "#interrupt-cells": > > + const: 0 > > + > > + interrupts-extended: > > + minItems: 1 > > You need maxItems too. I guess this based on number of cores, so just > pick a 'should be enough' value. There is a limit on the maximum number of connections between the device and HARTs or CPUs so this will be the maxItems over here. I will update this in the next patch revision. > > > + > > + interrupt-controller: true > > + > > +additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - interrupts-extended > > + - interrupt-controller > > + - "#interrupt-cells" > > + > > +examples: > > + - | > > + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel): > > + > > + interrupt-controller@2000000 { > > + compatible = "riscv,aclint-mswi"; > > + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>; > > interrupts-extended = <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>; Okay, will update. > > > + reg = <0x2000000 0x4000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + }; > > + > > + - | > > + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel): > > + > > + interrupt-controller@2100000 { > > + compatible = "riscv,aclint-sswi"; > > + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>; > > Same here. Okay, will update here as well. > > > + reg = <0x2100000 0x4000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > + }; > > +... > > -- > > 2.25.1 > > > > Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv