From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0367BC433EF for ; Thu, 21 Oct 2021 17:07:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 90D7F615A7 for ; Thu, 21 Oct 2021 17:07:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 90D7F615A7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:44306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mdbXn-0005pQ-LT for qemu-devel@archiver.kernel.org; Thu, 21 Oct 2021 13:07:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56790) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbWR-00043N-KS for qemu-devel@nongnu.org; Thu, 21 Oct 2021 13:06:31 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:37873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdbWJ-0005Bs-Ip for qemu-devel@nongnu.org; Thu, 21 Oct 2021 13:06:30 -0400 Received: by mail-wm1-x32f.google.com with SMTP id g79-20020a1c2052000000b00323023159e1so432310wmg.2 for ; Thu, 21 Oct 2021 10:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tEGhx5P3FcpsCBX6IaldfqX9RQtIXBdFtyUSKwEgIPQ=; b=wi84dFsfa2KJZdXM1ZIgbSVV9JFNKXLRun5LkWmI3p3eLFZ1LI3G4qdVz0ejAK2Mf4 x1beFqehB8OIjG5vd1nPIJVaXfTUiKH/yvcoMKy4b/qu1XRudBzUv69/SCUERo8Ykrqz gVXpNbLQqUMs68Z1ZT1jpqr1OHCogkutGyncbgVPR1TJcxqvGQFIldspIDd4NyUdidVp krql+V8voXNe1ka/nyZUxYcayZNkP7cTf1vGnkSuBdZGaO5kW0wPVQc08+ZeH05VsfUT ICOqrIVKo5mIicLiNum+dIGMVwytU4ks3D8QcJgTNKGm7dCSnduQ8oVMmaWagLns2woQ s73A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tEGhx5P3FcpsCBX6IaldfqX9RQtIXBdFtyUSKwEgIPQ=; b=IsMZIidGpvN9nupMFSYJZzbmaGX+jRd8IaxBW8qoXyJ10pMGOZtah7CJLAcmjVDTKi loCSmijFjOq6BV8FNFRsR/w3/l7ATt07qkX6nuCbe/2jIh2y/N6gNMPn92xqTJNn7Y1n 4x804foAI+9kfLC5L031qH4H9T3QjNxhw/C+X2G1HZpxbPRNv7A7Dnf5ZTr37C9ecRIJ FdmC5IjBHTbjcmiOozu/lwmmP5wDmMqA6h14LnqsI2F9/CwLvGfeRSMZG1k1Bm/isVVk XQZbtBnTHsUEJFYU/AtimIWArXhlxCfeBEPFOGKzJTqKRZdWjKxGuBF8YOjWrFw2v6hT zr8A== X-Gm-Message-State: AOAM53259E1J3/r8gd9BgX2xA/YzvTii5BMAeZvEzeTw8PdWGSkPDJh0 JyrAs6DC0FKr6ZVdsTZjR/gTsBRLsURLFIiBChvMBA== X-Google-Smtp-Source: ABdhPJw1tvqSTLGhSFTfRea8Wuwo+wjgf9id9lEqBd77jlyX+Fq7eczxDL8GHlyNYamcUD+q3Zw3D3pO7z87FFquRnI= X-Received: by 2002:a7b:c742:: with SMTP id w2mr8178932wmk.61.1634835980038; Thu, 21 Oct 2021 10:06:20 -0700 (PDT) MIME-Version: 1.0 References: <20210902112520.475901-1-anup.patel@wdc.com> <20210902112520.475901-6-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Thu, 21 Oct 2021 22:36:08 +0530 Message-ID: Subject: Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation To: Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::32f; envelope-from=anup@brainfault.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, Sep 4, 2021 at 8:42 PM Bin Meng wrote: > > On Thu, Sep 2, 2021 at 7:42 PM Anup Patel wrote: > > > > The machine or device emulation should be able to force set certain > > CPU features because: > > 1) We can have certain CPU features which are in-general optional > > but implemented by RISC-V CPUs on machine. > > on the machine > > > 2) We can have devices which require certain CPU feature. For example, > > a certain > > > AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. > > expect Okay, I will update the commit description based on the above comments. Regards, Anup > > > > > Signed-off-by: Anup Patel > > --- > > target/riscv/cpu.c | 11 +++-------- > > target/riscv/cpu.h | 5 +++++ > > 2 files changed, 8 insertions(+), 8 deletions(-) > > > > Otherwise, > Reviewed-by: Bin Meng From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mdbWX-00044Z-0y for mharc-qemu-riscv@gnu.org; Thu, 21 Oct 2021 13:06:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mdbWP-000434-1X for qemu-riscv@nongnu.org; Thu, 21 Oct 2021 13:06:30 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:36511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mdbWJ-0005Br-5f for qemu-riscv@nongnu.org; Thu, 21 Oct 2021 13:06:28 -0400 Received: by mail-wm1-x335.google.com with SMTP id z11-20020a1c7e0b000000b0030db7b70b6bso436827wmc.1 for ; Thu, 21 Oct 2021 10:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tEGhx5P3FcpsCBX6IaldfqX9RQtIXBdFtyUSKwEgIPQ=; b=wi84dFsfa2KJZdXM1ZIgbSVV9JFNKXLRun5LkWmI3p3eLFZ1LI3G4qdVz0ejAK2Mf4 x1beFqehB8OIjG5vd1nPIJVaXfTUiKH/yvcoMKy4b/qu1XRudBzUv69/SCUERo8Ykrqz gVXpNbLQqUMs68Z1ZT1jpqr1OHCogkutGyncbgVPR1TJcxqvGQFIldspIDd4NyUdidVp krql+V8voXNe1ka/nyZUxYcayZNkP7cTf1vGnkSuBdZGaO5kW0wPVQc08+ZeH05VsfUT ICOqrIVKo5mIicLiNum+dIGMVwytU4ks3D8QcJgTNKGm7dCSnduQ8oVMmaWagLns2woQ s73A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tEGhx5P3FcpsCBX6IaldfqX9RQtIXBdFtyUSKwEgIPQ=; b=F0cOZ2wBiXBtd3tSryrtVlME4fSXy+C2yBAgVoDdGhkbyekv3IAbHJaUZ2IQs4I2M5 Gp98G2U78Jwmf+TAw7k2htqERW9k/4G+R1amCMaJ2jvcbIr1kPJTim2/O1MaJcvNZqPS X+l8GByvxfvFmIQoOl27R9eXvHSs0HHSVg6oEkgVhQDP/mdykMsDpYRbHBoqDJNW4zlc 7wBG02lFa4yyWysCDNktkGt+LY61mTWOpUroqmSxLKo7v2CFBo5NVQ1zqHJSHRv1Yn6m Q+3oX1W8n32aIYoNDaICC86fqZdlItO2+oTBF4+/7uF1GgHFSfcfE+6C510/VT1ds4F3 Saqg== X-Gm-Message-State: AOAM531IqzShMowpshmMd7bCjkhiqnh7hy4aW9IfSPf8K4fJEJ6StLNr IpRlpVb4eQBmuD3fIYNkPNTRt6DAaOJ6hb6ht7sWWw== X-Google-Smtp-Source: ABdhPJw1tvqSTLGhSFTfRea8Wuwo+wjgf9id9lEqBd77jlyX+Fq7eczxDL8GHlyNYamcUD+q3Zw3D3pO7z87FFquRnI= X-Received: by 2002:a7b:c742:: with SMTP id w2mr8178932wmk.61.1634835980038; Thu, 21 Oct 2021 10:06:20 -0700 (PDT) MIME-Version: 1.0 References: <20210902112520.475901-1-anup.patel@wdc.com> <20210902112520.475901-6-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Thu, 21 Oct 2021 22:36:08 +0530 Message-ID: Subject: Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation To: Bin Meng Cc: Anup Patel , Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::335; envelope-from=anup@brainfault.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 17:06:32 -0000 On Sat, Sep 4, 2021 at 8:42 PM Bin Meng wrote: > > On Thu, Sep 2, 2021 at 7:42 PM Anup Patel wrote: > > > > The machine or device emulation should be able to force set certain > > CPU features because: > > 1) We can have certain CPU features which are in-general optional > > but implemented by RISC-V CPUs on machine. > > on the machine > > > 2) We can have devices which require certain CPU feature. For example, > > a certain > > > AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs. > > expect Okay, I will update the commit description based on the above comments. Regards, Anup > > > > > Signed-off-by: Anup Patel > > --- > > target/riscv/cpu.c | 11 +++-------- > > target/riscv/cpu.h | 5 +++++ > > 2 files changed, 8 insertions(+), 8 deletions(-) > > > > Otherwise, > Reviewed-by: Bin Meng