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Sat, 01 Jan 2022 05:19:49 -0800 (PST) MIME-Version: 1.0 References: <20211231080923.24252-1-liweiwei@iscas.ac.cn> <20211231080923.24252-4-liweiwei@iscas.ac.cn> In-Reply-To: <20211231080923.24252-4-liweiwei@iscas.ac.cn> From: Anup Patel Date: Sat, 1 Jan 2022 18:49:38 +0530 Message-ID: Subject: Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension To: Weiwei Li Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::330 (failed) Received-SPF: none client-ip=2a00:1450:4864:20::330; envelope-from=anup@brainfault.org; helo=mail-wm1-x330.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , "open list:RISC-V" , wangjunqiang@iscas.ac.cn, Bin Meng , QEMU Developers , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote: > > It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_helper.c | 9 ++++++++- > 4 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 77ef0f85fe..743bcfe297 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false), Drop the "x-" prefix, same as the other two patches. The Svpmbt extension is also ratified. Regards, Anup > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5dd9e53293..6656b8a4f3 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -317,6 +317,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_svinval; > bool ext_svnapot; > + bool ext_svpbmt; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1156c941cb..3dae358aa5 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -483,7 +483,10 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ > +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ > #define PTE_N 0x8000000000000000 /* NAPOT translation */ > +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e044153986..41d04675b3 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,16 +619,23 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; > > RISCVCPU *cpu = env_archcpu(env); > if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > return TRANSLATE_FAIL; > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } else if (pte & PTE_RSVD) { > + return TRANSLATE_FAIL; > } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } > base = ppn << PGSHIFT; > } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { > /* Reserved leaf PTE flags: PTE_W */ > -- > 2.17.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1n3eIf-0005Ft-RJ for mharc-qemu-riscv@gnu.org; Sat, 01 Jan 2022 08:19:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n3eIa-0005FS-Kh for qemu-riscv@nongnu.org; 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charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::336 (failed) Received-SPF: none client-ip=2a00:1450:4864:20::336; envelope-from=anup@brainfault.org; helo=mail-wm1-x336.google.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Jan 2022 13:19:56 -0000 On Fri, Dec 31, 2021 at 1:40 PM Weiwei Li wrote: > > It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Tested-by: Heiko Stuebner > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_helper.c | 9 ++++++++- > 4 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 77ef0f85fe..743bcfe297 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -649,6 +649,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > DEFINE_PROP_BOOL("x-svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("x-svnapot", RISCVCPU, cfg.ext_svnapot, false), > + DEFINE_PROP_BOOL("x-svpbmt", RISCVCPU, cfg.ext_svpbmt, false), Drop the "x-" prefix, same as the other two patches. The Svpmbt extension is also ratified. Regards, Anup > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5dd9e53293..6656b8a4f3 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -317,6 +317,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_svinval; > bool ext_svnapot; > + bool ext_svpbmt; > bool ext_zfh; > bool ext_zfhmin; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1156c941cb..3dae358aa5 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -483,7 +483,10 @@ typedef enum { > #define PTE_A 0x040 /* Accessed */ > #define PTE_D 0x080 /* Dirty */ > #define PTE_SOFT 0x300 /* Reserved for Software */ > +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ > +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ > #define PTE_N 0x8000000000000000 /* NAPOT translation */ > +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ > > /* Page table PPN shift amount */ > #define PTE_PPN_SHIFT 10 > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e044153986..41d04675b3 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -619,16 +619,23 @@ restart: > return TRANSLATE_FAIL; > } > > - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; > + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; > > RISCVCPU *cpu = env_archcpu(env); > if (!cpu->cfg.ext_svnapot && (pte & PTE_N)) { > return TRANSLATE_FAIL; > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } else if (pte & PTE_RSVD) { > + return TRANSLATE_FAIL; > } else if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { > + return TRANSLATE_FAIL; > + } > base = ppn << PGSHIFT; > } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { > /* Reserved leaf PTE flags: PTE_W */ > -- > 2.17.1 > >