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Mon, 12 Jul 2021 08:02:59 -0700 (PDT) MIME-Version: 1.0 References: <20210612160615.330768-1-anup.patel@wdc.com> <20210612160615.330768-4-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Mon, 12 Jul 2021 20:32:48 +0530 Message-ID: Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine To: Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::433; envelope-from=anup@brainfault.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:RISC-V" , Sagar Karandikar , Anup Patel , "qemu-devel@nongnu.org Developers" , Atish Patra , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jul 12, 2021 at 6:41 PM Bin Meng wrote: > > On Mon, Jul 12, 2021 at 6:54 PM Anup Patel wrote: > > > > On Mon, Jul 12, 2021 at 11:45 AM Bin Meng wrote: > > > > > > On Mon, Jul 12, 2021 at 1:39 PM Anup Patel wrote: > > > > > > > > On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > > > > > > > > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel wrote: > > > > > > > > > > > > We extend virt machine to emulate ACLINT devices only when "aclint=on" > > > > > > parameter is passed along with machine name in QEMU command-line. > > > > > > > > > > > > Signed-off-by: Anup Patel > > > > > > --- > > > > > > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++- > > > > > > include/hw/riscv/virt.h | 2 + > > > > > > 2 files changed, 111 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > > > > > index 977d699753..a35f66af13 100644 > > > > > > --- a/hw/riscv/virt.c > > > > > > +++ b/hw/riscv/virt.c > > > > > > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = { > > > > > > [VIRT_TEST] = { 0x100000, 0x1000 }, > > > > > > [VIRT_RTC] = { 0x101000, 0x1000 }, > > > > > > [VIRT_CLINT] = { 0x2000000, 0x10000 }, > > > > > > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, > > > > > > > > > > How about we reuse the same register space to support both CLINT and > > > > > ACLINT? This saves some register space for future extension. > > > > > > > > The intention of placing ACLINT SSWI separate from ACLINT MTIMER and > > > > MSWI is to minimize PMP region usage. > > > > > > Okay, so this leaves spaces for 240 ACLINT MTIMER and MSWI devices in > > > total, if we put ACLINT SSWI at 0x2F00000, and we still have spaces > > > for 64 ACLINT SSWI devices. Is this enough? > > > > We just need one instance of MTIMER, MSWI, and SSWI per-socket. > > Current limit of max sockets in RISC-V virt machine is 8. We will be > > reducing this to 4 due space required by IMSICs. This means no matter > > what 8 instances of each MTIMER, MSWI, and SSWI is the max we > > can go for RISC-V virt machine. This limits are due to the fact that > > we want to fit devices in first 2GB space. > > > > Can you list the maximum ACLINT devices and their memory map we intend > to support and with that we can see how many PMP is used? For 4 sockets, we will have following layout: 0x2000000-0x200FFFF (Socket0 MTIMER and MSWI) 0x2010000-0x201FFFF (Socket1 MTIMER and MSWI) 0x2020000-0x202FFFF (Socket2 MTIMER and MSWI) 0x2030000-0x203FFFF (Socket3 MTIMER and MSWI) 0x2F00000-0x2F03FFF (Socket0 SSWI) 0x2F04000-0x2F07FFF (Socket1 SSWI) 0x2F08000-0x2F0bFFF (Socket2 SSWI) 0x2F0C000-0x2F0FFFF (Socket3 SSWI) OpenSBI will create one PMP region to protect all MTIMERs and MSWIs which is: 0x2000000-0x203FFFF Regards, Anup > > Regards, > Bin From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1m2xSc-0003ZV-3k for mharc-qemu-riscv@gnu.org; Mon, 12 Jul 2021 11:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51254) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m2xSa-0003UJ-0c for qemu-riscv@nongnu.org; Mon, 12 Jul 2021 11:03:04 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:40542) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m2xSX-0007MH-Oj for qemu-riscv@nongnu.org; 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Mon, 12 Jul 2021 08:02:59 -0700 (PDT) MIME-Version: 1.0 References: <20210612160615.330768-1-anup.patel@wdc.com> <20210612160615.330768-4-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Mon, 12 Jul 2021 20:32:48 +0530 Message-ID: Subject: Re: [PATCH v1 3/3] hw/riscv: virt: Add optional ACLINT support to virt machine To: Bin Meng Cc: Anup Patel , Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::42b; envelope-from=anup@brainfault.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Jul 2021 15:03:04 -0000 On Mon, Jul 12, 2021 at 6:41 PM Bin Meng wrote: > > On Mon, Jul 12, 2021 at 6:54 PM Anup Patel wrote: > > > > On Mon, Jul 12, 2021 at 11:45 AM Bin Meng wrote: > > > > > > On Mon, Jul 12, 2021 at 1:39 PM Anup Patel wrote: > > > > > > > > On Mon, Jun 14, 2021 at 5:52 PM Bin Meng wrote: > > > > > > > > > > On Sun, Jun 13, 2021 at 12:14 AM Anup Patel wrote: > > > > > > > > > > > > We extend virt machine to emulate ACLINT devices only when "aclint=on" > > > > > > parameter is passed along with machine name in QEMU command-line. > > > > > > > > > > > > Signed-off-by: Anup Patel > > > > > > --- > > > > > > hw/riscv/virt.c | 110 +++++++++++++++++++++++++++++++++++++++- > > > > > > include/hw/riscv/virt.h | 2 + > > > > > > 2 files changed, 111 insertions(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > > > > > index 977d699753..a35f66af13 100644 > > > > > > --- a/hw/riscv/virt.c > > > > > > +++ b/hw/riscv/virt.c > > > > > > @@ -50,6 +50,7 @@ static const MemMapEntry virt_memmap[] = { > > > > > > [VIRT_TEST] = { 0x100000, 0x1000 }, > > > > > > [VIRT_RTC] = { 0x101000, 0x1000 }, > > > > > > [VIRT_CLINT] = { 0x2000000, 0x10000 }, > > > > > > + [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, > > > > > > > > > > How about we reuse the same register space to support both CLINT and > > > > > ACLINT? This saves some register space for future extension. > > > > > > > > The intention of placing ACLINT SSWI separate from ACLINT MTIMER and > > > > MSWI is to minimize PMP region usage. > > > > > > Okay, so this leaves spaces for 240 ACLINT MTIMER and MSWI devices in > > > total, if we put ACLINT SSWI at 0x2F00000, and we still have spaces > > > for 64 ACLINT SSWI devices. Is this enough? > > > > We just need one instance of MTIMER, MSWI, and SSWI per-socket. > > Current limit of max sockets in RISC-V virt machine is 8. We will be > > reducing this to 4 due space required by IMSICs. This means no matter > > what 8 instances of each MTIMER, MSWI, and SSWI is the max we > > can go for RISC-V virt machine. This limits are due to the fact that > > we want to fit devices in first 2GB space. > > > > Can you list the maximum ACLINT devices and their memory map we intend > to support and with that we can see how many PMP is used? For 4 sockets, we will have following layout: 0x2000000-0x200FFFF (Socket0 MTIMER and MSWI) 0x2010000-0x201FFFF (Socket1 MTIMER and MSWI) 0x2020000-0x202FFFF (Socket2 MTIMER and MSWI) 0x2030000-0x203FFFF (Socket3 MTIMER and MSWI) 0x2F00000-0x2F03FFF (Socket0 SSWI) 0x2F04000-0x2F07FFF (Socket1 SSWI) 0x2F08000-0x2F0bFFF (Socket2 SSWI) 0x2F0C000-0x2F0FFFF (Socket3 SSWI) OpenSBI will create one PMP region to protect all MTIMERs and MSWIs which is: 0x2000000-0x203FFFF Regards, Anup > > Regards, > Bin