From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD601C433EF for ; Wed, 20 Oct 2021 16:19:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC92361374 for ; Wed, 20 Oct 2021 16:19:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231236AbhJTQVY (ORCPT ); Wed, 20 Oct 2021 12:21:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231134AbhJTQVH (ORCPT ); Wed, 20 Oct 2021 12:21:07 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C571CC06161C for ; Wed, 20 Oct 2021 09:18:49 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id s198-20020a1ca9cf000000b0030d6986ea9fso11492007wme.1 for ; Wed, 20 Oct 2021 09:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=RpDaphKaULN4/89C8L4bD1DcIqBybhRsQBUxIBBeNZg=; b=kUprcAR2htHrBKfjlDZ75+0TfgTGJ7mUB2W2QoT1ebBXuZD6CgaBOHQ0sskcNqyspB Ce+zCkoQFhHtOwwsxQ/jWh91yCUs2nHQfdFUsX54h+heArdNsQ1Wi1ldGyoC3/L0IHpb /GwAowqyK7TbukDad86HgttnmD+4wS91cVvUsf9gplFAeUCzC0Yom30tl6QRAX6wGULq 0O/SjmaEXWNmktVuNeSyXNmT5n4QuKYGlIgjY+F5Qqm7YJA0W1Z4xBwXdQjXdB7fSCRR ZdAl8702GCr07s39QjoOwUmNmHduGyLNBH7hD9GF4YzhvkS3imn038m5AeEXmW3ZWLeH b7cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=RpDaphKaULN4/89C8L4bD1DcIqBybhRsQBUxIBBeNZg=; b=0+dUBjQFsW5dpBNx7QS0DvQm8MX7I9T032I+GzgAeEWriF9RSAKHf4iNsEN8w3KieI E0tl+gie+LpVBorZjVkQHImMAfq7oQPCm9j+ly7a1YQT7CfmJcdVGhfFGyzKyUEmTn7v 9LKFic6pgGl0tk1qONZ23J2D6cRBGrShJVlliexxY029cn6604j12vLV5F1Jf7CKgEJh RRAo/obEzWHy3USufdj3R2mo95O6PiRVYJH1YA19KkDgHlA7sg+K9PMDcFV7bI2cep8a mG0HpdH7mr3uM00brl5FzdKweWWR3GPqxp64uKGOupB6/O18kX2VTMJSGG0BO8Qn+xM5 AVkw== X-Gm-Message-State: AOAM530tgRxUqN7ddJe9CMPiHHnRs986nv4Y+98lrqve2BOLDa2CwrLd El01Ihd/UH07QzybUM20mBc2v+3gkK4JkPxKmtlcng== X-Google-Smtp-Source: ABdhPJwLBRyQtWG7x7CWXuH1W3s6K3jBd6D+Z46Mv0MN16GIwgS2GF3/OsPoN2Fr1EXpMi48GJkBydY5lP97XUbFXC0= X-Received: by 2002:a5d:5849:: with SMTP id i9mr167911wrf.331.1634746728173; Wed, 20 Oct 2021 09:18:48 -0700 (PDT) MIME-Version: 1.0 References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> <875ytrddma.wl-maz@kernel.org> In-Reply-To: From: Anup Patel Date: Wed, 20 Oct 2021 21:48:36 +0530 Message-ID: Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support To: Guo Ren , Marc Zyngier , Samuel Holland , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 20, 2021 at 8:29 PM Darius Rad wrote: > > On Wed, Oct 20, 2021 at 10:19:06PM +0800, Guo Ren wrote: > > On Wed, Oct 20, 2021 at 9:34 PM Marc Zyngier wrote: > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > Guo Ren wrote: > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > Guo Ren wrote: > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > breaks > > > > > > > the HW interrupt state or not. > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > continues irqs could come in. > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > handled? How great... > > > > If the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the completion is silently ignored. > > > > So, C9xx completion depends on enable-bit. > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > can understand that one implementation would be broken, but if the > > > PLIC architecture itself is broken, that's far more concerning. > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > The PLIC signals it has completed executing an interrupt handler by > > writing the interrupt ID it received from the claim to the claim/complete > > register. The PLIC does not check whether the completion ID is the same > > as the last claim ID for that target. If the completion ID does not match > > an interrupt source that is currently enabled for the target, the > > ^^ ^^^^^^^^^ ^^^^^^^ > > completion is silently ignored. > > > > [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > Did we misunderstand the PLIC spec? > > > > That clause sounds to me like it is due to the SiFive implementation, which > the RISC-V PLIC specification is based on. Since the PLIC spec is still a > draft I would expect it to change before release. The SiFive PLIC has been adopted by various RISC-V platforms (including SiFive themselves). Almost all existing RISC-V boards have PLIC as the interrupt controller. Considering the wide usage of PLIC across existing platforms, the RISC-V International has adopted it as an official RISC-V non-ISA spec. Of course, the RISC-V PLIC spec needs to follow the process for RISC-V non-ISA spec but changing the RISC-V PLIC spec now would mean all existing RISC-V platforms will become non-compliant. The RISC-V AIA spec is intended to replace the RISC-V PLIC spec as the new interrupt controller spec for future RISC-V platforms. Regards, Anup From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93607C433EF for ; Wed, 20 Oct 2021 16:19:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49293611B0 for ; Wed, 20 Oct 2021 16:19:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 49293611B0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Cc:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; 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Wed, 20 Oct 2021 09:18:48 -0700 (PDT) MIME-Version: 1.0 References: <20211016032200.2869998-1-guoren@kernel.org> <20211016032200.2869998-2-guoren@kernel.org> <8be1bdbd-365d-cd28-79d7-b924908f9e39@sholland.org> <8735oxuxlq.wl-maz@kernel.org> <875ytrddma.wl-maz@kernel.org> In-Reply-To: From: Anup Patel Date: Wed, 20 Oct 2021 21:48:36 +0530 Message-ID: Subject: Re: [PATCH V4 1/3] irqchip/sifive-plic: Add thead,c900-plic support To: Guo Ren , Marc Zyngier , Samuel Holland , Anup Patel , Atish Patra , Thomas Gleixner , Palmer Dabbelt , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Rob Herring , Linux Kernel Mailing List , linux-riscv , Guo Ren X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_091851_860616_25652542 X-CRM114-Status: GOOD ( 30.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Oct 20, 2021 at 8:29 PM Darius Rad wrote: > > On Wed, Oct 20, 2021 at 10:19:06PM +0800, Guo Ren wrote: > > On Wed, Oct 20, 2021 at 9:34 PM Marc Zyngier wrote: > > > > > > On Tue, 19 Oct 2021 14:27:02 +0100, > > > Guo Ren wrote: > > > > > > > > On Tue, Oct 19, 2021 at 6:18 PM Marc Zyngier wrote: > > > > > > > > > > On Tue, 19 Oct 2021 10:33:49 +0100, > > > > > Guo Ren wrote: > > > > > > > > > > > > If you have an 'automask' behavior and yet the HW doesn't record this > > > > > > > in a separate bit, then you need to track this by yourself in the > > > > > > > irq_eoi() callback instead. I guess that you would skip the write to > > > > > > > the CLAIM register in this case, though I have no idea whether this > > > > > > > breaks > > > > > > > the HW interrupt state or not. > > > > > > The problem is when enable bit is 0 for that irq_number, > > > > > > "writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM)" wouldn't affect > > > > > > the hw state machine. Then this irq would enter in ack state and no > > > > > > continues irqs could come in. > > > > > > > > > > Really? This means that you cannot mask an interrupt while it is being > > > > > handled? How great... > > > > If the completion ID does not match an interrupt source that is > > > > currently enabled for the target, the completion is silently ignored. > > > > So, C9xx completion depends on enable-bit. > > > > > > Is that what the PLIC spec says? Or what your implementation does? I > > > can understand that one implementation would be broken, but if the > > > PLIC architecture itself is broken, that's far more concerning. > > > > Here is the description of Interrupt Completion in PLIC spec [1]: > > > > The PLIC signals it has completed executing an interrupt handler by > > writing the interrupt ID it received from the claim to the claim/complete > > register. The PLIC does not check whether the completion ID is the same > > as the last claim ID for that target. If the completion ID does not match > > an interrupt source that is currently enabled for the target, the > > ^^ ^^^^^^^^^ ^^^^^^^ > > completion is silently ignored. > > > > [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc > > > > Did we misunderstand the PLIC spec? > > > > That clause sounds to me like it is due to the SiFive implementation, which > the RISC-V PLIC specification is based on. Since the PLIC spec is still a > draft I would expect it to change before release. The SiFive PLIC has been adopted by various RISC-V platforms (including SiFive themselves). Almost all existing RISC-V boards have PLIC as the interrupt controller. Considering the wide usage of PLIC across existing platforms, the RISC-V International has adopted it as an official RISC-V non-ISA spec. Of course, the RISC-V PLIC spec needs to follow the process for RISC-V non-ISA spec but changing the RISC-V PLIC spec now would mean all existing RISC-V platforms will become non-compliant. The RISC-V AIA spec is intended to replace the RISC-V PLIC spec as the new interrupt controller spec for future RISC-V platforms. Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv