From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E7DC433FE for ; Tue, 24 May 2022 11:25:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236605AbiEXLZj (ORCPT ); Tue, 24 May 2022 07:25:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236366AbiEXLZi (ORCPT ); Tue, 24 May 2022 07:25:38 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77B997A45B for ; Tue, 24 May 2022 04:25:36 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id z15so1417303wrg.11 for ; Tue, 24 May 2022 04:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IrQKUMgGfJCg4Qp/wyG56UieXV8r90cWTrXiOz7LDck=; b=Gy4q7CN99HFyXAicqG9X11IlQ+svRqwnN8b26/bIiFUYInmpSeZdUBS3liSbUIVsla wWqnBTLpRQPJXp79wdo0TnrKGBjeXoH4SAS6hOlROajnfLUnMxqS9d1aBvJMrZpmBlmU 3w5uSFppAXGa1yK8Vd3H9oCbvZcA3UMQD1EBvSxo0HYq1UPQ92+AbDrlGLPE8klvrRTs D0PRsfDlXTkRrjxnorF72umS/EPsYzL5y1oK0SJLDG+nwR3peuR7Rzkpfm12leFAYxpX clNf3Yy0i28wX0quPqA3glr021cdnZGGrEnVORu8zgPSuMm/hbUSHkuiQJqq1MJNgfSh 1N/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IrQKUMgGfJCg4Qp/wyG56UieXV8r90cWTrXiOz7LDck=; b=qMUM5aOdsyLSNm2nHAY+h65daPfMd1HiSv66QHOGv6NzmWhahuDEjY0D588dKLHDb1 OBqZZ5E65voSGj9kzQPhPl8cTDE3C/FQFNiWi7Z9mcogx3dGfJuLGRgrAfN6tiLiQb/B kDuGx0FOEWztlow/cVu79vdfb3Rtr6m1Wx8nHhI4NuF7bYKR87nOeLrmrM0YtsI9lHEY DbSTdwgPhfdJ9dooQaDLnbVmwiL9OlISLgPGqZZoOZiE2hfUbbAEjFdq9F36cFlEejQY gdEbgHtr5s91aG1KdETS376XMoVEKWdJcNYUb7C4wPTacYJkDu9ETi4RmihR4Tr+rQet ZQ2w== X-Gm-Message-State: AOAM531ofLD8li0u5r9xvr45NdKOO1f19/s6k9RA0lYBaQbXx83Q2ln9 91qoA1lB4QpLjtlmCUgn5DIRNkTPWVMcpEdxEWMZChMCjhN+UWOD X-Google-Smtp-Source: ABdhPJxSztbMN+n2TmP0z6nr9DurWwl3+BCxash8ct2jbn4OvYv+CLh96rMCl3y/TYL6GZCHByl5uXayneQiJM2qHqo= X-Received: by 2002:a05:6000:1f18:b0:20f:e61b:520e with SMTP id bv24-20020a0560001f1800b0020fe61b520emr6372906wrb.214.1653391534839; Tue, 24 May 2022 04:25:34 -0700 (PDT) MIME-Version: 1.0 References: <20220426185245.281182-1-atishp@rivosinc.com> <20220426185245.281182-3-atishp@rivosinc.com> In-Reply-To: <20220426185245.281182-3-atishp@rivosinc.com> From: Anup Patel Date: Tue, 24 May 2022 16:55:23 +0530 Message-ID: Subject: Re: [PATCH v3 2/4] RISC-V: Enable sstc extension parsing from DT To: Atish Patra Cc: "linux-kernel@vger.kernel.org List" , Atish Patra , Damien Le Moal , DTML , Jisheng Zhang , Krzysztof Kozlowski , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 27, 2022 at 12:23 AM Atish Patra wrote: > > The ISA extension framework now allows parsing any multi-letter > ISA extension. > > Enable that for sstc extension. > > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..25915eb60d61 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_SSTC, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..ca0e4c0db17e 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..a214537c22f1 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); > } > #undef SET_ISA_EXT_MAP > } > -- > 2.25.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39863C433F5 for ; Tue, 24 May 2022 11:25:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Tue, 24 May 2022 04:25:34 -0700 (PDT) MIME-Version: 1.0 References: <20220426185245.281182-1-atishp@rivosinc.com> <20220426185245.281182-3-atishp@rivosinc.com> In-Reply-To: <20220426185245.281182-3-atishp@rivosinc.com> From: Anup Patel Date: Tue, 24 May 2022 16:55:23 +0530 Message-ID: Subject: Re: [PATCH v3 2/4] RISC-V: Enable sstc extension parsing from DT To: Atish Patra Cc: "linux-kernel@vger.kernel.org List" , Atish Patra , Damien Le Moal , DTML , Jisheng Zhang , Krzysztof Kozlowski , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220524_042538_530886_A02001D8 X-CRM114-Status: GOOD ( 15.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 27, 2022 at 12:23 AM Atish Patra wrote: > > The ISA extension framework now allows parsing any multi-letter > ISA extension. > > Enable that for sstc extension. > > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel Regards, Anup > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..25915eb60d61 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_SSTC, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..ca0e4c0db17e 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..a214537c22f1 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); > } > #undef SET_ISA_EXT_MAP > } > -- > 2.25.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv