From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F2EAC4320A for ; Wed, 1 Sep 2021 12:00:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 62F9860F6C for ; Wed, 1 Sep 2021 12:00:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243954AbhIAMBv (ORCPT ); Wed, 1 Sep 2021 08:01:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243940AbhIAMBt (ORCPT ); Wed, 1 Sep 2021 08:01:49 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62F92C061575 for ; Wed, 1 Sep 2021 05:00:52 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id m9so4162010wrb.1 for ; Wed, 01 Sep 2021 05:00:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=JK6kRJSrXbJA7J85nnMO2GVwwyHjBoelMGPJ1c1OWrk=; b=ZCn9pLdXZLA751P/mQGlLXsZjVe4HZrnDMooJMGXQhVpxiD8UJcNUeedtaooMEqpM5 KyuMjLonZTG9wnLFv4lNz2x+Ftrf71FWsgp0o09hjxwD/CnOB4AyVQnQkxcuXQWd8NNP +TEr5FWy33aQtyc0obV6TmvlWGzvA7R2hDMABmsLT7UTnfxvQTVxMb7uFsy+6P9MAIf5 /0U+Tq4tl5y4+vy6SbfkSkEydgV1tAxVvM95cBf0IWaJmcot3eX/vqq0dxDz8fLe5VWo mCOU+BEqmE8VNfp6xxaJQMa0QawFgzrlbX7xStMDEwJlJ6l8aqNyjmYsFBzYkUTy6uWe xS3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=JK6kRJSrXbJA7J85nnMO2GVwwyHjBoelMGPJ1c1OWrk=; b=V7Dxa2hnsIPPXDUDqpzx8naFpasxnA66JDPab74bxtG9UV4HjSSqIvCzCrY9fIYh9D jxXRnegFfXSXMBdzQGKwKg2cl51F6mjBUCrRZyDE7T/csqIvYOEIPGnm+nt/qAhS3wdf HAbh6MhQSR0sPac7BpPHvomT/S/L3gSCvZRYVOsoCRywBxIkoeZ70f/RENkVecd/sPEn gdVYRcRgnBSZZyCvqREo6CJbE0OJBOJHnmFyF/cwSZG5iThTJ2bTrwWhi/DitpMeqixp wa7K4/kvt/hVODTzeaJ98ZyR1u7X49tbZ0CfRFZ/VubIWOpb/hm/TjPB6MIb/8bcOv6t SpwQ== X-Gm-Message-State: AOAM532pVq1v/2HvuQqLhP5vFB4VBP+XSqa1OWpNKvuJFD36cizT4HLm 5wB1Iixfd5rKZUmxSQaBCyqe53OiKMWk8cwNtZyaWg== X-Google-Smtp-Source: ABdhPJzmsR8+8INzT7ymkKlmM911UHAjY59ObO0CD+XE3R1hrukQBpEZvSaHQ1OOD8lRWX/r1F5ousC00VLyv+Z4jEQ= X-Received: by 2002:a5d:464f:: with SMTP id j15mr37728462wrs.325.1630497650858; Wed, 01 Sep 2021 05:00:50 -0700 (PDT) MIME-Version: 1.0 References: <20210830041729.237252-1-anup.patel@wdc.com> <20210830041729.237252-7-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Wed, 1 Sep 2021 17:30:39 +0530 Message-ID: Subject: Re: [RFC PATCH v3 06/11] dt-bindings: timer: Update SiFive CLINT bindings for IPI support To: Rob Herring Cc: Anup Patel , Palmer Dabbelt , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , DTML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 1, 2021 at 6:59 AM Rob Herring wrote: > > On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote: > > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means > > we have to create a IPI interrupt domain to use CLINT IPI functionality > > hence requiring a "interrupt-controller" and "#interrupt-cells" DT > > property in CLINT DT nodes. > > > > Impact of this CLINT DT bindings change only affects Linux RISC-V > > NoMMU kernel and has no effect of existing M-mode runtime firmwares > > (i.e. OpenSBI). > > It appears to me you should fix Linux to not need these 2 useless > properties. I say useless because #interrupt-cells being 0 is pretty > useless. Linux IRQCHIP framework only probes IRQCHIP DT nodes which have "interrupt-controller" DT property. The "interrupt-cells" DT property can be removed because as an interrupt controller SiFive CLINT will only provide IPIs to arch code. Regards, Anup > > > > > Signed-off-by: Anup Patel > > --- > > .../bindings/timer/sifive,clint.yaml | 20 ++++++++++++++----- > > arch/riscv/boot/dts/canaan/k210.dtsi | 2 ++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 2 ++ > > 3 files changed, 19 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > index a35952f48742..9c8ef9f4094f 100644 > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -43,6 +43,12 @@ properties: > > > > interrupts-extended: > > minItems: 1 > > + maxItems: 4095 > > + > > + "#interrupt-cells": > > + const: 0 > > + > > + interrupt-controller: true > > > > additionalProperties: false > > > > @@ -50,15 +56,19 @@ required: > > - compatible > > - reg > > - interrupts-extended > > + - interrupt-controller > > + - "#interrupt-cells" > > > > examples: > > - | > > timer@2000000 { > > compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > > - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > > - &cpu2intc 3 &cpu2intc 7 > > - &cpu3intc 3 &cpu3intc 7 > > - &cpu4intc 3 &cpu4intc 7>; > > - reg = <0x2000000 0x10000>; > > + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, > > + <&cpu2intc 3>, <&cpu2intc 7>, > > + <&cpu3intc 3>, <&cpu3intc 7>, > > + <&cpu4intc 3>, <&cpu4intc 7>; > > + reg = <0x2000000 0x10000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > }; > > ... > > diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi > > index 5e8ca8142482..67dcda1efadb 100644 > > --- a/arch/riscv/boot/dts/canaan/k210.dtsi > > +++ b/arch/riscv/boot/dts/canaan/k210.dtsi > > @@ -105,6 +105,8 @@ clint0: timer@2000000 { > > reg = <0x2000000 0xC000>; > > interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > &cpu1_intc 3 &cpu1_intc 7>; > > + #interrupt-cells = <0>; > > + interrupt-controller; > > }; > > > > plic0: interrupt-controller@c000000 { > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > index b9819570a7d1..67fb41439f20 100644 > > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > @@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7 > > &cpu2_intc 3 &cpu2_intc 7 > > &cpu3_intc 3 &cpu3_intc 7 > > &cpu4_intc 3 &cpu4_intc 7>; > > + #interrupt-cells = <0>; > > + interrupt-controller; > > }; > > > > plic: interrupt-controller@c000000 { > > -- > > 2.25.1 > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A561C4320E for ; Wed, 1 Sep 2021 12:08:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35F9360FE6 for ; Wed, 1 Sep 2021 12:08:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 35F9360FE6 Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Sep 1, 2021 at 6:59 AM Rob Herring wrote: > > On Mon, Aug 30, 2021 at 09:47:24AM +0530, Anup Patel wrote: > > The Linux RISC-V now treats IPIs as regular per-CPU IRQs. This means > > we have to create a IPI interrupt domain to use CLINT IPI functionality > > hence requiring a "interrupt-controller" and "#interrupt-cells" DT > > property in CLINT DT nodes. > > > > Impact of this CLINT DT bindings change only affects Linux RISC-V > > NoMMU kernel and has no effect of existing M-mode runtime firmwares > > (i.e. OpenSBI). > > It appears to me you should fix Linux to not need these 2 useless > properties. I say useless because #interrupt-cells being 0 is pretty > useless. Linux IRQCHIP framework only probes IRQCHIP DT nodes which have "interrupt-controller" DT property. The "interrupt-cells" DT property can be removed because as an interrupt controller SiFive CLINT will only provide IPIs to arch code. Regards, Anup > > > > > Signed-off-by: Anup Patel > > --- > > .../bindings/timer/sifive,clint.yaml | 20 ++++++++++++++----- > > arch/riscv/boot/dts/canaan/k210.dtsi | 2 ++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 2 ++ > > 3 files changed, 19 insertions(+), 5 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > index a35952f48742..9c8ef9f4094f 100644 > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -43,6 +43,12 @@ properties: > > > > interrupts-extended: > > minItems: 1 > > + maxItems: 4095 > > + > > + "#interrupt-cells": > > + const: 0 > > + > > + interrupt-controller: true > > > > additionalProperties: false > > > > @@ -50,15 +56,19 @@ required: > > - compatible > > - reg > > - interrupts-extended > > + - interrupt-controller > > + - "#interrupt-cells" > > > > examples: > > - | > > timer@2000000 { > > compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > > - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > > - &cpu2intc 3 &cpu2intc 7 > > - &cpu3intc 3 &cpu3intc 7 > > - &cpu4intc 3 &cpu4intc 7>; > > - reg = <0x2000000 0x10000>; > > + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, > > + <&cpu2intc 3>, <&cpu2intc 7>, > > + <&cpu3intc 3>, <&cpu3intc 7>, > > + <&cpu4intc 3>, <&cpu4intc 7>; > > + reg = <0x2000000 0x10000>; > > + interrupt-controller; > > + #interrupt-cells = <0>; > > }; > > ... > > diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi > > index 5e8ca8142482..67dcda1efadb 100644 > > --- a/arch/riscv/boot/dts/canaan/k210.dtsi > > +++ b/arch/riscv/boot/dts/canaan/k210.dtsi > > @@ -105,6 +105,8 @@ clint0: timer@2000000 { > > reg = <0x2000000 0xC000>; > > interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > &cpu1_intc 3 &cpu1_intc 7>; > > + #interrupt-cells = <0>; > > + interrupt-controller; > > }; > > > > plic0: interrupt-controller@c000000 { > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > index b9819570a7d1..67fb41439f20 100644 > > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > @@ -168,6 +168,8 @@ &cpu1_intc 3 &cpu1_intc 7 > > &cpu2_intc 3 &cpu2_intc 7 > > &cpu3_intc 3 &cpu3_intc 7 > > &cpu4_intc 3 &cpu4_intc 7>; > > + #interrupt-cells = <0>; > > + interrupt-controller; > > }; > > > > plic: interrupt-controller@c000000 { > > -- > > 2.25.1 > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv