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Tue, 23 Nov 2021 00:04:01 -0800 (PST) MIME-Version: 1.0 References: <20211118083912.981995-1-atishp@rivosinc.com> <20211118083912.981995-5-atishp@rivosinc.com> In-Reply-To: <20211118083912.981995-5-atishp@rivosinc.com> From: Anup Patel Date: Tue, 23 Nov 2021 13:33:50 +0530 Message-ID: Subject: Re: [PATCH v5 4/5] RISC-V: KVM: Add v0.1 replacement SBI extensions defined in v02 To: Atish Patra Cc: "linux-kernel@vger.kernel.org List" , Atish Patra , Anup Patel , Albert Ou , Heinrich Schuchardt , Kefeng Wang , kvm-riscv@lists.infradead.org, KVM General , linux-riscv , Palmer Dabbelt , Paul Walmsley Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 18, 2021 at 2:10 PM Atish Patra wrote: > > From: Atish Patra > > The SBI v0.2 contains some of the improved versions of required v0.1 > extensions such as remote fence, timer and IPI. > > This patch implements those extensions. > > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > Signed-off-by: Atish Patra I have queued this for 5.17 Thanks, Anup > --- > arch/riscv/kvm/Makefile | 1 + > arch/riscv/kvm/vcpu_sbi.c | 7 ++ > arch/riscv/kvm/vcpu_sbi_replace.c | 133 ++++++++++++++++++++++++++++++ > 3 files changed, 141 insertions(+) > create mode 100644 arch/riscv/kvm/vcpu_sbi_replace.c > > diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile > index 84c02922a329..4757ae158bf3 100644 > --- a/arch/riscv/kvm/Makefile > +++ b/arch/riscv/kvm/Makefile > @@ -25,4 +25,5 @@ kvm-y += vcpu_switch.o > kvm-y += vcpu_sbi.o > kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o > kvm-y += vcpu_sbi_base.o > +kvm-y += vcpu_sbi_replace.o > kvm-y += vcpu_timer.o > diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c > index 915a044a0b4f..cf284e080f3e 100644 > --- a/arch/riscv/kvm/vcpu_sbi.c > +++ b/arch/riscv/kvm/vcpu_sbi.c > @@ -40,9 +40,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = { > }; > #endif > extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; > + > static const struct kvm_vcpu_sbi_extension *sbi_ext[] = { > &vcpu_sbi_ext_v01, > &vcpu_sbi_ext_base, > + &vcpu_sbi_ext_time, > + &vcpu_sbi_ext_ipi, > + &vcpu_sbi_ext_rfence, > }; > > void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run) > diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c > new file mode 100644 > index 000000000000..67a64db1efc9 > --- /dev/null > +++ b/arch/riscv/kvm/vcpu_sbi_replace.c > @@ -0,0 +1,133 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > + * > + * Authors: > + * Atish Patra > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int ret = 0; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + u64 next_cycle; > + > + if (cp->a6 != SBI_EXT_TIME_SET_TIMER) > + return -EINVAL; > + > +#if __riscv_xlen == 32 > + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; > +#else > + next_cycle = (u64)cp->a0; > +#endif > + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time = { > + .extid_start = SBI_EXT_TIME, > + .extid_end = SBI_EXT_TIME, > + .handler = kvm_sbi_ext_time_handler, > +}; > + > +static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int i, ret = 0; > + struct kvm_vcpu *tmp; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + unsigned long hmask = cp->a0; > + unsigned long hbase = cp->a1; > + > + if (cp->a6 != SBI_EXT_IPI_SEND_IPI) > + return -EINVAL; > + > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > + if (hbase != -1UL) { > + if (tmp->vcpu_id < hbase) > + continue; > + if (!(hmask & (1UL << (tmp->vcpu_id - hbase)))) > + continue; > + } > + ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); > + if (ret < 0) > + break; > + } > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi = { > + .extid_start = SBI_EXT_IPI, > + .extid_end = SBI_EXT_IPI, > + .handler = kvm_sbi_ext_ipi_handler, > +}; > + > +static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int i, ret = 0; > + struct cpumask cm, hm; > + struct kvm_vcpu *tmp; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + unsigned long hmask = cp->a0; > + unsigned long hbase = cp->a1; > + unsigned long funcid = cp->a6; > + > + cpumask_clear(&cm); > + cpumask_clear(&hm); > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > + if (hbase != -1UL) { > + if (tmp->vcpu_id < hbase) > + continue; > + if (!(hmask & (1UL << (tmp->vcpu_id - hbase)))) > + continue; > + } > + if (tmp->cpu < 0) > + continue; > + cpumask_set_cpu(tmp->cpu, &cm); > + } > + > + riscv_cpuid_to_hartid_mask(&cm, &hm); > + > + switch (funcid) { > + case SBI_EXT_RFENCE_REMOTE_FENCE_I: > + ret = sbi_remote_fence_i(cpumask_bits(&hm)); > + break; > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: > + ret = sbi_remote_hfence_vvma(cpumask_bits(&hm), cp->a2, cp->a3); > + break; > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: > + ret = sbi_remote_hfence_vvma_asid(cpumask_bits(&hm), cp->a2, > + cp->a3, cp->a4); > + break; > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID: > + /* TODO: implement for nested hypervisor case */ > + default: > + ret = -EOPNOTSUPP; > + } > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence = { > + .extid_start = SBI_EXT_RFENCE, > + .extid_end = SBI_EXT_RFENCE, > + .handler = kvm_sbi_ext_rfence_handler, > +}; > -- > 2.33.1 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0237DC433EF for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Nov 18, 2021 at 2:10 PM Atish Patra wrote: > > From: Atish Patra > > The SBI v0.2 contains some of the improved versions of required v0.1 > extensions such as remote fence, timer and IPI. > > This patch implements those extensions. > > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > Signed-off-by: Atish Patra I have queued this for 5.17 Thanks, Anup > --- > arch/riscv/kvm/Makefile | 1 + > arch/riscv/kvm/vcpu_sbi.c | 7 ++ > arch/riscv/kvm/vcpu_sbi_replace.c | 133 ++++++++++++++++++++++++++++++ > 3 files changed, 141 insertions(+) > create mode 100644 arch/riscv/kvm/vcpu_sbi_replace.c > > diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile > index 84c02922a329..4757ae158bf3 100644 > --- a/arch/riscv/kvm/Makefile > +++ b/arch/riscv/kvm/Makefile > @@ -25,4 +25,5 @@ kvm-y += vcpu_switch.o > kvm-y += vcpu_sbi.o > kvm-$(CONFIG_RISCV_SBI_V01) += vcpu_sbi_v01.o > kvm-y += vcpu_sbi_base.o > +kvm-y += vcpu_sbi_replace.o > kvm-y += vcpu_timer.o > diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c > index 915a044a0b4f..cf284e080f3e 100644 > --- a/arch/riscv/kvm/vcpu_sbi.c > +++ b/arch/riscv/kvm/vcpu_sbi.c > @@ -40,9 +40,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 = { > }; > #endif > extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi; > +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; > + > static const struct kvm_vcpu_sbi_extension *sbi_ext[] = { > &vcpu_sbi_ext_v01, > &vcpu_sbi_ext_base, > + &vcpu_sbi_ext_time, > + &vcpu_sbi_ext_ipi, > + &vcpu_sbi_ext_rfence, > }; > > void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run) > diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c > new file mode 100644 > index 000000000000..67a64db1efc9 > --- /dev/null > +++ b/arch/riscv/kvm/vcpu_sbi_replace.c > @@ -0,0 +1,133 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > + * > + * Authors: > + * Atish Patra > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int ret = 0; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + u64 next_cycle; > + > + if (cp->a6 != SBI_EXT_TIME_SET_TIMER) > + return -EINVAL; > + > +#if __riscv_xlen == 32 > + next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0; > +#else > + next_cycle = (u64)cp->a0; > +#endif > + kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time = { > + .extid_start = SBI_EXT_TIME, > + .extid_end = SBI_EXT_TIME, > + .handler = kvm_sbi_ext_time_handler, > +}; > + > +static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int i, ret = 0; > + struct kvm_vcpu *tmp; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + unsigned long hmask = cp->a0; > + unsigned long hbase = cp->a1; > + > + if (cp->a6 != SBI_EXT_IPI_SEND_IPI) > + return -EINVAL; > + > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > + if (hbase != -1UL) { > + if (tmp->vcpu_id < hbase) > + continue; > + if (!(hmask & (1UL << (tmp->vcpu_id - hbase)))) > + continue; > + } > + ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); > + if (ret < 0) > + break; > + } > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi = { > + .extid_start = SBI_EXT_IPI, > + .extid_end = SBI_EXT_IPI, > + .handler = kvm_sbi_ext_ipi_handler, > +}; > + > +static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, > + unsigned long *out_val, > + struct kvm_cpu_trap *utrap, bool *exit) > +{ > + int i, ret = 0; > + struct cpumask cm, hm; > + struct kvm_vcpu *tmp; > + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; > + unsigned long hmask = cp->a0; > + unsigned long hbase = cp->a1; > + unsigned long funcid = cp->a6; > + > + cpumask_clear(&cm); > + cpumask_clear(&hm); > + kvm_for_each_vcpu(i, tmp, vcpu->kvm) { > + if (hbase != -1UL) { > + if (tmp->vcpu_id < hbase) > + continue; > + if (!(hmask & (1UL << (tmp->vcpu_id - hbase)))) > + continue; > + } > + if (tmp->cpu < 0) > + continue; > + cpumask_set_cpu(tmp->cpu, &cm); > + } > + > + riscv_cpuid_to_hartid_mask(&cm, &hm); > + > + switch (funcid) { > + case SBI_EXT_RFENCE_REMOTE_FENCE_I: > + ret = sbi_remote_fence_i(cpumask_bits(&hm)); > + break; > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: > + ret = sbi_remote_hfence_vvma(cpumask_bits(&hm), cp->a2, cp->a3); > + break; > + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: > + ret = sbi_remote_hfence_vvma_asid(cpumask_bits(&hm), cp->a2, > + cp->a3, cp->a4); > + break; > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA: > + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID: > + /* TODO: implement for nested hypervisor case */ > + default: > + ret = -EOPNOTSUPP; > + } > + > + return ret; > +} > + > +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence = { > + .extid_start = SBI_EXT_RFENCE, > + .extid_end = SBI_EXT_RFENCE, > + .handler = kvm_sbi_ext_rfence_handler, > +}; > -- > 2.33.1 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv