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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, May 8, 2022 at 9:46 PM Jisheng Zhang wrote: > > This is to use the unified cpus_have_{final|const}_cap() instead of > putting static key related here and there. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/cpufeature.h | 5 +++++ > arch/riscv/include/asm/switch_to.h | 9 ++------- > arch/riscv/kernel/cpufeature.c | 8 ++------ > arch/riscv/kernel/process.c | 2 +- > arch/riscv/kernel/signal.c | 4 ++-- > 5 files changed, 12 insertions(+), 16 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index d80ddd2f3b49..634a653c7fa2 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -91,4 +91,9 @@ static inline void cpus_set_cap(unsigned int num) > } > } > > +static inline bool system_supports_fpu(void) > +{ > + return IS_ENABLED(CONFIG_FPU) && !cpus_have_final_cap(RISCV_HAS_NO_FPU); This should be checking for "f" and "d" ISA extensions since "FPU" is not an ISA extension name. > +} > + > #endif > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > index 0a3f4f95c555..362cb18d12d5 100644 > --- a/arch/riscv/include/asm/switch_to.h > +++ b/arch/riscv/include/asm/switch_to.h > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -56,13 +57,7 @@ static inline void __switch_to_aux(struct task_struct *prev, > fstate_restore(next, task_pt_regs(next)); > } > > -extern struct static_key_false cpu_hwcap_fpu; > -static __always_inline bool has_fpu(void) > -{ > - return static_branch_likely(&cpu_hwcap_fpu); > -} > #else > -static __always_inline bool has_fpu(void) { return false; } > #define fstate_save(task, regs) do { } while (0) > #define fstate_restore(task, regs) do { } while (0) > #define __switch_to_aux(__prev, __next) do { } while (0) > @@ -75,7 +70,7 @@ extern struct task_struct *__switch_to(struct task_struct *, > do { \ > struct task_struct *__prev = (prev); \ > struct task_struct *__next = (next); \ > - if (has_fpu()) \ > + if (system_supports_fpu()) \ > __switch_to_aux(__prev, __next); \ > ((last) = __switch_to(__prev, __next)); \ > } while (0) > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index e6c72cad0c1c..1edf3c3f8f62 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -22,10 +22,6 @@ unsigned long elf_hwcap __read_mostly; > /* Host ISA bitmap */ > static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > -#ifdef CONFIG_FPU > -__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > -#endif > - > DECLARE_BITMAP(cpu_hwcaps, RISCV_NCAPS); > EXPORT_SYMBOL(cpu_hwcaps); > > @@ -254,8 +250,8 @@ void __init riscv_fill_hwcap(void) > pr_info("riscv: ELF capabilities %s\n", print_str); > > #ifdef CONFIG_FPU > - if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > - static_branch_enable(&cpu_hwcap_fpu); > + if (!(elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))) > + cpus_set_cap(RISCV_HAS_NO_FPU); > #endif > enable_cpu_capabilities(); > static_branch_enable(&riscv_const_caps_ready); > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c > index 504b496787aa..c9cd0b42299e 100644 > --- a/arch/riscv/kernel/process.c > +++ b/arch/riscv/kernel/process.c > @@ -88,7 +88,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, > unsigned long sp) > { > regs->status = SR_PIE; > - if (has_fpu()) { > + if (system_supports_fpu()) { > regs->status |= SR_FS_INITIAL; > /* > * Restore the initial value to the FP register > diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c > index 9f4e59f80551..96aa593a989e 100644 > --- a/arch/riscv/kernel/signal.c > +++ b/arch/riscv/kernel/signal.c > @@ -90,7 +90,7 @@ static long restore_sigcontext(struct pt_regs *regs, > /* sc_regs is structured the same as the start of pt_regs */ > err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); > /* Restore the floating-point state. */ > - if (has_fpu()) > + if (system_supports_fpu()) > err |= restore_fp_state(regs, &sc->sc_fpregs); > return err; > } > @@ -143,7 +143,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, > /* sc_regs is structured the same as the start of pt_regs */ > err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); > /* Save the floating-point state. */ > - if (has_fpu()) > + if (system_supports_fpu()) > err |= save_fp_state(regs, &sc->sc_fpregs); > return err; > } > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55F5CC433FE for ; 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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 8, 2022 at 9:46 PM Jisheng Zhang wrote: > > This is to use the unified cpus_have_{final|const}_cap() instead of > putting static key related here and there. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/cpufeature.h | 5 +++++ > arch/riscv/include/asm/switch_to.h | 9 ++------- > arch/riscv/kernel/cpufeature.c | 8 ++------ > arch/riscv/kernel/process.c | 2 +- > arch/riscv/kernel/signal.c | 4 ++-- > 5 files changed, 12 insertions(+), 16 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index d80ddd2f3b49..634a653c7fa2 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -91,4 +91,9 @@ static inline void cpus_set_cap(unsigned int num) > } > } > > +static inline bool system_supports_fpu(void) > +{ > + return IS_ENABLED(CONFIG_FPU) && !cpus_have_final_cap(RISCV_HAS_NO_FPU); This should be checking for "f" and "d" ISA extensions since "FPU" is not an ISA extension name. > +} > + > #endif > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > index 0a3f4f95c555..362cb18d12d5 100644 > --- a/arch/riscv/include/asm/switch_to.h > +++ b/arch/riscv/include/asm/switch_to.h > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -56,13 +57,7 @@ static inline void __switch_to_aux(struct task_struct *prev, > fstate_restore(next, task_pt_regs(next)); > } > > -extern struct static_key_false cpu_hwcap_fpu; > -static __always_inline bool has_fpu(void) > -{ > - return static_branch_likely(&cpu_hwcap_fpu); > -} > #else > -static __always_inline bool has_fpu(void) { return false; } > #define fstate_save(task, regs) do { } while (0) > #define fstate_restore(task, regs) do { } while (0) > #define __switch_to_aux(__prev, __next) do { } while (0) > @@ -75,7 +70,7 @@ extern struct task_struct *__switch_to(struct task_struct *, > do { \ > struct task_struct *__prev = (prev); \ > struct task_struct *__next = (next); \ > - if (has_fpu()) \ > + if (system_supports_fpu()) \ > __switch_to_aux(__prev, __next); \ > ((last) = __switch_to(__prev, __next)); \ > } while (0) > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index e6c72cad0c1c..1edf3c3f8f62 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -22,10 +22,6 @@ unsigned long elf_hwcap __read_mostly; > /* Host ISA bitmap */ > static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > -#ifdef CONFIG_FPU > -__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > -#endif > - > DECLARE_BITMAP(cpu_hwcaps, RISCV_NCAPS); > EXPORT_SYMBOL(cpu_hwcaps); > > @@ -254,8 +250,8 @@ void __init riscv_fill_hwcap(void) > pr_info("riscv: ELF capabilities %s\n", print_str); > > #ifdef CONFIG_FPU > - if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > - static_branch_enable(&cpu_hwcap_fpu); > + if (!(elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))) > + cpus_set_cap(RISCV_HAS_NO_FPU); > #endif > enable_cpu_capabilities(); > static_branch_enable(&riscv_const_caps_ready); > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c > index 504b496787aa..c9cd0b42299e 100644 > --- a/arch/riscv/kernel/process.c > +++ b/arch/riscv/kernel/process.c > @@ -88,7 +88,7 @@ void start_thread(struct pt_regs *regs, unsigned long pc, > unsigned long sp) > { > regs->status = SR_PIE; > - if (has_fpu()) { > + if (system_supports_fpu()) { > regs->status |= SR_FS_INITIAL; > /* > * Restore the initial value to the FP register > diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c > index 9f4e59f80551..96aa593a989e 100644 > --- a/arch/riscv/kernel/signal.c > +++ b/arch/riscv/kernel/signal.c > @@ -90,7 +90,7 @@ static long restore_sigcontext(struct pt_regs *regs, > /* sc_regs is structured the same as the start of pt_regs */ > err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); > /* Restore the floating-point state. */ > - if (has_fpu()) > + if (system_supports_fpu()) > err |= restore_fp_state(regs, &sc->sc_fpregs); > return err; > } > @@ -143,7 +143,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, > /* sc_regs is structured the same as the start of pt_regs */ > err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); > /* Save the floating-point state. */ > - if (has_fpu()) > + if (system_supports_fpu()) > err |= save_fp_state(regs, &sc->sc_fpregs); > return err; > } > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup