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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang wrote: > > Only support supervisor external interrupt currently. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > hw/intc/sifive_plic.c | 29 ++++++++++++++++++++--------- > target/riscv/kvm-stub.c | 5 +++++ > target/riscv/kvm.c | 20 ++++++++++++++++++++ > target/riscv/kvm_riscv.h | 1 + > 4 files changed, 46 insertions(+), 9 deletions(-) > > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c > index 97a1a27a9a..2746eb7a05 100644 > --- a/hw/intc/sifive_plic.c > +++ b/hw/intc/sifive_plic.c > @@ -31,6 +31,8 @@ > #include "target/riscv/cpu.h" > #include "sysemu/sysemu.h" > #include "migration/vmstate.h" > +#include "sysemu/kvm.h" > +#include "kvm_riscv.h" > > #define RISCV_DEBUG_PLIC 0 > > @@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic) > continue; > } > int level = sifive_plic_irqs_pending(plic, addrid); > - switch (mode) { > - case PLICMode_M: > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); > - break; > - case PLICMode_S: > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); > - break; > - default: > - break; > + if (kvm_enabled()) { > + if (mode == PLICMode_M) { > + continue; > + } > + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level); > + } else { > + switch (mode) { > + case PLICMode_M: > + riscv_cpu_update_mip(RISCV_CPU(cpu), > + MIP_MEIP, BOOL_TO_MASK(level)); > + break; > + case PLICMode_S: > + riscv_cpu_update_mip(RISCV_CPU(cpu), > + MIP_SEIP, BOOL_TO_MASK(level)); > + break; > + default: > + break; > + } I am not comfortable with this patch. This way we will endup calling kvm_riscv_set_irq() from various places in hw/intc and hw/riscv. I suggest to extend riscv_cpu_update_mip() such that when kvm is enabled riscv_cpu_update_mip() will: 1) Consider only MIP_SEIP bit in "mask" parameter and all other bits in "mask" parameter will be ignored probably with warning 2) When the MIP_SEIP bit is set in "mask" call kvm_riscv_set_irq() to change the IRQ state in the KVM module. Regards, Anup > } > } > > diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c > index 39b96fe3f4..4e8fc31a21 100644 > --- a/target/riscv/kvm-stub.c > +++ b/target/riscv/kvm-stub.c > @@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > { > abort(); > } > + > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > +{ > + abort(); > +} > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 79c931acb4..da63535812 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->gpr[11] = cpu->env.fdt_addr; /* a1 */ > } > > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > +{ > + int ret; > + unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; > + > + if (irq != IRQ_S_EXT) { > + return; > + } > + > + if (!kvm_enabled()) { > + return; > + } > + > + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); > + if (ret < 0) { > + perror("Set irq failed"); > + abort(); > + } > +} > + > bool kvm_arch_cpu_check_are_resettable(void) > { > return true; > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h > index f38c82bf59..ed281bdce0 100644 > --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -20,5 +20,6 @@ > #define QEMU_KVM_RISCV_H > > void kvm_riscv_reset_vcpu(RISCVCPU *cpu); > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); > > #endif > -- > 2.19.1 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 236A9C433B4 for ; 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charset="UTF-8" Received-SPF: none client-ip=2a00:1450:4864:20::32c; envelope-from=anup@brainfault.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , "open list:RISC-V" , Sagar Karandikar , KVM General , libvir-list@redhat.com, Bastian Koppelmann , Anup Patel , QEMU Developers , yinyipeng , Palmer Dabbelt , kvm-riscv@lists.infradead.org, Alistair Francis , fanliang@huawei.com, "Wubin \(H\)" , Zhanghailiang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Apr 12, 2021 at 12:24 PM Yifei Jiang wrote: > > Only support supervisor external interrupt currently. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > hw/intc/sifive_plic.c | 29 ++++++++++++++++++++--------- > target/riscv/kvm-stub.c | 5 +++++ > target/riscv/kvm.c | 20 ++++++++++++++++++++ > target/riscv/kvm_riscv.h | 1 + > 4 files changed, 46 insertions(+), 9 deletions(-) > > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c > index 97a1a27a9a..2746eb7a05 100644 > --- a/hw/intc/sifive_plic.c > +++ b/hw/intc/sifive_plic.c > @@ -31,6 +31,8 @@ > #include "target/riscv/cpu.h" > #include "sysemu/sysemu.h" > #include "migration/vmstate.h" > +#include "sysemu/kvm.h" > +#include "kvm_riscv.h" > > #define RISCV_DEBUG_PLIC 0 > > @@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic) > continue; > } > int level = sifive_plic_irqs_pending(plic, addrid); > - switch (mode) { > - case PLICMode_M: > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level)); > - break; > - case PLICMode_S: > - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level)); > - break; > - default: > - break; > + if (kvm_enabled()) { > + if (mode == PLICMode_M) { > + continue; > + } > + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level); > + } else { > + switch (mode) { > + case PLICMode_M: > + riscv_cpu_update_mip(RISCV_CPU(cpu), > + MIP_MEIP, BOOL_TO_MASK(level)); > + break; > + case PLICMode_S: > + riscv_cpu_update_mip(RISCV_CPU(cpu), > + MIP_SEIP, BOOL_TO_MASK(level)); > + break; > + default: > + break; > + } I am not comfortable with this patch. This way we will endup calling kvm_riscv_set_irq() from various places in hw/intc and hw/riscv. I suggest to extend riscv_cpu_update_mip() such that when kvm is enabled riscv_cpu_update_mip() will: 1) Consider only MIP_SEIP bit in "mask" parameter and all other bits in "mask" parameter will be ignored probably with warning 2) When the MIP_SEIP bit is set in "mask" call kvm_riscv_set_irq() to change the IRQ state in the KVM module. Regards, Anup > } > } > > diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c > index 39b96fe3f4..4e8fc31a21 100644 > --- a/target/riscv/kvm-stub.c > +++ b/target/riscv/kvm-stub.c > @@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > { > abort(); > } > + > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > +{ > + abort(); > +} > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 79c931acb4..da63535812 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->gpr[11] = cpu->env.fdt_addr; /* a1 */ > } > > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > +{ > + int ret; > + unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; > + > + if (irq != IRQ_S_EXT) { > + return; > + } > + > + if (!kvm_enabled()) { > + return; > + } > + > + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); > + if (ret < 0) { > + perror("Set irq failed"); > + abort(); > + } > +} > + > bool kvm_arch_cpu_check_are_resettable(void) > { > return true; > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h > index f38c82bf59..ed281bdce0 100644 > --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -20,5 +20,6 @@ > #define QEMU_KVM_RISCV_H > > void kvm_riscv_reset_vcpu(RISCVCPU *cpu); > +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); > > #endif > -- > 2.19.1 > > > -- > kvm-riscv mailing list > kvm-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/kvm-riscv