From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E60D4C433EF for ; Mon, 18 Oct 2021 04:33:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7A206127C for ; Mon, 18 Oct 2021 04:33:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229707AbhJREf3 (ORCPT ); Mon, 18 Oct 2021 00:35:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229453AbhJREf2 (ORCPT ); Mon, 18 Oct 2021 00:35:28 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8937C06161C for ; Sun, 17 Oct 2021 21:33:17 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id o20so38941004wro.3 for ; Sun, 17 Oct 2021 21:33:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FtUBtWA90x+Pb9HFP4uoXiLc4o2TxeGhqR6fwQbYKb8=; b=8FITqn9K5KfRz8Ss1x15c/E4gIyXjugA04x7iNdNUejiXgz2555yzSJAAogSzeqS7q q7PQ64fPTE7OmgI+KE4+63vBXNG4t75ylGCguocaJ6W9ts3/Z1BzDET5FIoc2I0p573S nMV1YdamHEgyQ8bjZKH1qaKYLQpK/1souUpEJWopgjAFcAIaKWe90l9Yg/iheEyLtPaO nXfg1S4L/hDNCIp7SPKlZHganpou+0uiJ/IhRAu8zr1ObxfsGE2/es/iP0LCvWlVHVW+ 1tkyy3NLORkCqIBvtpdUCdzdyiHfetUE4MxNWl8QmpFlJYamaRoNqlJfWNs1c0s3QA7f 2WuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FtUBtWA90x+Pb9HFP4uoXiLc4o2TxeGhqR6fwQbYKb8=; b=ISJw37ZuXfYbEXT01hjwKKXkI7M50qsxrEO4ORCjEKg8nTZbyo+3IzexgRJbVgc6Yf vqWPSFh3vCa966p1Wzr2q23TLpZLLl/dpxvA/upF7H6V7A+Xkykzd9yGKRm6/sW4RtgQ OWeoUGAQPRdxLEJtwfwJX0gRN140cMxoH9Z8VB2pxLlPzOTLMdgYMJTvDMWKth6WCzln SnD8LFKir/RZ1YareSn0ZY9KhTmbg/jq+/38I5H7+ZLCPjxlCjuxjFiNjoMxR9aPwWw0 L0LD7xZ9YSi22E7RXeeqIYn6wAqQYsXP065v+qRl6pBWPzl3/mQopHevveeKqvubx+cw XvNg== X-Gm-Message-State: AOAM531L91G8uViwAJvCT88GQrGj0+W7CNXgyVgr2Xw51pLwTHZm3mqm o9TCxiKkCfvZ+r7M/zGCNF/e8ndEZeR/9AXdQQ9jDg== X-Google-Smtp-Source: ABdhPJydk0ydbDmFLt6u8ok8LYEytDSxAqGGTqx/OVzL0U1AcEhdOHzFxvIrItXho4WDm+C9oH+N3RJyq1U48OoRJwM= X-Received: by 2002:a5d:6dce:: with SMTP id d14mr32967521wrz.363.1634531595601; Sun, 17 Oct 2021 21:33:15 -0700 (PDT) MIME-Version: 1.0 References: <20211015120735.27972-1-heinrich.schuchardt@canonical.com> In-Reply-To: <20211015120735.27972-1-heinrich.schuchardt@canonical.com> From: Anup Patel Date: Mon, 18 Oct 2021 10:03:04 +0530 Message-ID: Subject: Re: [PATCH v2 1/1] dt-bindings: reg-io-width for SiFive CLINT To: Heinrich Schuchardt Cc: Daniel Lezcano , Thomas Gleixner , Guo Ren , Bin Meng , Xiang W , Samuel Holland , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Anup Patel , "linux-kernel@vger.kernel.org List" , DTML , linux-riscv , OpenSBI Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 15, 2021 at 5:37 PM Heinrich Schuchardt wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > Add a new compatible string "allwinner,sun20i-d1-clint" for the CLINT of > the Allwinner D1 SoC. > > Signed-off-by: Heinrich Schuchardt > --- > .../devicetree/bindings/timer/sifive,clint.yaml | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..d3b4c6844e2f 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -26,6 +26,7 @@ properties: > - enum: > - sifive,fu540-c000-clint > - canaan,k210-clint > + - allwinner,sun20i-d1-clint > - const: sifive,clint0 > > description: > @@ -33,14 +34,22 @@ properties: > Supported compatible strings are - > "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive > - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and > - "sifive,clint0" for the SiFive CLINT v0 IP block with no chip > + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, > + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC, > + and "sifive,clint0" for the SiFive CLINT v0 IP block with no chip > integration tweaks. > Please refer to sifive-blocks-ip-versioning.txt for details > > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + Please drop the "reg-io-width" DT property. Based on discussion on ACLINT MTIMER DT bindings, Rob suggested using implementation specific compatible string for detecting register IO width. We should follow the same strategy here as well. Regards, Anup > interrupts-extended: > minItems: 1 > > -- > 2.32.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BF15C433F5 for ; Mon, 18 Oct 2021 04:33:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29BAE610E8 for ; Mon, 18 Oct 2021 04:33:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 29BAE610E8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Sun, 17 Oct 2021 21:33:15 -0700 (PDT) MIME-Version: 1.0 References: <20211015120735.27972-1-heinrich.schuchardt@canonical.com> In-Reply-To: <20211015120735.27972-1-heinrich.schuchardt@canonical.com> From: Anup Patel Date: Mon, 18 Oct 2021 10:03:04 +0530 Message-ID: Subject: Re: [PATCH v2 1/1] dt-bindings: reg-io-width for SiFive CLINT To: Heinrich Schuchardt Cc: Daniel Lezcano , Thomas Gleixner , Guo Ren , Bin Meng , Xiang W , Samuel Holland , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Anup Patel , "linux-kernel@vger.kernel.org List" , DTML , linux-riscv , OpenSBI X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211017_213317_637259_AEA63DE4 X-CRM114-Status: GOOD ( 23.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Oct 15, 2021 at 5:37 PM Heinrich Schuchardt wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > Add a new compatible string "allwinner,sun20i-d1-clint" for the CLINT of > the Allwinner D1 SoC. > > Signed-off-by: Heinrich Schuchardt > --- > .../devicetree/bindings/timer/sifive,clint.yaml | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..d3b4c6844e2f 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -26,6 +26,7 @@ properties: > - enum: > - sifive,fu540-c000-clint > - canaan,k210-clint > + - allwinner,sun20i-d1-clint > - const: sifive,clint0 > > description: > @@ -33,14 +34,22 @@ properties: > Supported compatible strings are - > "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive > - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and > - "sifive,clint0" for the SiFive CLINT v0 IP block with no chip > + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, > + "allwinner,sun20i-d1-clint" for the CLINT in the Allwinner D1 SoC, > + and "sifive,clint0" for the SiFive CLINT v0 IP block with no chip > integration tweaks. > Please refer to sifive-blocks-ip-versioning.txt for details > > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + Please drop the "reg-io-width" DT property. Based on discussion on ACLINT MTIMER DT bindings, Rob suggested using implementation specific compatible string for detecting register IO width. We should follow the same strategy here as well. Regards, Anup > interrupts-extended: > minItems: 1 > > -- > 2.32.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv