From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2870C433DB for ; Mon, 11 Jan 2021 04:01:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E2B522473 for ; Mon, 11 Jan 2021 04:01:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727237AbhAKEAz (ORCPT ); Sun, 10 Jan 2021 23:00:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726362AbhAKEAz (ORCPT ); Sun, 10 Jan 2021 23:00:55 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AED67C061786 for ; Sun, 10 Jan 2021 20:00:14 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id n8so2019126ljg.3 for ; Sun, 10 Jan 2021 20:00:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aHEcr4bSN1zx2FiEMYBhMzgQIQxqAhuq0PemUwVcZMc=; b=17Yxy068PsRgBYF8Z92oLby9dxH4xCw0G3KUSVK5aO7ukRRPstyXKGXxnHINqOemMp bU+NJ7KZAgJRAVo1zy+w+gzx0dM0gHBT+TQt0yxMMgKCsw5tPTwi5KdwHDmcU01JhPNV Bq9F+wWEQQ5tV7c9UmvAI+X3CWzL3R0e2Vo4y/OJhC+Q/1amaASVE7w5mH5k+bbFG1jA wRgBprCrTIrNPjuO56ZRm3Vjyv4ZJsDDjbmGyCJXoMCA2T0TBPAWe+/DQKLeJZ+CIrJP 7gPBedFvoO6wG3diINpIwu3pGaOmD8MLRNwJOiAvB/SGca5vL0Y3LUbVHbfy/laplQwT s0PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aHEcr4bSN1zx2FiEMYBhMzgQIQxqAhuq0PemUwVcZMc=; b=YAlgsdMh6zSm3OmPkLWpgXfcRGcaEZoKyUYfABPOrDrU8BUNpzc+JTFCA0s+ynjgGz ytnOOTQzqw0UMay8wSz97eJ+xFD2iF7Recf32xy/0n8DlLWLSS+alDA3UKrHSk+Yxmjs UPO50VINSOCq3ZCvJuMIP6kDLhiz7zxsbJJFaqv4TzRMibvi824A/M8Iw3WPT9L2Q/0m p7T0HTNw8yQOYarfCLCwBZBU/rsk1sVx7VkatYNlM8lu6+mOuBC8aG7se58CZUoK77h+ E7vUK7gKTIXQeDkKYSTmAAZcTHcTNcmutaO+R3uIZH2F/fABfIWTDW3QOXaeko2x7Sac BA8g== X-Gm-Message-State: AOAM532afrUK+XLvTTcbFZxN6gKg5zYPzvkYzVPrm4QG6M9gUli4ZGus DhOrlrr+oHc1ZOoHV35PKZWVi12QB+wGczNHCs6w5A== X-Google-Smtp-Source: ABdhPJx0b8YVu7rdN1I7HqOu9IoKI4q9eHnmGHiqxjmUPNYuhHmSXBuJjGwjX9ZjFoRWPWz4LF2jbblYZ1gYh8hSE7c= X-Received: by 2002:a05:651c:202:: with SMTP id y2mr6385586ljn.162.1610337613243; Sun, 10 Jan 2021 20:00:13 -0800 (PST) MIME-Version: 1.0 References: <20210107092652.3438696-1-atish.patra@wdc.com> <20210107092652.3438696-4-atish.patra@wdc.com> In-Reply-To: <20210107092652.3438696-4-atish.patra@wdc.com> From: Anup Patel Date: Mon, 11 Jan 2021 09:30:01 +0530 Message-ID: Subject: Re: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 To: Atish Patra Cc: "linux-kernel@vger.kernel.org List" , Albert Ou , Anup Patel , linux-riscv , Palmer Dabbelt , Paul Walmsley , Nick Kossifidis , Andrew Morton , Ard Biesheuvel , Mike Rapoport Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 7, 2021 at 2:57 PM Atish Patra wrote: > > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock > allocation if it is requested to be aligned with SMP_CACHE_BYTES. > > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel > --- > arch/riscv/include/asm/cache.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > index 9b58b104559e..c9c669ea2fe6 100644 > --- a/arch/riscv/include/asm/cache.h > +++ b/arch/riscv/include/asm/cache.h > @@ -7,7 +7,11 @@ > #ifndef _ASM_RISCV_CACHE_H > #define _ASM_RISCV_CACHE_H > > +#ifdef CONFIG_64BIT > #define L1_CACHE_SHIFT 6 > +#else > +#define L1_CACHE_SHIFT 5 > +#endif > > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A9EDC433DB for ; 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Sun, 10 Jan 2021 20:00:13 -0800 (PST) MIME-Version: 1.0 References: <20210107092652.3438696-1-atish.patra@wdc.com> <20210107092652.3438696-4-atish.patra@wdc.com> In-Reply-To: <20210107092652.3438696-4-atish.patra@wdc.com> From: Anup Patel Date: Mon, 11 Jan 2021 09:30:01 +0530 Message-ID: Subject: Re: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 To: Atish Patra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210110_230014_708559_BD9D88A1 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Anup Patel , "linux-kernel@vger.kernel.org List" , Ard Biesheuvel , Palmer Dabbelt , Paul Walmsley , Nick Kossifidis , linux-riscv , Andrew Morton , Mike Rapoport Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jan 7, 2021 at 2:57 PM Atish Patra wrote: > > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock > allocation if it is requested to be aligned with SMP_CACHE_BYTES. > > Signed-off-by: Atish Patra Looks good to me. Reviewed-by: Anup Patel > --- > arch/riscv/include/asm/cache.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > index 9b58b104559e..c9c669ea2fe6 100644 > --- a/arch/riscv/include/asm/cache.h > +++ b/arch/riscv/include/asm/cache.h > @@ -7,7 +7,11 @@ > #ifndef _ASM_RISCV_CACHE_H > #define _ASM_RISCV_CACHE_H > > +#ifdef CONFIG_64BIT > #define L1_CACHE_SHIFT 6 > +#else > +#define L1_CACHE_SHIFT 5 > +#endif > > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv